aboutsummaryrefslogtreecommitdiffstats
path: root/arch/sh/include/cpu-sh4 (follow)
AgeCommit message (Collapse)AuthorFilesLines
2010-01-16sh: New extended page flag to wire/unwire TLB entriesMatt Fleming1-0/+4
Provide a new extended page flag, _PAGE_WIRED and an SH4 implementation for wiring TLB entries and use it in the fixmap code path so that we can wire the fixmap TLB entry. Signed-off-by: Matt Fleming <matt@console-pimps.org>
2010-01-05sh: Kill off dead UBC headers.Paul Mundt1-64/+0
Nothing is using these now, so kill them all off. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-12-17sh: dmaengine support for sh7724.Guennadi Liakhovetski1-4/+4
Add a dmaengine platform device to sh7724, fix DMA channel interrupt numbers. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-10-27sh: fix watchdog timer for sh7780/sh7785Valentin R Sitsikov1-0/+13
Signed-off-by: Valentin Sitdikov <valentin.sitdikov@siemens.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-09-01Merge branch 'master' into sh/smpPaul Mundt2-0/+247
Conflicts: arch/sh/mm/cache-sh4.c
2009-08-21sh: Add initial support for SH7757 CPU subtypeYoshihiro Shimoda2-0/+247
Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-08-15sh: Migrate SH-4 cacheflush ops to function pointers.Paul Mundt1-31/+0
This paves the way for allowing individual CPUs to overload the individual flushing routines that they care about without having to depend on weak aliases. SH-4 is converted over initially, as it wires up pretty much everything. The majority of the other CPUs will simply use the default no-op implementation with their own region flushers wired up. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-08-15sh: Kill off unused flush_icache_user_range().Paul Mundt1-2/+0
We use flush_cache_page() outright in copy_to_user_page(), and nothing else needs it, so just kill it off. SH-5 still defines its own version, but that too will go away in the same fashion once it converts over. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-08-15sh: consolidate flush_dcache_mmap_lock/unlock() definitions.Paul Mundt1-4/+0
All of the flush_dcache_mmap_lock()/flush_dcache_mmap_unlock() definitions are identical across all CPUs, so just provide them generically in asm/cacheflush.h. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-08-15sh: Don't export flush_dcache_all().Paul Mundt1-1/+0
flush_dcache_all() is used internally by the SH-4 cache code, it is not part of the exported cache API, so make it static and don't export it. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-08-15sh: Centralize the CPU cache initialization routines.Paul Mundt1-3/+0
This provides a central point for CPU cache initialization routines. This replaces the antiquated p3_cache_init() method, which the vast majority of CPUs never cared about. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-08-15sh: rework nommu for generic cache.c use.Paul Mundt1-2/+0
This does a bit of reorganizing for allowing nommu to use the new and generic cache.c, no functional changes. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-08-15Merge branch 'master' into sh/cachetlbPaul Mundt2-1/+19
2009-08-04sh: Add SH7724 DMAC support.Kuninori Morimoto1-1/+2
Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-08-04sh: hwblk support for sh7724Magnus Damm1-0/+17
This patch adds hwblk support for the sh7724 processor. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-07-22sh: Migrate from PG_mapped to PG_dcache_dirty.Paul Mundt1-1/+1
This inverts the delayed dcache flush a bit to be more in line with other platforms. At the same time this also gives us the ability to do some more optimizations and cleanup. Now that the update_mmu_cache() callsite only tests for the bit, the implementation can gradually be split out and made generic, rather than relying on special implementations for each of the peculiar CPU types. SH7705 in 32kB mode and SH-4 still need slightly different handling, but this is something that can remain isolated in the varying page copy/clear routines. On top of that, SH-X3 is dcache coherent, so there is no need to bother with any of these tests in the PTEAEX version of update_mmu_cache(), so we kill that off too. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-07-20sh: hwblk support for sh7723Magnus Damm1-0/+17
This patch adds hwblk support for the sh7723 processor. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-07-05sh: hwblk for sh7722Magnus Damm1-0/+14
This patch contains the sh7722 specific hwblk implementation. Hwblk ids are added to the processor specific header file, module stop bits and areas are kept track of as hwblks, clocks are converted to make use of the shared hwblk code. Code to determine allowed sleep modes is also added. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-06-11sh: sh7722 mode pin definitionsMagnus Damm1-0/+14
This patch adds sh7722 mode pin and pin function controller comments. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-06-11sh: sh7724 mode pin commentsMagnus Damm1-0/+14
This patch adds comments for the sh7724 mode pins and pin function controller. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-06-11sh: sh7723 mode pin V2Magnus Damm1-0/+14
This patch is sh7723 mode pin V2. Mode pins and pin function controller comments are added. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-06-11sh: rework mode pin codeMagnus Damm1-19/+20
This patch reworks the mode pin code to keep the pin definitions in one place. The mode pins values are now the value of the bit instead of bit number. With this patch in place the sh7785 header file contains mode pin comments. The sh7785 clock code and the sh7785lcr board code are updated to reflect the new shared mode pins. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-06-02sh: add RAMCR definition for sh4Kuninori Morimoto1-0/+2
Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-06-01sh: sh7785 mode pin definitionsMagnus Damm1-0/+24
This patch adds sh7785 mode pin definitions. Mode pins and pin function controller comments are added as well. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-05-12sh: remove old TMU driverMagnus Damm1-60/+0
This patch removes the old TMU driver (CONFIG_SH_TMU/timer-tmu.c) As replacement, select the sh_tmu driver with CONFIG_SH_TIMER_TMU and configure timer channel using platform data. If multiple TMU channels are enabled using platform data, use the earlytimer parameter on the kernel command line to select channel. For instance, use "earlytimer=sh_tmu.0" to select the first channel. To verify which timer is being used, look at printouts or the timer irq count in /proc/interrupts. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-04-16sh: Add support for SH7724 (SH-Mobile R2R) CPU subtype.Kuninori Morimoto2-0/+273
This implements initial support for the SH-Mobile R2R CPU. Based on Rev 0.11 of the initial SH7724 hardware manual. Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-03-31sh: Tidy up sh7786 pinmux table.Kuninori Morimoto1-135/+79
Formatting and typo fix. Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-03-17sh: Support for extended ASIDs on PTEAEX-capable SH-X3 cores.Paul Mundt1-19/+16
This adds support for extended ASIDs (up to 16-bits) on newer SH-X3 cores that implement the PTAEX register and respective functionality. Presently only the 65nm SH7786 (90nm only supports legacy 8-bit ASIDs). The main change is in how the PTE is written out when loading the entry in to the TLB, as well as in how the TLB entry is selectively flushed. While SH-X2 extended mode splits out the memory-mapped U and I-TLB data arrays for extra bits, extended ASID mode splits out the address arrays. While we don't use the memory-mapped data array access, the address array accesses are necessary for selective TLB flushes, so these are implemented newly and replace the generic SH-4 implementation. With this, TLB flushes in switch_mm() are almost non-existent on newer parts. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-03-10sh: dma-sh updates for multi IRQ and new SH-4A CPUs.Nobuhiro Iwamatsu3-55/+108
This adds DMA support for newer SH-4A CPUs, particularly SH7763/64/80/85. This also enables multi IRQ support for platforms that have multiple vectors bound to the same IRQ source. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-03-03sh: Add support for SH7786 CPU subtype.Kuninori Morimoto2-0/+196
This adds preliminary support for the SH7786 CPU subtype. While this is a dual-core CPU, only UP is supported for now. L2 cache support is likewise not yet implemented. More information on this particular CPU subtype is available at: http://www.renesas.com/fmwk.jsp?cnt=sh7786_root.jsp&fp=/products/mpumcu/superh_family/sh7780_series/sh7786_group/ Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-10-28sh: Add on-chip RTC support for SH7722.Paul Mundt1-1/+1
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-10-23sh: sh7785 pinmux supportMagnus Damm1-0/+234
This patch implements pinmux tables for the sh7785 processor. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-10-20sh: Move SH-4 CPU headers down one more level.Paul Mundt2-0/+0
These accidentally got placed in to cpu-sh4 instead of cpu-sh4/cpu, push them down one more level. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-10-20sh: Move the CPU definition headers from asm/ to cpu/.Paul Mundt2-0/+464
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-07-29sh: migrate to arch/sh/include/Paul Mundt14-0/+584
This follows the sparc changes a439fe51a1f8eb087c22dd24d69cebae4a3addac. Most of the moving about was done with Sam's directions at: http://marc.info/?l=linux-sh&m=121724823706062&w=2 with subsequent hacking and fixups entirely my fault. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.