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2017-08-09sparc64: Add a new hypercall CPU_POKEVijay Kumar1-0/+11
This adds a new hypercall CPU_POKE for quickly waking up an idle CPU. CPU_POKE should only be sent to valid non-local CPUs. Signed-off-by: Rob Gardner <rob.gardner@oracle.com> Signed-off-by: Vijay Kumar <vijay.ac.kumar@oracle.com> Reviewed-by: Anthony Yznaga <anthony.yznaga@oracle.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-07sparc: move exports to definitionsAl Viro1-0/+5
Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2016-01-31Add sun4v_wdt watchdog driverwim.coekaerts@oracle.com1-1/+2
This driver adds sparc hypervisor watchdog support. The default timeout is 60 seconds and the range is between 1 and 31536000 seconds. Both watchdog-resolution and watchdog-max-timeout MD properties settings are supported. Signed-off-by: Wim Coekaerts <wim.coekaerts@oracle.com> Reviewed-by: Julian Calaby <julian.calaby@gmail.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: David S. Miller <davem@davemloft.net>
2015-03-19sparc: perf: Add support M7 processorDavid Ahern1-0/+16
The M7 processor has a different hypervisor group id and different PCR fast trap values. PIC read/write functions and PCR bit fields are the same as the T4 so those are reused. Signed-off-by: David Ahern <david.ahern@oracle.com> Acked-by: Bob Picco <bob.picco@oracle.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2014-09-16sparc64: T5 PMUbob picco1-0/+16
The T5 (niagara5) has different PCR related HV fast trap values and a new HV API Group. This patch utilizes these and shares when possible with niagara4. We use the same sparc_pmu niagara4_pmu. Should there be new effort to obtain the MCU perf statistics then this would have to be changed. Cc: sparclinux@vger.kernel.org Signed-off-by: Bob Picco <bob.picco@oracle.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-08-18sparc64: Add hypervisor interfaces for SPARC-T4 perf counter access.David S. Miller1-0/+16
Unlike for previous chips, access to the perf-counter control registers are all hyper-privileged. Therefore, access to them must go through a hypervisor interface. Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-02sparc: Set reboot-cmd using reboot data hypervisor call if available.David S. Miller1-0/+7
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-12-04sparc,sparc64: unify kernel/Sam Ravnborg1-0/+800
o Move all files from sparc64/kernel/ to sparc/kernel - rename as appropriate o Update sparc/Makefile to the changes o Update sparc/kernel/Makefile to include the sparc64 files NOTE: This commit changes link order on sparc64! Link order had to change for either of sparc32 and sparc64. And assuming sparc64 see more testing than sparc32 change link order on sparc64 where issues will be caught faster. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: David S. Miller <davem@davemloft.net>
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