| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2012-01-11 | Merge branch 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci |   Linus Torvalds | 1 | -0/+31 |
| 2012-01-06 | x86/PCI: amd: factor out MMCONFIG discovery |   Bjorn Helgaas | 1 | -0/+31 |
| 2011-12-21 | x86: Simplify code by removing a !SMP #ifdefs from 'struct cpuinfo_x86' |   Kevin Winchester | 1 | -6/+2 |
| 2011-03-31 | x86, amd-nb: Rename CPU PCI id define for F4 |   Borislav Petkov | 1 | -1/+1 |
| 2011-03-17 | Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp | Linus Torvalds | 1 | -1/+1 |
| 2011-03-17 | PCI: Rename CPU PCI id define |   Borislav Petkov | 1 | -1/+1 |
| 2011-03-03 | x86, amd-nb: Misc cleanliness fixes | Borislav Petkov | 1 | -8/+10 |
| 2011-02-10 | x86: Adjust section placement in AMD northbridge related code |   Jan Beulich | 1 | -3/+4 |
| 2011-02-07 | x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs |   Hans Rosenfeld | 1 | -0/+63 |
| 2011-01-26 | x86, amd: Extend AMD northbridge caching code to support "Link Control" devices | Hans Rosenfeld | 1 | -2/+9 |
| 2011-01-26 | x86, amd: Enable L3 cache index disable on family 0x15 | Hans Rosenfeld | 1 | -0/+3 |
| 2011-01-11 | x86: Use PCI method for enabling AMD extended config space before MSR method | Jan Beulich | 1 | -0/+7 |
| 2010-11-18 | x86, cacheinfo: Cleanup L3 cache index disable support | Hans Rosenfeld | 1 | -0/+10 |
| 2010-11-18 | x86, amd-nb: Cleanup AMD northbridge caching code | Hans Rosenfeld | 1 | -47/+62 |
| 2010-11-18 | x86, amd-nb: Complete the rename of AMD NB and related code | Hans Rosenfeld | 1 | -36/+36 |
| 2010-10-01 | x86, amd_nb: Enable GART support for AMD family 0x15 CPUs |   Andreas Herrmann | 1 | -1/+3 |
| 2010-09-20 | x86, k8: Rename k8.[ch] to amd_nb.[ch] and CONFIG_K8_NB to CONFIG_AMD_NB | Andreas Herrmann | 1 | -0/+145 |
