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2017-06-20dccp: call inet_add_protocol after register_pernet_subsys in dccp_v6_initXin Long1-10/+10
Patch "call inet_add_protocol after register_pernet_subsys in dccp_v4_init" fixed a null pointer dereference issue for dccp_ipv4 module. The same fix is needed for dccp_ipv6 module. Signed-off-by: Xin Long <lucien.xin@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20dccp: call inet_add_protocol after register_pernet_subsys in dccp_v4_initXin Long1-8/+9
Now dccp_ipv4 works as a kernel module. During loading this module, if one dccp packet is being recieved after inet_add_protocol but before register_pernet_subsys in which v4_ctl_sk is initialized, a null pointer dereference may be triggered because of init_net.dccp.v4_ctl_sk is 0x0. Jianlin found this issue when the following call trace occurred: [ 171.950177] BUG: unable to handle kernel NULL pointer dereference at 0000000000000110 [ 171.951007] IP: [<ffffffffc0558364>] dccp_v4_ctl_send_reset+0xc4/0x220 [dccp_ipv4] [...] [ 171.984629] Call Trace: [ 171.984859] <IRQ> [ 171.985061] [ 171.985213] [<ffffffffc0559a53>] dccp_v4_rcv+0x383/0x3f9 [dccp_ipv4] [ 171.985711] [<ffffffff815ca054>] ip_local_deliver_finish+0xb4/0x1f0 [ 171.986309] [<ffffffff815ca339>] ip_local_deliver+0x59/0xd0 [ 171.986852] [<ffffffff810cd7a4>] ? update_curr+0x104/0x190 [ 171.986956] [<ffffffff815c9cda>] ip_rcv_finish+0x8a/0x350 [ 171.986956] [<ffffffff815ca666>] ip_rcv+0x2b6/0x410 [ 171.986956] [<ffffffff810c83b4>] ? task_cputime+0x44/0x80 [ 171.986956] [<ffffffff81586f22>] __netif_receive_skb_core+0x572/0x7c0 [ 171.986956] [<ffffffff810d2c51>] ? trigger_load_balance+0x61/0x1e0 [ 171.986956] [<ffffffff81587188>] __netif_receive_skb+0x18/0x60 [ 171.986956] [<ffffffff8158841e>] process_backlog+0xae/0x180 [ 171.986956] [<ffffffff8158799d>] net_rx_action+0x16d/0x380 [ 171.986956] [<ffffffff81090b7f>] __do_softirq+0xef/0x280 [ 171.986956] [<ffffffff816b6a1c>] call_softirq+0x1c/0x30 This patch is to move inet_add_protocol after register_pernet_subsys in dccp_v4_init, so that v4_ctl_sk is initialized before any incoming dccp packets are processed. Reported-by: Jianlin Shi <jishi@redhat.com> Signed-off-by: Xin Long <lucien.xin@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20enic: Fix format truncation warningGovindarajulu Varadarajan2-6/+6
With -Wformat-truncation, gcc throws the following warning. Fix this by increasing the size of devname to accommodate 15 character netdev interface name and description. Remove length format precision for %s. We can fit entire name. Also increment the version. drivers/net/ethernet/cisco/enic/enic_main.c: In function ‘enic_open’: drivers/net/ethernet/cisco/enic/enic_main.c:1740:15: warning: ‘%u’ directive output may be truncated writing between 1 and 2 bytes into a region of size between 1 and 12 [-Wformat-truncation=] "%.11s-rx-%u", netdev->name, i); ^~ drivers/net/ethernet/cisco/enic/enic_main.c:1740:5: note: directive argument in the range [0, 16] "%.11s-rx-%u", netdev->name, i); ^~~~~~~~~~~~~ drivers/net/ethernet/cisco/enic/enic_main.c:1738:4: note: ‘snprintf’ output between 6 and 18 bytes into a destination of size 16 snprintf(enic->msix[intr].devname, ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ sizeof(enic->msix[intr].devname), ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ "%.11s-rx-%u", netdev->name, i); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Govindarajulu Varadarajan <gvaradar@cisco.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net: stmmac: enable TSO for IPv6Niklas Cassel1-2/+2
There is nothing in the IP that prevents us from enabling TSO for IPv6. Before patch: ftp fe80::2aa:bbff:fecc:1336%eth0 ftp> get /dev/zero 882512708 bytes received in 00:14 (56.11 MiB/s) After patch: ftp fe80::2aa:bbff:fecc:1336%eth0 ftp> get /dev/zero 1203326784 bytes received in 00:12 (94.52 MiB/s) Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20ibmvnic: Return from ibmvnic_resume if not in VNIC_OPEN stateJohn Allen1-0/+3
If the ibmvnic driver is not in the VNIC_OPEN state, return from ibmvnic_resume callback. If we are not in the VNIC_OPEN state, interrupts may not be initialized and directly calling the interrupt handler will cause a crash. Signed-off-by: John Allen <jallen@linux.vnet.ibm.com> Reviewed-by: Nathan Fontenot <nfont@linux.vnet.ibm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net: phy: lxt: Export link partner advertisingThomas Bogendoerfer1-7/+4
Provide link partner advertising information. Removed testing for gigabit modes, which is useless for a fast ethernet phy. Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@suse.de> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net-next: mediatek: set the rx_queue to 0John Crispin1-0/+1
The get_rps_cpu() function will not do any RPS on the data flow when no queue is setup and always use the current cpu where the IRQ was handled to also handle the backlog. As we only have one physical queue we always set this to 0 unconditionally. Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net-next: mediatek: split IRQ register locking into TX and RXJohn Crispin2-30/+54
Originally the driver only utilised the new QDMA engine. The current code still assumes this is the case when locking the IRQ mask register. Since RX now runs on the old style PDMA engine we can add a second lock. This patch reduces the IRQ latency as the TX and RX path no longer need to wait on each other under heavy load. Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net-next: mediatek: add RX IRQ delay supportJohn Crispin2-4/+13
The PDMA engine used for RX allows IRQ aggregation. The patch sets up the corresponding registers to aggregate 4 IRQs into one. Using aggregation reduces the load on the core handling to a quarter thus reducing IRQ latency and increasing RX performance by around 10%. Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net-next: mediatek: print phy status changes for non DSA GMACsJohn Crispin1-0/+3
Currently PHY status changes are only printed for DSA ports. This patch adds code to also print status changes for non-fixed links. Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20vxlan: allow multiple VXLANs with same VNI for IPv6 link-local addressesMatthias Schiffer1-23/+45
As link-local addresses are only valid for a single interface, we can allow to use the same VNI for multiple independent VXLANs, as long as the used interfaces are distinct. This way, VXLANs can always be used as a drop-in replacement for VLANs with greater ID space. This also extends VNI lookup to respect the ifindex when link-local IPv6 addresses are used, so using the same VNI on multiple interfaces can actually work. Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20vxlan: fix snooping for link-local IPv6 addressesMatthias Schiffer1-5/+15
If VXLAN is run over link-local IPv6 addresses, it is necessary to store the ifindex in the FDB entries. Otherwise, the used interface is undefined and unicast communication will most likely fail. Support for link-local IPv4 addresses should be possible as well, but as the semantics aren't as well defined as for IPv6, and there doesn't seem to be much interest in having the support, it's not implemented for now. Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20vxlan: check valid combinations of address scopesMatthias Schiffer2-0/+31
* Multicast addresses are never valid as local address * Link-local IPv6 unicast addresses may only be used as remote when the local address is link-local as well * Don't allow link-local IPv6 local/remote addresses without interface We also store in the flags field if link-local addresses are used for the follow-up patches that actually make VXLAN over link-local IPv6 work. Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20vxlan: improve validation of address family configurationMatthias Schiffer1-11/+28
Address families of source and destination addresses must match, and changelink operations can't change the address family. In addition, always use the VXLAN_F_IPV6 to check if a VXLAN device uses IPv4 or IPv6. Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20vxlan: get rid of redundant vxlan_dev.flagsMatthias Schiffer3-42/+39
There is no good reason to keep the flags twice in vxlan_dev and vxlan_config. Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20vxlan: refactor verification and application of configurationMatthias Schiffer1-97/+111
The vxlan_dev_configure function was mixing validation and application of the vxlan configuration; this could easily lead to bugs with the changelink operation, as it was hard to see if the function wcould return an error after parts of the configuration had already been applied. This commit splits validation and application out of vxlan_dev_configure as separate functions to make it clearer where error returns are allowed and where the vxlan_dev or net_device may be configured. Log messages in these functions are removed, as it is generally unexpected to find error output for netlink requests in the kernel log. Userspace should be able to handle errors based on the error codes returned via netlink just fine. In addition, some validation and initialization is moved to vxlan_validate and vxlan_setup respectively to improve grouping of similar settings. Finally, this also fixes two actual bugs: * if set, conf->mtu would overwrite dev->mtu in each changelink operation, reverting other changes of dev->mtu * the "if (!conf->dst_port)" branch would never be run, as conf->dst_port was set in vxlan_setup before. This caused VXLAN-GPE to use the same default port as other VXLAN sockets instead of the intended IANA-assigned 4790. Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net: manual clean code which call skb_put_[data:zero]yuan linyu39-135/+93
Signed-off-by: yuan linyu <Linyu.Yuan@alcatel-sbell.com.cn> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net: replace more place to skb_put_[data:zero]yuan linyu7-16/+9
spatch file, @@ expression skb, len, data; type t; @@ -memcpy((t *)skb_put(skb, len), data, len); +skb_put_data(skb, data, len); @@ identifier p; expression skb, len, data; type t; @@ -p = (t *)memset(skb_put(skb, len), data, len); +p = skb_put_zero(skb, len); @@ expression skb, len, data; type t; @@ -memcpy((t *)__skb_put(skb, len), data, len); +__skb_put_data(skb, data, len); @@ identifier p; expression skb, len, data; type t; @@ -p = (t *)memset(__skb_put(skb, len), data, len); +p = __skb_put_zero(skb, len); Signed-off-by: yuan linyu <Linyu.Yuan@alcatel-sbell.com.cn> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net: introduce __skb_put_[zero, data, u8]yuan linyu19-67/+64
follow Johannes Berg, semantic patch file as below, @@ identifier p, p2; expression len; expression skb; type t, t2; @@ ( -p = __skb_put(skb, len); +p = __skb_put_zero(skb, len); | -p = (t)__skb_put(skb, len); +p = __skb_put_zero(skb, len); ) ... when != p ( p2 = (t2)p; -memset(p2, 0, len); | -memset(p, 0, len); ) @@ identifier p; expression len; expression skb; type t; @@ ( -t p = __skb_put(skb, len); +t p = __skb_put_zero(skb, len); ) ... when != p ( -memset(p, 0, len); ) @@ type t, t2; identifier p, p2; expression skb; @@ t *p; ... ( -p = __skb_put(skb, sizeof(t)); +p = __skb_put_zero(skb, sizeof(t)); | -p = (t *)__skb_put(skb, sizeof(t)); +p = __skb_put_zero(skb, sizeof(t)); ) ... when != p ( p2 = (t2)p; -memset(p2, 0, sizeof(*p)); | -memset(p, 0, sizeof(*p)); ) @@ expression skb, len; @@ -memset(__skb_put(skb, len), 0, len); +__skb_put_zero(skb, len); @@ expression skb, len, data; @@ -memcpy(__skb_put(skb, len), data, len); +__skb_put_data(skb, data, len); @@ expression SKB, C, S; typedef u8; identifier fn = {__skb_put}; fresh identifier fn2 = fn ## "_u8"; @@ - *(u8 *)fn(SKB, S) = C; + fn2(SKB, C); Signed-off-by: yuan linyu <Linyu.Yuan@alcatel-sbell.com.cn> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net: dsa: mv88e6xxx: better IEEE Prio Mapping Table descriptionVivien Didelot2-7/+8
Kill the remaining shift macro in favor of calculating at compile time its value from the more descriptive mask, which gives us a better representation of the register layout. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net: dsa: mv88e6xxx: prefix Global 2 remaining macrosVivien Didelot2-35/+57
Prefix and document the remaining Global 2 registers macros. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net: dsa: mv88e6xxx: prefix Global 2 Watchdog macrosVivien Didelot2-43/+52
The Marvell 88E6352 family has a Global 2 register dedicated to the watchdog setup. But the 88E6390 turned it into an indirect table. Prefix and document that. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net: dsa: mv88e6xxx: prefix Global 2 Switch MAC macrosVivien Didelot2-2/+7
Prefix and document the Global 2 Switch MAC registers macros. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net: dsa: mv88e6xxx: prefix Global 2 EEPROM macrosVivien Didelot2-25/+38
Prefix and document the Global 2 EEPROM registers macros. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net: dsa: mv88e6xxx: prefix Global 2 PVT macrosVivien Didelot2-12/+21
Prefix and document the Global 2 Cross-chip Port VLAN registers macros. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net: dsa: mv88e6xxx: prefix Global 2 MGMT macrosVivien Didelot2-13/+21
Prefix and document the Global 2 MGMT registers macros. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net: dsa: mv88e6xxx: prefix Global 2 Device Mapping macrosVivien Didelot2-5/+7
Prefix and document the Global 2 Device Mapping macros. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net: dsa: mv88e6xxx: prefix Global 2 Trunk macrosVivien Didelot2-14/+17
Prefix and document the Global 2 Trunk registers macros. At the same time, fix the hask -> hash typo and use the mv88e6xxx_port_mask helper. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net: dsa: mv88e6xxx: clarify SMI PHY functionsVivien Didelot2-100/+143
Marvell chips with an SMI PHY access in Global 2 registers handle both Clause 22 and Clause 45 of IEEE 802.3. The 88E6390 family has addition bits to target the internal or external PHYs connected to the device, and a Setup function in addition to the default (register) Access function. Prefix the SMI PHY Command and Data registers macros, implement clear helpers for Clause 22 and 44 Access functions, rename variable to match the SMI and switch vocabulary (device and register addresses for Clause 22 and port and device class for Clause 45.) Finally do not use complex macros but simple 16-bit mask to document the registers organization. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net: dsa: mv88e6xxx: add irl_init_all opVivien Didelot4-50/+116
Some Marvell chips have an Ingress Rate Limit unit. But the command values slightly differs between models: 88E6352 use 3-bit for operations while 88E6390 use different 2-bit operations. This commit kills the IRL flags in favor of a new operation implementing the "Init all resources to the initial state" operation. This fixes the operation of 88E6390 family where 0x1000 means Read the selected resource 0, register 0 on port 16, instead of init all. A mv88e6xxx_irl_setup helper is added to wrap the operation call. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net-next: stmmac: dwmac-sun8i: add support for V3s EMACIcenowy Zheng2-0/+9
Allwinner V3s SoC has an Ethernet MAC and an internal PHY like the ones in H3 SoC, however the MAC has no external *MII interfaces available at GPIOs, thus only MII connection to internal PHY is supported. Add this variant of EMAC to dwmac-sun8i driver. The default value of the syscon EMAC-related register seems to have changed from H3, but it seems to be a harmless change. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net-next: stmmac: dwmac-sun8i: force EPHY clock freq to 24MHzIcenowy Zheng1-0/+4
The EPHY control part of the EMAC syscon register has a bit called CLK_SEL. On the datasheet it says that if it's 0 the EPHY clock is 25MHz and if it's 1 the clock is 24MHz. However, according to the datasheets, no Allwinner SoC with EPHY has any extra xtal input pins for the EPHY, and the system xtal is 24MHz. That means the EPHY is not possible to get a 25MHz xtal input, and thus the frequency can only be 24MHz. It doesn't matter on H3 as the default value of H3 is 24MHz, however on V3s the default value is wrongly set to 25MHz, which prevented the EPHY from working properly. Force the EPHY clock frequency to 24MHz. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20dt-bindings: syscon: Add DT bindings documentation for Allwinner V3s sysconIcenowy Zheng1-0/+1
Allwinner V3s SoC has a syscon like the one in H3. Add its compatible string. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20dt-bindings: net-next: Add DT bindings documentation for Allwinner V3s EMACIcenowy Zheng1-2/+8
Allwinner V3s SoC has a Ethernet MAC like the one in Allwinner H3, but have no external MII capability. That means that it can only use the EPHY and cannot do Gbps transmission. Add binding for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20selftests: Introduce tc testsuiteLucas Bates10-0/+1863
Add the beginnings of a testsuite for tc functionality in the kernel. These are a series of unit tests that use the tc executable and verify the success of those commands by checking both the exit codes and the output from tc's 'show' operation. To run the tests: # cd tools/testing/selftests/tc-testing # sudo ./tdc.py You can specify the tc executable to use with the -p argument on the command line or editing the 'TC' variable in tdc_config.py. Refer to the README for full details on how to run. The initial complement of test cases are limited mostly to tc actions. Test cases are most welcome; see the creating-testcases subdirectory for help in creating them. Signed-off-by: Lucas Bates <lucasb@mojatatu.com> Signed-off-by: Jamal Hadi Salim <jhs@mojatatu.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20qed: SPQ async callback registrationMichal Kalderon7-55/+96
Whenever firmware indicates that there's an async indication it needs to handle, there's a switch-case where the right functionality is called based on function's personality and information. Before iWARP is added [as yet another client], switch over the SPQ into a callback-registered mechanism, allowing registration of the relevant event-processing logic based on the function's personality. This allows us to tidy the code by removing protocol-specifics from a common file. Signed-off-by: Michal Kalderon <Michal.Kalderon@cavium.com> Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20qed: Wait for resources before FUNC_CLOSEMichal Kalderon1-15/+20
Driver needs to wait for all resources to return from FW before it can send the FUNC_CLOSE ramrod. Signed-off-by: Michal Kalderon <Michal.Kalderon@cavium.com> Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20qed*: Set rdma generic functions prefixMichal Kalderon5-100/+101
Rename the functions common to both iWARP and RoCE to have a prefix of _rdma_ instead of _roce_. Signed-off-by: Michal Kalderon <Michal.Kalderon@cavium.com> Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20qed*: qede_roce.[ch] -> qede_rdma.[ch]Michal Kalderon7-5/+10
Once we have iWARP support, the qede portion of the qedr<->qede would serve all the RDMA protocols - so rename the file to be appropriate to its function. While we're at it, we're also moving a couple of inclusions to it into .h files and adding includes to make sure it contains all type definitions it requires. Signed-off-by: Michal Kalderon <Michal.Kalderon@cavium.com> Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20qed: Disable RoCE dpm when DCBx change occursMintz, Yuval3-0/+49
If DCBx update occurs while QPs are open, stop sending edpms until all QPs are closed. Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20qed: RoCE EDPM to honor PFCMintz, Yuval2-0/+22
Configure device according to DCBx results so that EDPMs made by RoCE would honor flow-control. Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20qed: Chain support for external PBLMintz, Yuval10-28/+56
iWARP would require the chains to allocate/free their PBL memory independently, so add the infrastructure to provide it externally. Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-19tcp: md5: add TCP_MD5SIG_EXT socket option to set a key address prefixIvan Delalande5-15/+41
Replace first padding in the tcp_md5sig structure with a new flag field and address prefix length so it can be specified when configuring a new key for TCP MD5 signature. The tcpm_flags field will only be used if the socket option is TCP_MD5SIG_EXT to avoid breaking existing programs, and tcpm_prefixlen only when the TCP_MD5SIG_FLAG_PREFIX flag is set. Signed-off-by: Bob Gilligan <gilligan@arista.com> Signed-off-by: Eric Mowat <mowat@arista.com> Signed-off-by: Ivan Delalande <colona@arista.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-19tcp: md5: add an address prefix for key lookupIvan Delalande3-16/+70
This allows the keys used for TCP MD5 signature to be used for whole range of addresses, specified with a prefix length, instead of only one address as it currently is. Signed-off-by: Bob Gilligan <gilligan@arista.com> Signed-off-by: Eric Mowat <mowat@arista.com> Signed-off-by: Ivan Delalande <colona@arista.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-19cxgb4: notify uP to route ctrlq compl to rdma rspqRaju Rangoju1-4/+6
During the module initialisation there is a possible race (basically race between uld and lld) where neither the uld nor lld notifies the uP about where to route the ctrl queue completions. LLD skips notifying uP as the rdma queues were not created by then (will leave it to ULD to notify the uP). As the ULD comes up, it also skips notifying the uP as the flag FULL_INIT_DONE is not set yet (ULD assumes that the interface is not up yet). Consequently, this race between uld and lld leaves uP unnotified about where to send the ctrl queue completions to, leading to iwarp RI_RES WR failure. Here is the race: CPU 0 CPU1 - allocates nic rx queus - t4_sge_alloc_ctrl_txq() (if rdma rsp queues exists, tell uP to route ctrl queue compl to rdma rspq) - acquires the mutex_lock - allocates rdma response queues - if FULL_INIT_DONE set, tell uP to route ctrl queue compl to rdma rspq - relinquishes mutex_lock - acquires the mutex_lock - enable_rx() - set FULL_INIT_DONE - relinquishes mutex_lock This patch fixes the above issue. Fixes: e7519f9926f1('cxgb4: avoid enabling napi twice to the same queue') Signed-off-by: Raju Rangoju <rajur@chelsio.com> Acked-by: Steve Wise <swise@opengridcomputing.com> CC: Stable <stable@vger.kernel.org> # 4.9+ Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-19cxgb4: add new T6 pci device id'sGanesh Goudar1-0/+3
Add 0x6082, 0x6083 and 0x6084 T6 device id's Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-19nfp: add VLAN filtering supportPablo Cascón2-1/+100
Add general use per-vNIC mailbox area and use it for VLAN filtering support. Initially proto is hardcoded to 802.1q. Signed-off-by: Pablo Cascón <pablo.cascon@netronome.com> Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-19cxgb4: fix a NULL dereferenceGanesh Goudar1-1/+4
Avoid NULL dereference in setup_sge_queues() when the adapter is in non offload mode. Fixes: 0fbc81b3ad51 ('chcr/cxgb4i/cxgbit/RDMA/cxgb4: Allocate resources dynamically for all cxgb4 ULD's') Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-18liquidio: replace info-pointer mode with buffer-pointer-only modePrasad Kanneganti11-109/+37
Each Octeon output ring can DMA packets to host memory in two modes: info- pointer mode and buffer-pointer-only mode. In info-pointer mode, Octeon takes two buffer pointers for each packet and places the length of the packet along with specified number of bytes from the beginning of the packet into one buffer and the rest of the packet in a separate buffer. In buffer-pointer-only mode, Octeon takes single buffer pointer and places the length of the packet at the beginning of the buffer followed by the packet data. This patch switches all Octeon output rings from info-pointer mode to buffer-pointer-only mode. This results in fewer DMA setups and cache line snoops. Signed-off-by: Prasad Kanneganti <pkanneganti@cavium.com> Signed-off-by: Derek Chickles <derek.chickles@cavium.com> Signed-off-by: Satanand Burla <satananda.burla@cavium.com> Signed-off-by: Felix Manlunas <felix.manlunas@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-18pptp: Remove unused variable in pptp_release()Christos Gkekas1-2/+0
Variable opt in pptp_release() is set but never used, thus needs to be removed. Signed-off-by: Christos Gkekas <chris.gekas@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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