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2011-01-14agp/intel: Fix device names of i845 and 845GOswald Buddenhagen2-3/+3
They got mixed up when the switch was converted to a table in 2007. Signed-off-by: Oswald Buddenhagen <ossi@kde.org> [ickle: minor changes for 2.6.37+] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-12i915/gtt: fix ordering causing DMAR errors on object teardown.Dave Airlie1-2/+2
Previous to the last GTT rework we always rewrote the GTT then unmapped the object, somehow this got reversed in the rework in 2.6.37-rc5 timeframe. This fix needs to go to stable in an alternate form since the code changed. This fixes DMAR reports on my Ironlake HP2540p. Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-01-12i915/gtt: fix ordering issues with status setup and DMARDave Airlie1-2/+2
This code was setting up the status page before setting the DMAR-is-on-bit, so we were getting DMAR errors on the status page. Reverse the two bits of init code to the correct result. Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-01-11agp/intel: Flush the chipset write buffers when changing GTT baseChris Wilson2-0/+11
Flush the chipset write buffers before and after adjusting the GTT base register, just in case. We only modify this value upon initialisation (boot and resume) so there should be no outstanding writes, however there are always those persistent PGTBL_ER that keep getting reported upon resume. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-10Merge branch 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6Linus Torvalds8-472/+363
* 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (390 commits) drm/radeon/kms: disable underscan by default drm/radeon/kms: only enable hdmi features if the monitor supports audio drm: Restore the old_fb upon modeset failure drm/nouveau: fix hwmon device binding radeon: consolidate asic-specific function decls for pre-r600 vga_switcheroo: comparing too few characters in strncmp() drm/radeon/kms: add NI pci ids drm/radeon/kms: don't enable pcie gen2 on NI yet drm/radeon/kms: add radeon_asic struct for NI asics drm/radeon/kms/ni: load default sclk/mclk/vddc at pm init drm/radeon/kms: add ucode loader for NI drm/radeon/kms: add support for DCE5 display LUTs drm/radeon/kms: add ni_reg.h drm/radeon/kms: add bo blit support for NI drm/radeon/kms: always use writeback/events for fences on NI drm/radeon/kms: adjust default clock/vddc tracking for pm on DCE5 drm/radeon/kms: add backend map workaround for barts drm/radeon/kms: fill gpu init for NI asics drm/radeon/kms: add disabled vbios accessor for NI asics drm/radeon/kms: handle NI thermal controller ...
2011-01-06Merge branch 'x86-amd-nb-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tipLinus Torvalds1-17/+16
* 'x86-amd-nb-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, cacheinfo: Cleanup L3 cache index disable support x86, amd-nb: Cleanup AMD northbridge caching code x86, amd-nb: Complete the rename of AMD NB and related code
2010-12-14Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson1-2/+9
2010-12-14agp/intel: Fix missed cached memory flags setting in i965_write_entry()Chris Wilson1-2/+9
This fixes regression from a6963596a13e62f8e65b1cf3403a330ff2db407c, that missed to set cached memory type in GTT entry. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson1-2/+4
Immediate merge for the conflicting introduction of HAS_COHERENT_RINGS. Conflicts: drivers/gpu/drm/i915/i915_dma.c include/drm/i915_drm.h
2010-12-05agp/intel: Fix wrong kunmap in i830_cleanup()Takashi Iwai1-2/+4
Add a missing NULL check and fix the wrong address passed to kunmap() in i830_cleanup(). Cc: stable@kernel.org Signed-off-by: Takashi Iwai <tiwai@suse.de> [danvet: added cc stable] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23agp/intel: Remove duplicate constChris Wilson1-1/+1
drivers/char/agp/intel-gtt.c:340:48: warning: duplicate const Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23intel-gtt: export api for drm/i915Daniel Vetter1-52/+68
Just some minor shuffling to get rid of any agp traces in the exported functions. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23agp: kill agp_rebind_memoryDaniel Vetter1-20/+0
Its only user, intel-gtt.c is now gone. Cc: Dave Airlie <airlied@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23drm/i915: restore gtt on resume in the drm instead of in intel-gtt.koDaniel Vetter1-5/+0
This still uses the agp functions to actually reinstate the mappings (with a gross hack to make agp cooperate), but it wires everything up correctly for the switchover. The call to agp_rebind_memory can be dropped because all non-kms drivers do all their rebinding on EnterVT. v2: Be more paranoid and flush the chipset cache after restoring gtt mappings. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23agp: kill agp_flush_chipset and corresponding ioctlDaniel Vetter6-24/+0
The intel drm calls the chipset functions now directly. Userspace never called the corresponding ioctl, hence it can be killed, too. Cc: Dave Airlie <airlied@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23drm/i915/gtt: call chipset flush directlyDaniel Vetter1-0/+7
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23drm/i915|intel-gtt: consolidate intel-gtt.h headersDaniel Vetter1-5/+0
... and a few other defines. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23intel-gtt: fold i81x-only dcache support into the generic driverDaniel Vetter1-89/+61
Now the intel-gtt.c rewrite is complete! Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23intel-gtt: switch i81x to the common initialization helpersDaniel Vetter1-127/+71
Still a separate agp_bridge_driver because of the i81x-only dedicated vram support. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23intel-gtt: switch i81x to the write_entry helpersDaniel Vetter1-92/+60
Initialization is still done with the old code with a few added things sprinkled in to make the intel_fake_agp helper functions work. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23intel-gtt: kill unneeded sandybridge memory typesDaniel Vetter1-6/+0
Used for the now dead agp type_to_mask stuff. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23intel-gtt: drop dcache support for i830 and laterDaniel Vetter1-7/+1
i830_check_flags already disallows it, so no need to implement it in the write_entry function. Seems to be a remnant from i810 support. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23agp/intel: Remove confusion of stolen entries not stolen memoryChris Wilson1-33/+7
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23agp/intel: Remove the artificial cap on stolen sizeChris Wilson1-13/+3
Now that the stolen memory does not also steal entries from the GTT, we can use all the memory the BIOS set aside for the GPU. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-22Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson1-1/+0
Conflicts: drivers/gpu/drm/i915/i915_gem.c
2010-11-18x86, amd-nb: Cleanup AMD northbridge caching codeHans Rosenfeld1-15/+14
Support more than just the "Misc Control" part of the northbridges. Support more flags by turning "gart_supported" into a single bit flag that is stored in a flags member. Clean up related code by using a set of functions (amd_nb_num(), amd_nb_has_feature() and node_to_amd_nb()) instead of accessing the NB data structures directly. Reorder the initialization code and put the GART flush words caching in a separate function. Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
2010-11-18x86, amd-nb: Complete the rename of AMD NB and related codeHans Rosenfeld1-16/+16
Not only the naming of the files was confusing, it was even more so for the function and variable names. Renamed the K8 NB and NUMA stuff that is also used on other AMD platforms. This also renames the CONFIG_K8_NUMA option to CONFIG_AMD_NUMA and the related file k8topology_64.c to amdtopology_64.c. No functional changes intended. Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
2010-11-17BKL: remove extraneous #include <smp_lock.h>Arnd Bergmann1-1/+0
The big kernel lock has been removed from all these files at some point, leaving only the #include. Remove this too as a cleanup. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-11-15Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson1-0/+5
Conflicts: drivers/gpu/drm/i915/i915_gem.c drivers/gpu/drm/i915/intel_ringbuffer.c
2010-11-09Merge branch 'drm-intel-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/ickle/drm-intelDave Airlie1-3/+3
* 'drm-intel-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/ickle/drm-intel: drm/i915: Fix LVDS fixed-mode regression from 219adae1 drm/i915/ringbuffer: Use the HEAD auto-reporting mechanism drm/i915: Avoid might_fault during pwrite whilst holding our mutex agp/intel: fix cache control for sandybridge agp/intel: restore cache behavior on sandybridge drm/i915; Don't apply Ironlake FDI clock workaround to Sandybridge drm/i915: Fix KMS regression on Sandybridge/CPT i915: reprogram power monitoring registers on resume drm/i915: SNB BLT workaround drm/i915: Fix the graphics frequency clamping at init and when IPS is active. drm/i915: Allow powersave modparam to be adjusted at runtime. drm/i915: Apply big hammer to serialise buffer access between rings drm/i915: opregion_setup: iounmap correct address drm/i915: Flush read-only buffers from the active list upon idle as well i915: signedness bug in check_overlay_src() drm/i915: Fix typo from "Enable DisplayPort Audio"
2010-11-04agp/intel: fix cache control for sandybridgeZhenyu Wang1-2/+2
This is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3. Let's set the correct bit for LLC+MLC and LLC only. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-04agp/intel: restore cache behavior on sandybridgeZhenyu Wang1-1/+1
This restores cache behavior for default AGP_USER_MEMORY as uncached, and leave default AGP_USER_CACHED_MEMORY as LLC only. I've seen different cache behavior on one sandybridge desktop CPU vs. another mobile CPU. Until we figure out how to detect the real cache config, restore back to the original behavior now. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-02agp/intel: restore cache behavior on sandybridgeZhenyu Wang1-1/+1
This restores cache behavior for default AGP_USER_MEMORY as uncached, and leave default AGP_USER_CACHED_MEMORY as LLC only. I've seen different cache behavior on one sandybridge desktop CPU vs. another mobile CPU. Until we figure out how to detect the real cache config, restore back to the original behavior now. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-02agp/intel: fix cache control for sandybridgeZhenyu Wang1-2/+2
This is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3. Let's set the correct bit for LLC+MLC and LLC only. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-31agp/intel: the GMCH is always enabled for integrated processor graphicsChris Wilson1-16/+27
... and trying to set the bit is ineffectual. Fixes the regression from e380f60 which detected that we were trying to do undefined operations on the I830_GMCH_CTRL. Reported-by: Alexey Fisher <bug-track@fisher-privat.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-29agp/intel: Sandybridge doesn't require GMCH enablingChris Wilson1-7/+30
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-29parisc-agp: fix missing slab.h includeKyle McMartin1-0/+1
Commit 338e4fab added a missing kfree if the alloc_pci_dev failed but forgot to include <linux/slab.h> for the definition of kfree. Signed-off-by: Kyle McMartin <kyle@redhat.com>
2010-10-28Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/kyle/parisc-2.6Linus Torvalds1-0/+4
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/kyle/parisc-2.6: parisc: add tty driver to PDC console drivers/parisc/iosapic.c: Remove unnecessary kzalloc cast parisc: remove homegrown L1_CACHE_ALIGN macro arch/parisc: Removing undead ifdef CONFIG_PA20 parisc: unwind - optimise linked-list searches for modules parisc: change to new flag variable drivers/char/agp/parisc-agp.c: eliminate memory leak parisc: kill __do_IRQ parisc: convert eisa interrupts to flow handlers parisc: convert gsc and dino pci interrupts to flow handlers parisc: convert suckyio interrupts to flow handlers parisc: convert iosapic interrupts to proper flow handlers parisc: convert cpu interrupts to proper flow handlers parisc: lay groundwork for killing __do_IRQ parisc: add prlimit64 syscall parisc: squelch warning when using dev_get_stats
2010-10-27intel-gtt: maximize ggtt size on platforms that support thisDaniel Vetter2-29/+81
On VT-d supporting platforms the GGTT is allocated in a stolen mem section separate from graphcis stolen mem. The GMCH register contains a bitfield specifying the size of that region. Docs suggest that this region can only be used for GGTT and PPGTT. Hence ensure that the PPGTT is disabled and use the complete area for the GGTT. Unfortunately the graphics core on G33/Pineview can't cope with really large GTTs and the BIOS usually enables the maximum of 512MB. So don't bother with maximizing the GTT on these platforms. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-27intel-gtt: save PGETBL_CTL later in the setup processDaniel Vetter1-7/+7
... and switch to a more classical store-reg-on-suspend, restore-on-resume way of doing things. Obviously this is just preparation for the future, the code is not there at all, yet. This is needed because the next patch adjusts this register and everything in it (not just the pagetable address) needs to be restored on resume. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-26Merge branch 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6Linus Torvalds8-1094/+804
* 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (476 commits) vmwgfx: Implement a proper GMR eviction mechanism drm/radeon/kms: fix r6xx/7xx 1D tiling CS checker v2 drm/radeon/kms: properly compute group_size on 6xx/7xx drm/radeon/kms: fix 2D tile height alignment in the r600 CS checker drm/radeon/kms/evergreen: set the clear state to the blit state drm/radeon/kms: don't poll dac load detect. gpu: Add Intel GMA500(Poulsbo) Stub Driver drm/radeon/kms: MC vram map needs to be >= pci aperture size drm/radeon/kms: implement display watermark support for evergreen drm/radeon/kms/evergreen: add some additional safe regs v2 drm/radeon/r600: fix tiling issues in CS checker. drm/i915: Move gpu_write_list to per-ring drm/i915: Invalidate the to-ring, flush the old-ring when updating domains drm/i915/ringbuffer: Write the value passed in to the tail register agp/intel: Restore valid PTE bit for Sandybridge after bdd3072 drm/i915: Fix flushing regression from 9af90d19f drm/i915/sdvo: Remove unused encoding member i915: enable AVI infoframe for intel_hdmi.c [v4] drm/i915: Fix current fb blocking for page flip drm/i915: IS_IRONLAKE is synonymous with gen == 5 ... Fix up conflicts in - drivers/gpu/drm/i915/{i915_gem.c, i915/intel_overlay.c}: due to the new simplified stack-based kmap_atomic() interface - drivers/gpu/drm/vmwgfx/vmwgfx_drv.c: added .llseek entry due to BKL removal cleanups.
2010-10-24Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivialLinus Torvalds2-2/+2
* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (39 commits) Update broken web addresses in arch directory. Update broken web addresses in the kernel. Revert "drivers/usb: Remove unnecessary return's from void functions" for musb gadget Revert "Fix typo: configuation => configuration" partially ida: document IDA_BITMAP_LONGS calculation ext2: fix a typo on comment in ext2/inode.c drivers/scsi: Remove unnecessary casts of private_data drivers/s390: Remove unnecessary casts of private_data net/sunrpc/rpc_pipe.c: Remove unnecessary casts of private_data drivers/infiniband: Remove unnecessary casts of private_data drivers/gpu/drm: Remove unnecessary casts of private_data kernel/pm_qos_params.c: Remove unnecessary casts of private_data fs/ecryptfs: Remove unnecessary casts of private_data fs/seq_file.c: Remove unnecessary casts of private_data arm: uengine.c: remove C99 comments arm: scoop.c: remove C99 comments Fix typo configue => configure in comments Fix typo: configuation => configuration Fix typo interrest[ing|ed] => interest[ing|ed] Fix various typos of valid in comments ... Fix up trivial conflicts in: drivers/char/ipmi/ipmi_si_intf.c drivers/usb/gadget/rndis.c net/irda/irnet/irnet_ppp.c
2010-10-22agp/intel: Restore valid PTE bit for Sandybridge after bdd3072Chris Wilson1-3/+3
In cleaning up the mask functions in bdd3072, the setting of the PTE valid bit was dropped for Sandybridge. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-21drivers/char/agp/parisc-agp.c: eliminate memory leakJulia Lawall1-0/+4
alloc_pci_dev allocates some memory, so that memory should be freed before leaving the function in an error case. A simplified version of the semantic match that finds this problem is: (http://coccinelle.lip6.fr/) // <smpl> @r exists@ local idexpression x; expression E; identifier f1; iterator I; @@ x = alloc_pci_dev(...); <... when != x when != true (x == NULL || ...) when != if (...) { <+...x...+> } when != I (...) { <+...x...+> } ( x == NULL | x == E | x->f1 ) ...> * return ...; // </smpl> Signed-off-by: Julia Lawall <julia@diku.dk> Dan Carpenter <error27@gmail.com> Dave Airlie <airlied@linux.ie> Cc: Helge Deller <deller@gmx.de> Cc: "James E.J. Bottomley" <jejb@parisc-linux.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Kyle McMartin <kyle@redhat.com>
2010-10-21Merge branch 'x86-amd-nb-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tipLinus Torvalds2-12/+25
* 'x86-amd-nb-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, amd_nb: Enable GART support for AMD family 0x15 CPUs x86, amd: Use compute unit information to determine thread siblings x86, amd: Extract compute unit information for AMD CPUs x86, amd: Add support for CPUID topology extension of AMD CPUs x86, nmi: Support NMI watchdog on newer AMD CPU families x86, mtrr: Assume SYS_CFG[Tom2ForceMemTypeWB] exists on all future AMD CPUs x86, k8: Rename k8.[ch] to amd_nb.[ch] and CONFIG_K8_NB to CONFIG_AMD_NB x86, k8-gart: Decouple handling of garts and northbridges x86, cacheinfo: Fix dependency of AMD L3 CID x86, kvm: add new AMD SVM feature bits x86, cpu: Fix allowed CPUID bits for KVM guests x86, cpu: Update AMD CPUID feature bits x86, cpu: Fix renamed, not-yet-shipping AMD CPUID feature bit x86, AMD: Remove needless CPU family check (for L3 cache info) x86, tsc: Remove CPU frequency calibration on AMD
2010-10-19agp/intel: Also add B43.1 to list of supported devicesChris Wilson1-0/+1
This was a missing piece from 41a5142 that dropped recognition of the AGP module for the second B43 variant. Reported-by: Stefan Bader <stefan.bader@canonical.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
2010-10-19agp/amd-k7: Allow binding user memory to the AGP GART.Francisco Jerez1-2/+4
TTM-based DRM drivers need to be able to bind user memory to the AGP aperture. This patch fixes the "[TTM] AGP Bind memory failed." errors and the subsequent fallout seen with the nouveau driver. Signed-off-by: Francisco Jerez <currojerez@riseup.net> Tested-by: Grzesiek Sójka <pld@pfu.pl> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-10-18Update broken web addresses in the kernel.Justin P. Mattock2-2/+2
The patch below updates broken web addresses in the kernel Signed-off-by: Justin P. Mattock <justinmattock@gmail.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Finn Thain <fthain@telegraphics.com.au> Cc: Randy Dunlap <rdunlap@xenotime.net> Cc: Matt Turner <mattst88@gmail.com> Cc: Dimitry Torokhov <dmitry.torokhov@gmail.com> Cc: Mike Frysinger <vapier.adi@gmail.com> Acked-by: Ben Pfaff <blp@cs.stanford.edu> Acked-by: Hans J. Koch <hjk@linutronix.de> Reviewed-by: Finn Thain <fthain@telegraphics.com.au> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2010-10-13Merge branch 'amd-iommu/2.6.37' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/linux-2.6-iommu into core/iommuIngo Molnar3-27/+81
2010-09-24some clean up to intel-gtt.cJan Beulich1-2/+1
In commit e517a5e97080bbe52857bd0d7df9b66602d53c4d the call to map_page_into_agp() got removed from intel_i830_setup_flush(), but the counterpart call from intel_i830_fini_flush() to unmap_page_from_agp() was left in place. Additionally, the page allocated here never gets its physical address used for sending to hardware, so there's no need to allocate it with GFP_DMA32. Nor is __GFP_ZERO really necessary, as the page is used only to store data to force flushing of some internal processor state. Signed-off-by: Jan Beulich <jbeulich@novell.com> Cc: Eric Anholt <eric@anholt.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>