aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/clk/berlin (follow)
AgeCommit message (Collapse)AuthorFilesLines
2015-01-13clk: berlin: bg2q: remove non-exist "smemc" gate clockJisheng Zhang1-1/+0
The "smemc" clock is removed on BG2Q SoCs. In fact, bit19 of clkenable register is for nfc. Current code use bit19 for non-exist "smemc" incorrectly, this prevents eMMC from working due to the sdhci's "core" clk is still gated. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Cc: stable@vger.kernel.org # 3.16+ Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-05-29clk: berlin: add core clock driver for BG2QAlexandre Belloni2-0/+390
This driver deals with the core clocks found on Marvell Berlin BG2Q. For the shared register dividers, make use of the corresponding driver and add some single clock muxes and gates for the rest. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-05-29clk: berlin: add core clock driver for BG2/BG2CDSebastian Hesselbarth3-0/+722
This driver deals with the core clocks found on Marvell Berlin BG2 and BG2CD. For the shared register dividers, make use of the corresponding driver and add some single clock muxes and gates for the rest. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-05-29clk: berlin: add driver for BG2x complex divider cellsAlexandre Belloni3-1/+355
This is a driver for the complex divider cells found on Marvell Berlin2 SoCs. The cells come in two flavors: single register cells and shared register cells. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-05-29clk: berlin: add driver for BG2x simple PLLsAlexandre Belloni3-1/+155
This is a clock driver for the simple PLLs found on Berlin SoCs. With repect to PLL registers and features, BG2/BG2CD and BG2Q are slightly different, e.g. different allowed VCO dividers and bit shifts. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-05-29clk: berlin: add driver for BG2x audio/video PLLSebastian Hesselbarth3-0/+430
This is a driver for the AVPLLs built upon a VCO with 8 channels each found on Marvell Berlin2 SoCs. While both VCOs found on BG2/BG2CD share the same register set, sometimes registers shifts for one of the VCOs are a bit off. Nothing serious that should require a separate driver, so deal with both VCOs in a single driver instead. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>