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2015-02-02clk: Add rate constraints to clocksTomeu Vizoso1-0/+2
Adds a way for clock consumers to set maximum and minimum rates. This can be used for thermal drivers to set minimum rates, or by misc. drivers to set maximum rates to assure a minimum performance level. Changes the signature of the determine_rate callback by adding the parameters min_rate and max_rate. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [sboyd@codeaurora.org: set req_rate in __clk_init] Signed-off-by: Michael Turquette <mturquette@linaro.org> [mturquette@linaro.org: min/max rate for sun6i_ahb1_clk_determine_rate migrated clk-private.h changes to clk.c]
2014-12-03clk: Change clk_ops->determine_rate to return a clk_hw as the best parentTomeu Vizoso1-1/+1
This is in preparation for clock providers to not have to deal with struct clk. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-19clk: hi3620: Move const initdata into correct code sectionBintian Wang1-35/+35
Use __initconst instead of __initdata for constant init data. Signed-off-by: Bintian Wang <bintian.wang@huawei.com> Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-09-28clk: hix5hd2: add I2C clocksWei Yan1-0/+25
hix5hd2 add I2C clocks (I2C0~i2C5) Signed-off-by: Wei Yan <sledge.yanwei@huawei.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2014-09-28clk: hix5hd2: add watchdog0 clocksGuoxiong Yan1-0/+5
hix5hd2 add watchdog0 clocks Signed-off-by: Guoxiong Yan <yanguoxiong@huawei.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2014-09-28clk: hix5hd2: add sd clkJiancheng Xue1-6/+15
Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2014-09-28clk: hix5hd2: add complex clkZhangfei Gao1-0/+181
Support clk of sata, usb and ethernet Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2014-05-12clk: hisi: add clk-hix5hd2.cZhangfei Gao2-0/+102
Signed-off-by: Haifeng Yan <haifeng.yan@linaro.org> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2014-05-12clk: hisi: add hisi_clk_register_gateZhangfei Gao2-0/+30
Add hisi_clk_register_gate register clk gate table Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2014-05-12clk: hisi: use clk_register_mux_table in hisi_clk_register_muxZhangfei Gao2-5/+9
Platform hix5hd2 use mux table, so use clk_register_mux_table instead Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2014-03-20clk: hisilicon: fix warning from smatchZhangfei Gao1-8/+7
drivers/clk/hisilicon/clk-hi3620.c:338 mmc_clk_delay() warn: always true condition '(para >= 0) => (0-u32max >= 0)' Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-19Merge tag 'clk-hisi' of https://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1/linux into clk-next-hisilconMike Turquette5-39/+128
updating clock drivers for Hisilicon
2014-03-19clk: hisi: remove static variableHaojian Zhuang4-42/+72
Remove the static variable. So these common clock register helper could be used in more SoCs. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2014-03-19clk: hip04: add clock driverHaojian Zhuang2-1/+58
Now only fixed rate clocks are appended into the clock driver. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2014-03-19clk: hisi: assign missing clk to tableHaojian Zhuang1-0/+2
The fixed rate and fixed factor clock isn't registered to clk table. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2014-02-26clk: hisilicon: add hi3620_mmc_clksZhangfei Gao1-0/+274
Suggest by Arnd: abstract mmc tuning as clock behavior, also because different soc have different tuning method and registers. hi3620_mmc_clks is added to handle mmc clock specifically on hi3620. Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-12-11clk: hi3620: add gate clock flagHaojian Zhuang1-59/+59
Add missing CLK_SET_RATE_PARENT flag for gate clock. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
2013-12-11clk: hi3620: fix wrong flags on dividerHaojian Zhuang1-11/+11
The flags on dividers should be CLK_DIVIDER_HIWORD_MASK, not CLK_MUX_HIWORD_MASK. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
2013-12-04clk: hisilicon: add common clock supportHaojian Zhuang5-0/+651
Enable common clock driver of Hi3620 SoC. clkgate-seperated driver is used to support the clock gate that enable/disable/status registers are seperated. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
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