linux-dev - Linux kernel development work

Age	Commit message (Collapse)	Author	Files	Lines
2018-10-17	clk: imx6sl: add mmdc ipg clocks	Anson Huang	1	-0/+2
	i.MX6SL has MMDC0 and MMDC1 ipg clock in CCM CCGR, add them into clock tree for clock management. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-29	clk: imx6sl: remove clks_init_on array	Anson Huang	1	-12/+0
	Clock framework will enable those clocks registered with CLK_IS_CRITICAL flag, so no need to have clks_init_on array during clock initialization now. ARM clock is busy divider type which has the CLK_IS_CRITICAL flag set by default when registered. IPG clock has no clock gate and its parent AHB clock is busy divider type, so no need to add CLK_IS_CRITICAL flag for IPG clock. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-01	clk: imx6sl: correct ocram_podf clock type	Anson Huang	1	-1/+1
	IMX6SL_CLK_OCRAM_PODF is a busy divider, its name in CCM_CDHIPR register of Reference Manual CCM chapter is axi_podf_busy, correct its clock type. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2017-08-30	clk: imx: constify clk_div_table	Arvind Yadav	1	-3/+3
	clk_div_table are not supposed to change at runtime. All functions working with clk_div_table provided by <linux/clk-provider.h> work with const clk_div_table. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-12	clk: imx: fix pll clock parents	Dong Aisheng	1	-7/+7
	pllx_bypass_src mux shouldn't be the parent of pllx clock since it's only valid when when pllx BYPASS bit is set. Thus it is actually one parent of pllx_bypass only. Instead, pllx parent should be fixed to osc according to reference manual. Other plls have the same issue. e.g. before fix, the pll tree is: osc 6 6 24000000 0 0 pll1_bypass_src 0 0 24000000 0 0 pll1 0 0 792000000 0 0 pll1_bypass 0 0 792000000 0 0 pll1_sys 0 0 792000000 0 0 After the fix, it's: osc 6 6 24000000 0 0 pll1 0 0 792000000 0 0 pll1_bypass 0 0 792000000 0 0 pll1_sys 0 0 792000000 0 0 Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-10-12	clk: imx6: Add SPDIF_GCLK clock in clock tree	Shengjiu Wang	1	-1/+3
	Correct SPDIF clock setting issue in clock tree, the SPDIF_GCLK is also one clock of SPDIF, which is missed before. We found an issue that imx can't enter low power mode with spdif if IMX6x_CLK_SPDIF is used as the core clock of spdif. Because spdif driver will register IMX6x_CLK_SPDIF clock to regmap, regmap will do clk_prepare in init function, then IMX6x_CLK_SPDIF clock is prepared in probe, so its parent clock (PLL clock) is prepared, the prepare operation of PLL clock is to enable the clock. But I.MX needs all PLL clock is disabled, then it can enter low power mode. So we can't use IMX6x_CLK_SPDIF as the core clock of spdif, the correct spdif core clock is SPDIF_GCLK, which share same gate bit with IMX6x_CLK_SPDIF clock. SPDIF_GCLK's parent clock is ipg clock. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-09-25	clk: imx6: retain early UART clocks during kernel init	Lucas Stach	1	-0/+8
	Make sure to keep UART clocks enabled during kernel init if earlyprintk or earlycon are active. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-06-03	ARM: imx: move clock drivers into drivers/clk	Shawn Guo	1	-0/+443
	After the cleanup on clock drivers, they are now ready to be moved into drivers/clk. Let's move them into drivers/clk/imx folder. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org>