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path: root/drivers/clk/imx/clk-imx8mq.c (follow)
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2019-06-24clk: imx8mq: Keep uart clocks on during system bootAnson Huang1-0/+10
Call imx_register_uart_clocks() API to keep uart clocks enabled when earlyprintk or earlycon is active. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18clk: imx8mq: Use devm_platform_ioremap_resource() instead of of_iomap()Anson Huang1-3/+3
i.MX8MQ clock driver uses platform driver model, better to use devm_platform_ioremap_resource() instead of of_iomap() to get IO base. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18clk: imx8mq: Use imx_check_clocks() API directlyAnson Huang1-5/+1
Use imx_check_clocks() API to check clocks directly. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-05-23clk: imx8m: Add GIC clockLeonard Crestez1-0/+4
This is documented in the reference manuals as GIC_CLK_ROOT. In some out-of-tree DVFS scenarios the gic clock can end up as the only user of sys_pll2 so if we don't define the gic clk explicitly it might be turned off. This applies to both 8mq and 8mm: same clk register but diffferent parents. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-05-22clk: imx8mq: add SNVS clock to clock treeAnson Huang1-0/+1
i.MX8MQ has clock gate for SNVS module, add it into clock tree for SNVS RTC driver to manage. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-05-02clk: imx8mq: Add dsi_ipg_divGuido Günther1-0/+1
It's defined in imx8mq-clock.h but wasn't assigned yet. It's used as clk_tx_esc in the nwl dsi host controller (i.MX8MQ RM, Rev. 0, 01/2018 Sect. 13.5.3.7.4). Signed-off-by: Guido Günther <agx@sigxcpu.org> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-28clk: imx8mq: add GPIO clocks to clock treeAnson Huang1-0/+5
i.MX8MQ has clock gate for each GPIO bank, add them into clock tree for GPIO driver to manage. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-26clk: imx: Refactor entire sccg pll clkAbel Vesa1-45/+8
Make the entire combination of plls to be one single clock. The parents used for bypasses are specified each as an index in the parents list. The determine_rate does a lookup throughout all the possible combinations for all the divs and returns the best possible 'setup' which in turn is used by set_rate later to set up all the divs and bypasses. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Tested-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21clk: imx8mq: Add the missing ARM clockAbel Vesa1-0/+6
Add the ARM clock as imx_clk_cpu type. Will be used by cpufreq. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21clk: imx: imx8mq: Fix the rate propagation for arm pllAbel Vesa1-1/+1
The arm pll bypass needs to propagate the rate upwards in order for the cpufreq to work. Fixes: b80522040cd3f ("clk: imx: Add clock driver for i.MX8MQ CCM") Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21clk: imx8mq: Add support for the CLKO1 clockFabio Estevam1-0/+3
Add the entry for the CLKO1 clock. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21clk: imx8mq: Fix the CLKO2 source select listFabio Estevam1-2/+2
The CLKO2 clock source select list is the following as per the i.MX8M Reference Manual: 000 - 25M_REF_CLK 001 - SYSTEM_PLL2_DIV5 010 - SYSTEM_PLL1_DIV2 011 - SYSTEM_PLL2_DIV6 100 - SYSTEM_PLL3_CLK 101 - AUDIO_PLL1_CLK 110 - VIDEO_PLL1_CLK 111 - 32K_REF_CLK However, in imx8mq_clko2_sels[] only the first four entries are correct. Fix it by adding the missing "sys3_pll2_out" entry in order to match the description from the manual. Fixes: b80522040cd3f ("clk: imx: Add clock driver for i.MX8MQ CCM") Reported-by: Rogerio Pimentel <rogerio.silva@nxp.com> Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21clk: imx8mq: Add missing M4 clocksCarlo Caione1-0/+7
The clocks list is missing the clocks for the M4 core. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21clk: imx8mq: Make parent names arrays const pointersAbel Vesa1-97/+97
The arrays containing the mux selectors need to be of const pointer to const char. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03clk: imx: Add clock driver for i.MX8MQ CCMAbel Vesa1-0/+589
Add driver for the Clock Control Module found on i.MX8MQ. Signed-off-by: Anson Huang <anson.huang@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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