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2017-07-21clk: Convert to using %pOF instead of full_nameRob Herring3-3/+3
Now that we have a custom printf format specifier, convert users of full_name to use %pOF instead. This is preparation to remove storing of the full path string for each node. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Tero Kristo <t-kristo@ti.com> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mediatek@lists.infradead.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-tegra@vger.kernel.org Cc: linux-omap@vger.kernel.org Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: James Liao <jamesjj.liao@mediatek.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: mediatek: fixed static checker warning in clk_cpumux_get_parent callSean Wang1-4/+0
Fixed the signedness bug returning '(-22)' on the return type as u8 with removing the sanity checker in clk_cpumux_get_parent() since clk_cpumux_set_parent() always ensures validity in clk_cpumux_get_parent() got called. Fixes: 1e17de9049da ("clk: mediatek: add missing cpu mux causing Mediatek cpufreq can't work") Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: mediatek: export cpu multiplexer clock for MT8173 SoCsSean Wang1-0/+23
The patch enables CPU multiplexer clock on MT8173 SoC which fixes up cpufreq driver fails at acquiring intermediate clock source when driver probe is called. Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: mediatek: export cpu multiplexer clock for MT2701/MT7623 SoCsSean Wang1-0/+8
The patch enables CPU multiplexer clock on MT2701/MT7623 SoC which fixes up cpufreq driver fails at acquiring intermediate clock source when driver probe is called. Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: mediatek: add missing cpu mux causing Mediatek cpufreq can't workSean Wang3-1/+151
This patch adds CPU multiplexer clocks which are essential for Mediatek cpufreq driver. It would use the CPU clock multiplexer to switch to the intermediate clock source temporarily and then wait for the primary clock changing getting stable. Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-21clk: mediatek: add mt2701 ethernet resetJohn Crispin1-0/+2
The ethernet clock core has a reset register that is currently not exposed to the user. Fix this by adding the missing registration code. Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19clk: mediatek: add clk support for MT6797Kevin-CW Chen7-0/+1134
Add MT6797 clock support, include topckgen, apmixedsys, infracfg and subsystem clocks Signed-off-by: Kevin-CW Chen <kevin-cw.chen@mediatek.com> Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-26clk: mediatek: Fix MT8135 dependenciesJean Delvare1-2/+2
The MT8135 is a 32-bit SoC, so only propose it on ARM architecture, not ARM64. Signed-off-by: Jean Delvare <jdelvare@suse.de> Fixes: 234d511d8c15 ("clk: mediatek: Add hardware dependency") Cc: Andreas Färber <afaerber@suse.de> Acked-by: James Liao <jamesjj.liao@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-26clk: mediatek: Fix MT2701 dependenciesJean Delvare1-7/+8
If I say "no" to "Clock driver for Mediatek MT2701", I don't want to be asked individually about each sub-driver. No means no. Additionally, this driver shouldn't be proposed at all on non-mediatek builds, unless build-testing. Signed-off-by: Jean Delvare <jdelvare@suse.de> Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support") Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: James Liao <jamesjj.liao@mediatek.com> Cc: Shunli Wang <shunli.wang@mediatek.com> Cc: Erin Lo <erin.lo@mediatek.com> Cc: Michael Turquette <mturquette@baylibre.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-08reset: mediatek: Add MT2701 reset driverShunli Wang2-4/+16
In infrasys and perifsys, there are many reset control bits for kinds of modules. These bits are used as actual reset controllers to be registered into kernel's generic reset controller framework. Signed-off-by: Shunli Wang <shunli.wang@mediatek.com> Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Erin Lo <erin.lo@mediatek.com> Tested-by: John Crispin <blogic@openwrt.org> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-08clk: mediatek: Add MT2701 clock supportShunli Wang14-5/+1797
Add MT2701 clock support, include topckgen, apmixedsys, infracfg, pericfg and subsystem clocks. Signed-off-by: Shunli Wang <shunli.wang@mediatek.com> Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Erin Lo <erin.lo@mediatek.com> Tested-by: John Crispin <blogic@openwrt.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-17clk: mediatek: Add hardware dependencyJean Delvare1-0/+2
Only propose the mediatek clock drivers on this platform, unless build-testing. Signed-off-by: Jean Delvare <jdelvare@suse.de> Cc: Shunli Wang <shunli.wang@mediatek.com> Cc: James Liao <jamesjj.liao@mediatek.com> Cc: Erin Lo <erin.lo@mediatek.com> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: Michael Turquette <mturquette@baylibre.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-21clk: mediatek: clk-mt8173: Unmap region obtained by of_iomapArvind Yadav1-1/+3
Free memory mapping if init is not successful. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Reviewed-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-19clk: mediatek: Refine the makefile to support multiple clock driversJames Liao2-3/+24
Add a Kconfig to define clock configuration for each SoC, and modify the Makefile to build drivers that only selected in config. Signed-off-by: Shunli Wang <shunli.wang@mediatek.com> Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Erin Lo <erin.lo@mediatek.com> Tested-by: John Crispin <blogic@openwrt.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-18clk: mediatek: remove __init from clk registration functionsJames Liao3-8/+8
Remove __init from functions that will be used by init functions that support probe deferral. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Erin Lo <erin.lo@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-05-06clk: mediatek: remove hdmitx_dig_cts from TOP clocksPhilipp Zabel1-1/+0
The hdmitx_dig_cts clock signal is not a child of tvdpll_445p5m, but is routed out of the HDMI PHY module. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2016-05-06clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock outputPhilipp Zabel1-0/+5
The configurable hdmi_ref output of the PLL block is derived from the tvdpll_594m clock signal via a configurable PLL post-divider. It is used as the PLL reference input to the HDMI PHY module. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: James Liao <jamesjj.liao@mediatek.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2016-05-06clk: mediatek: make dpi0_sel propagate rate changesPhilipp Zabel2-3/+18
This mux is supposed to select a fitting divider after the PLL is already set to the correct rate. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: James Liao <jamesjj.liao@mediatek.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-29clk: mediatek: Make reset_control_ops constPhilipp Zabel1-1/+1
The mtk_reset_ops structure is never modified. Make it const. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02clk: mediatek: Remove CLK_IS_ROOTStephen Boyd1-2/+2
This flag is a no-op now. Remove usage of the flag. Acked-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk: mediatek: Fix memory leak on clock init failJames Liao1-2/+4
mtk_clk_register_composite() may leak memory due to some error handling path don't free all allocated memory. This patch free all pointers that may allocate memory before error return. And it's safe because kfree() can handle NULL pointers. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk: move the common clock's to_clk_*(_hw) macros to clk-provider.hGeliang Tang2-5/+5
to_clk_*(_hw) macros have been repeatedly defined in many places. This patch moves all the to_clk_*(_hw) definitions in the common clock framework to public header clk-provider.h, and drop the local definitions. Signed-off-by: Geliang Tang <geliangtang@163.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-01clk: mediatek: Add USB clock support in MT8173 APMIXEDSYSJames Liao5-7/+159
Add REF2USB_TX clock support into MT8173 APMIXEDSYS. This clock is needed by USB 3.0. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
2015-10-01clk: mediatek: Add subsystem clocks of MT8173James Liao1-0/+267
Most multimedia subsystem clocks will be accessed by multiple drivers, so it's a better way to manage these clocks in CCF. This patch adds clock support for MM, IMG, VDEC, VENC and VENC_LT subsystems. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
2015-10-01clk: mediatek: Fix rate and dependency of MT8173 clocksJames Liao1-6/+13
Remove the dependency from clk_null, and give all root clocks a typical rate, include clkph_mck_o, usb_syspll_125m and hdmitx_dig_cts. dpi_ck was removed due to no clock reference to it. Replace parent clock of infra_cpum with cpum_ck, which is an external clock and can be defined in the device tree. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
2015-10-01clk: mediatek: Add fixed clocks support for Mediatek SoC.James Liao2-0/+40
This patch adds fixed clocks support by using CCF fixed-rate clock implementation. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
2015-10-01clk: mediatek: Add __initdata and __init for data and functionsJames Liao3-10/+11
Add __init for clock registration functions, and add __initdata for mtk_gate_regs initial structures. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
2015-10-01clk: mediatek: Remove unused code from MT8173.James Liao2-4/+2
Remove unused header files from MT8173, and remove unused keywords from function declaration. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
2015-10-01clk: mediatek: Removed unused dpi_ck clock from MT8173James Liao1-1/+0
The dpi_ck clock can be removed because it not actually used in topckgen and subsystems. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
2015-10-01clk: mediatek: add 13mhz clock for MT8173Joe.C1-0/+5
Add 13mhz clock used by GPT timer in infracfg. Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
2015-07-28Merge branch 'cleanup-clk-h-includes' into clk-nextStephen Boyd4-2/+6
* cleanup-clk-h-includes: (62 commits) clk: Remove clk.h from clk-provider.h clk: h8300: Remove clk.h and clkdev.h includes clk: at91: Include clk.h and slab.h clk: ti: Switch clk-provider.h include to clk.h clk: pistachio: Include clk.h clk: ingenic: Include clk.h clk: si570: Include clk.h clk: moxart: Include clk.h clk: cdce925: Include clk.h clk: Include clk.h in clk.c clk: zynq: Include clk.h clk: ti: Include clk.h clk: sunxi: Include clk.h and remove unused clkdev.h includes clk: st: Include clk.h clk: qcom: Include clk.h clk: highbank: Include clk.h clk: bcm: Include clk.h clk: versatile: Remove clk.h and clkdev.h includes clk: ux500: Remove clk.h and clkdev.h includes clk: tegra: Properly include clk.h ...
2015-07-28clk: mediatek: Add MT8173 MMPLL change rate supportJames Liao3-6/+42
MT8173 MMPLL frequency settings are different from common PLLs. It needs different post divider settings for some ranges of frequency. This patch add support for MT8173 MMPLL frequency setting by adding div-rate table to lookup suitable post divider setting under a specified frequency. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28clk: mediatek: Fix calculation of PLL rate settingsJames Liao1-2/+2
Avoid u32 overflow when calculate post divider setting, and increase the max post divider setting from 3 (/8) to 4 (/16). Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28clk: mediatek: Fix PLL registers setting flowJames Liao1-9/+12
Write postdiv and pcw settings at the same time for PLLs if postdiv and pcw settings are on the same register. This is need by PLLs such as MT8173 MMPLL and ARM*PLL. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-20clk: mediatek: Properly include clk.hStephen Boyd4-2/+6
We don't need to include clk.h in header files, just forward declare struct clk here. This leads us to a few places where the include of clk.h was missing in C files. Add them. Cc: James Liao <jamesjj.liao@mediatek.com> Cc: Henry Chen <henryc.chen@mediatek.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06clk: mediatek: mt8173: Fix enabling of critical clocksSascha Hauer1-5/+21
On the MT8173 the clocks are provided by different units. To enable the critical clocks we must be sure that all parent clocks are already registered, otherwise the parents of the critical clocks end up being unused and get disabled later. To find a place where all parents are registered we try each time after we've registered some clocks if all known providers are present now and only then we enable the critical clocks Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: James Liao <jamesjj.liao@mediatek.com> [sboyd@codeaurora.org: Marked function and data __init] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-04clk: mediatek: Fix apmixedsys clock registrationJames Liao2-2/+2
The size of clk_data should be the same as CLK_APMIXED_NR_CLK instead of ARRAY_SIZE(plls). CLK_APMIXED_* is numbered from 1, so CLK_APMIXED_NR_CLK will be greater than ARRAY_SIZE(plls). Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-19clk: mediatek: Initialize clk_init_dataRicky Liang2-2/+2
The variable init (struct clk_init_data) is allocated on the stack. We weren't initializing the .flags field, so it contains random junk, which can cause all kinds of interesting issues when the flags are parsed by clk_register. Signed-off-by: Ricky Liang <jcliang@chromium.org> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-05clk: mediatek: Add basic clocks for Mediatek MT8173.James Liao2-0/+831
This patch adds basic clocks for MT8173, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-05clk: mediatek: Add basic clocks for Mediatek MT8135.James Liao2-0/+645
This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-05clk: mediatek: Add reset controller supportSascha Hauer3-0/+108
The pericfg and infracfg units also provide reset lines to several other SoC internal units. This adds a function which can be called from the pericfg and infracfg initialization functions which will register the reset controller using reset_controller_register. The reset controller will provide support for resetting the units connected to the pericfg and infracfg controller. The units resetted by this controller can use the standard reset device tree binding to gain access to the reset lines. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-05clk: mediatek: Add initial common clock support for Mediatek SoCs.James Liao6-0/+898
This patch adds common clock support for Mediatek SoCs, including plls, muxes and clock gates. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> [sboyd@codeaurora.org: Squelch checkpatch warning in clk-mtk.h] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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