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2019-04-11clk: qcom: Add QCS404 TuringCCBjorn Andersson1-0/+1
The Turing Clock Controller provides resources related to running the Turing subsystem. PM runtime is used to ensure that the associated AHB clock is ticking while the clock framework is accessing the registers in the Turing clock controller. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-14Merge branch 'clk-qcom-sdm845-lpass' into clk-nextStephen Boyd1-0/+1
- Qualcomm SDM845 audio subsystem clks * clk-qcom-sdm845-lpass: clk: qcom: Add lpass clock controller driver for SDM845 dt-bindings: clock: Introduce QCOM LPASS clock bindings dt-bindings: clock: Update GCC bindings for protected-clocks
2018-12-03clk: qcom: Add lpass clock controller driver for SDM845Taniya Das1-0/+1
Add support for the lpass clock controller found on SDM845 based devices. This would allow lpass peripheral loader drivers to control the clocks to bring the subsystem out of reset. LPASS clocks present on the global clock controller would be registered with the clock framework based on the protected-clock flag. Also do not gate these clocks if they are left unused, as the lpass clocks require the global clock controller lpass clocks to be enabled before they are accessed. Mark the GCC lpass clocks as CRITICAL, for the LPASS clock access. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-11-27clk: qcom: Add graphics clock controller driver for SDM845Amit Nischal1-0/+1
Add support for the graphics clock controller found on SDM845 based devices. This would allow graphics drivers to probe and control their clocks. Signed-off-by: Amit Nischal <anischal@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> [sboyd@kernel.org: Collapse return in probe into less lines] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-18Merge branches 'clk-imx6-mmdc', 'clk-qcom-krait', 'clk-rockchip' and 'clk-smp2s11-match' into clk-nextStephen Boyd1-0/+5
- iMX6 MMDC clks - Qualcomm Krait CPU clk support * clk-imx6-mmdc: clk: imx6q: add mmdc0 ipg clock clk: imx6sl: add mmdc ipg clocks clk: imx6sll: add mmdc1 ipg clock clk: imx6sx: add mmdc1 ipg clock clk: imx6ul: add mmdc1 ipg clock * clk-qcom-krait: clk: qcom: Add safe switch hook for krait mux clocks dt-bindings: clock: Document qcom,krait-cc clk: qcom: Add Krait clock controller driver dt-bindings: arm: Document qcom,kpss-gcc clk: qcom: Add KPSS ACC/GCC driver clk: qcom: Add support for Krait clocks clk: qcom: Add IPQ806X's HFPLLs clk: qcom: Add MSM8960/APQ8064's HFPLLs dt-bindings: clock: Document qcom,hfpll clk: qcom: Add HFPLL driver clk: qcom: Add support for High-Frequency PLLs (HFPLLs) ARM: Add Krait L2 register accessor functions * clk-rockchip: clk: rockchip: Fix static checker warning in rockchip_ddrclk_get_parent call clk: rockchip: use the newly added clock-id for hdmi on RK3066 clk: rockchip: add clock-id for HCLK_HDMI on rk3066 clk: rockchip: fix wrong mmc sample phase shift for rk3328 clk: rockchip: improve rk3288 pll rates for better hdmi output * clk-smp2s11-match: clk: s2mps11: Add used attribute to s2mps11_dt_match clk: s2mps11: Fix matching when built as module and DT node contains compatible
2018-10-18Merge branch 'clk-qcom-qcs404' into clk-nextStephen Boyd1-0/+1
- Qualcomm QCS404 GCC support * clk-qcom-qcs404: clk: qcom: gcc: Add global clock controller driver for QCS404 clk: qcom: Export clk_alpha_pll_configure()
2018-10-18Merge branch 'clk-qcom-sdm660' into clk-nextStephen Boyd1-0/+1
- Qualcomm SDM660 GCC support * clk-qcom-sdm660: clk: qcom: gcc-sdm660: Add MODULE_LICENSE clk: qcom: Add Global Clock controller (GCC) driver for SDM660
2018-10-17clk: qcom: Add Krait clock controller driverStephen Boyd1-0/+1
The Krait CPU clocks are made up of a primary mux and secondary mux for each CPU and the L2, controlled via cp15 accessors. For Kraits within KPSSv1 each secondary mux accepts a different aux source, but on KPSSv2 each secondary mux accepts the same aux source. Cc: <devicetree@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Tested-by: Craig Tatlor <ctatlor97@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17clk: qcom: Add KPSS ACC/GCC driverStephen Boyd1-0/+1
The ACC and GCC regions present in KPSSv1 contain registers to control clocks and power to each Krait CPU and L2. For CPUfreq purposes probe these devices and expose a mux clock that chooses between PXO and PLL8. Cc: <devicetree@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Tested-by: Craig Tatlor <ctatlor97@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17clk: qcom: Add support for Krait clocksStephen Boyd1-0/+1
The Krait clocks are made up of a series of muxes and a divider that choose between a fixed rate clock and dedicated HFPLLs for each CPU. Instead of using mmio accesses to remux parents, the Krait implementation exposes the remux control via cp15 registers. Support these clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Tested-by: Craig Tatlor <ctatlor97@gmail.com> [sboyd@kernel.org: Move hidden config to top outside of the visible qcom config zone so that menuconfig looks nice] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17clk: qcom: Add HFPLL driverStephen Boyd1-0/+1
On some devices (MSM8974 for example), the HFPLLs are instantiated within the Krait processor subsystem as separate register regions. Add a driver for these PLLs so that we can provide HFPLL clocks for use by the system. Cc: <devicetree@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Tested-by: Craig Tatlor <ctatlor97@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-17clk: qcom: Add support for High-Frequency PLLs (HFPLLs)Stephen Boyd1-0/+1
HFPLLs are the main frequency source for Krait CPU clocks. Add support for changing the rate of these PLLs. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Tested-by: Craig Tatlor <ctatlor97@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-16clk: qcom: gcc: Add global clock controller driver for QCS404Shefali Jain1-0/+1
Add the clocks supported in global clock controller which clock the peripherals like BLSPs, SDCC, USB, MDSS etc. Register all the clocks to the clock framework for the clients to be able to request for them. Signed-off-by: Shefali Jain <shefjain@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Co-developed-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Anu Ramanathan <anur@codeaurora.org> [bamse, vkoul: rebase and tidyup for upstream] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Acked-by: Rob Herring <robh@kernel.org> [sboyd@kernel.org: Lowercase hex] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-16clk: qcom: Add Global Clock controller (GCC) driver for SDM660Taniya Das1-0/+1
Add support for the global clock controller found on SDM660 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Based on CAF implementation. Signed-off-by: Taniya Das <tdas@codeaurora.org> [craig: rename parents to fit upstream, and other cleanups] Signed-off-by: Craig Tatlor <ctatlor97@gmail.com> Acked-by: Rob Herring <robh@kernel.org> [sboyd@kernel.org: Rename gcc_660 to gcc_sdm660 and fix numbering of defines to avoid duplicates] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-08-30clk: qcom: Add camera clock controller driver for SDM845Amit Nischal1-0/+1
Add support for the camera clock controller found on SDM845 based devices. This would allow camera drivers to probe and control their clocks. Signed-off-by: Amit Nischal <anischal@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-08-14Merge branches 'clk-actions-s700', 'clk-exynos-unused', 'clk-qcom-dispcc-845', 'clk-scmi-round' and 'clk-cs2000-spdx' into clk-nextStephen Boyd1-0/+1
* clk-actions-s700: : - Actions Semi Owl series S700 SoC clk driver clk: actions: Add S700 SoC clock support dt-bindings: clock: Add S700 support for Actions Semi Soc's clk: actions: Add missing REGMAP_MMIO dependency * clk-exynos-unused: : - Remove an unused variable from Exynos4412 ISP driver clk: samsung: Remove unused mout_user_aclk400_mcuisp_p4x12 variable * clk-qcom-dispcc-845: : - Qualcomm SDM845 display clock controller clk: qcom: Add display clock controller driver for SDM845 dt-bindings: clock: Introduce QCOM Display clock bindings clk: qcom: Move frequency table macro to common file * clk-scmi-round: : - Fix a thinko bug in SCMI clk division logic clk: scmi: Fix the rounding of clock rate * clk-cs2000-spdx: clk: cs2000-cp: convert to SPDX identifiers
2018-08-01clk: qcom: Add display clock controller driver for SDM845Taniya Das1-0/+1
Add support for the display clock controller found on SDM845 based devices. This would allow display drivers to probe and control their clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> [sboyd@kernel.org: Remove CLK_GET_RATE_NOCACHE everywhere] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-16clk: qcom: clk-rpmh: Add QCOM RPMh clock driverTaniya Das1-0/+1
Add the RPMh clock driver to control the RPMh managed clock resources on some of the Qualcomm Technologies, Inc. SoCs. Signed-off-by: Taniya Das <tdas@codeaurora.org> [sboyd@kernel.org: Clean up whitespace, indentation, remove cmd_db_ready check] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-04Merge branch 'clk-qcom-sdm845' into clk-nextStephen Boyd1-0/+2
* clk-qcom-sdm845: clk: qcom: Export clk_fabia_pll_configure() clk: qcom: Add video clock controller driver for SDM845 dt-bindings: clock: Introduce QCOM Video clock bindings clk: qcom: Add Global Clock controller (GCC) driver for SDM845 clk: qcom: Add DT bindings for SDM845 gcc clock controller clk: qcom: Configure the RCGs to a safe source as needed clk: qcom: Add support for BRANCH_HALT_SKIP flag for branch clocks clk: qcom: Simplify gdsc status checking logic clk: qcom: gdsc: Add support to poll CFG register to check GDSC state clk: qcom: gdsc: Add support to poll for higher timeout value clk: qcom: gdsc: Add support to reset AON and block reset logic clk: qcom: Add support for controlling Fabia PLL clk: qcom: Clear hardware clock control bit of RCG Also fixup the Kconfig mess where SDM845 GCC has msm8998 in the description and also the video Kconfig says things slightly differently from the GCC one so just make it the same.
2018-06-01clk: qcom: Add video clock controller driver for SDM845Amit Nischal1-0/+1
Add support for the video clock controller found on SDM845 based devices. This would allow video drivers to probe and control their clocks. Signed-off-by: Amit Nischal <anischal@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-08clk: qcom: Add Global Clock controller (GCC) driver for SDM845Taniya Das1-0/+1
Add support for the global clock controller found on SDM845 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Amit Nischal <anischal@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-04-16clk: qcom: Add MSM8998 Global Clock Control (GCC) driverJoonwoo Park1-0/+1
Add support for the global clock controller found on MSM8998 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org> Signed-off-by: Imran Khan <kimran@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> [bjorn: Specify regs for alpha_plls, fix white spaces and add binding] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-01-26Merge branches 'clk-iproc', 'clk-mvebu' and 'clk-qcom-a53' into clk-nextStephen Boyd1-0/+3
* clk-iproc: clk: iproc: Minor tidy up of iproc pll data structures clk: iproc: Allow plls to do minor rate changes without reset clk: iproc: Fix error in the pll post divider rate calculation clk: iproc: Allow iproc pll to runtime calculate vco parameters * clk-mvebu: clk: mvebu: armada-37xx-periph: Use PTR_ERR_OR_ZERO() * clk-qcom-a53: clk: qcom: Add APCS clock controller support clk: qcom: Add regmap mux-div clocks support clk: qcom: Add A53 PLL support
2018-01-02clk: qcom: Add APCS clock controller supportGeorgi Djakov1-0/+1
Add a driver for the APCS clock controller. It is part of the APCS hardware block, which among other things implements also a combined mux and half integer divider functionality. It can choose between a fixed-rate clock or the dedicated APCS (A53) PLL. The source and the divider can be set both at the same time. This is required for enabling CPU frequency scaling on MSM8916-based platforms. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Amit Kucheria <amit.kucheria@linaro.org> [sboyd@codeaurora.org: Include rcg header for parent_map, drop multiple unneeded includes, add COMPILE_TEST to APCS depends, made tristate/modular] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2018-01-02clk: qcom: Add regmap mux-div clocks supportGeorgi Djakov1-0/+1
Add support for hardware that can switch both parent clock and divider at the same time. This avoids generating intermediate frequencies from either the old parent clock and new divider or new parent clock and old divider combinations. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Tested-by: Amit Kucheria <amit.kucheria@linaro.org> [sboyd@codeaurora.org: Change a comment style, drop parent_map in favor of a u32 array instead, export symbols for clk_ops and mux function] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2018-01-02clk: qcom: Add A53 PLL supportGeorgi Djakov1-0/+1
The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs, a primary (A53) CPU PLL and a secondary fixed-rate GPLL0. These sources are connected to a mux and half-integer divider, which is feeding the CPU cores. This patch adds support for the primary CPU PLL which generates the higher range of frequencies above 1GHz. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Amit Kucheria <amit.kucheria@linaro.org> [sboyd@codeaurora.org: Move to devm provider registration, NUL terminate frequency table, made tristate/modular] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-06clk: qcom: Add spmi_pmic clock divider supportTirupathi Reddy1-0/+1
Clkdiv module provides a clock output on the PMIC with CXO as the source. This clock can be routed through PMIC GPIOs. Add a device driver to configure this clkdiv module. Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org> [sboyd: Simplified code and moved to devm clk provider APIs] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-11-02License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman1-0/+1
Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-06-19clk: qcom: Add ipq8074 Global Clock Controller supportAbhishek Sahu1-0/+1
This patch adds support for the global clock controller found on the ipq8074 based devices. This includes UART, I2C, SPI etc. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-10Merge branch 'clk-qcom-rpm' into clk-nextStephen Boyd1-0/+2
* clk-qcom-rpm: clk: qcom: Add support for RPM Clocks clk: qcom: Add support for SMD-RPM Clocks clk: qcom: Always add factor clock for xo clocks
2016-11-10clk: qcom: Add support for RPM ClocksGeorgi Djakov1-0/+1
This adds initial support for clocks controlled by the Resource Power Manager (RPM) processor on some Qualcomm SoCs, which use the qcom_rpm driver to communicate with RPM. Such platforms are apq8064 and msm8960. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-10clk: qcom: Add support for SMD-RPM ClocksGeorgi Djakov1-0/+1
This adds initial support for clocks controlled by the Resource Power Manager (RPM) processor on some Qualcomm SoCs, which use the qcom_smd_rpm driver to communicate with RPM. Such platforms are msm8916, apq8084 and msm8974. The RPM is a dedicated hardware engine for managing the shared SoC resources in order to keep the lowest power profile. It communicates with other hardware subsystems via shared memory and accepts clock requests, aggregates the requests and turns the clocks on/off or scales them on demand. This driver is based on the codeaurora.org driver: https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/clk/qcom/clock-rpm.c Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Acked-by: Rob Herring <robh@kernel.org> [sboyd@codeaurora.org: Remove useless braces for single line if] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-10clk: qcom: Add support for msm8994 global clock controllerBastian Köcher1-0/+1
The clock definition was ported from the Google 3.10 kernel tree to work with the latest kernel. Signed-off-by: Bastian Köcher <mail@kchr.de> [jeremymc@redhat.com: created new commit of just dt-bindings] Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com> [sboyd@codeaurora.org: Tidy up commit text and Kconfig help] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-15clk: qcom: Sort Makefile alphabeticallyStephen Boyd1-3/+4
We've started getting out of order, fix it. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-15clk: mdm9615: Add support for MDM9615 Clock ControllersNeil Armstrong1-0/+2
In order to support the Qualcomm MDM9615 SoC, add support for the Global and LPASS Clock Controllers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-25clk: qcom: Add IPQ4019 Global Clock Controller supportVaradarajan Narayanan1-0/+1
This patch adds support for the global clock controller found on the IPQ4019 based devices. This includes UART, I2C, SPI etc. Signed-off-by: Pradeep Banavathi <pradeepb@codeaurora.org> Signed-off-by: Senthilkumar N L <snlakshm@codeaurora.org> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Acked-by: Andy Gross <andy.gross@linaro.org> [sboyd@codeaurora.org: Drop 0x16024 enable_reg in crypto_ahb] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-11-30clk: qcom: Add MSM8996 Multimedia Clock Controller (MMCC) driverStephen Boyd1-0/+1
Add a driver for the multimedia clock controller found on MSM8996 based devices. This should allow most multimedia device drivers to probe and control their clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-11-30clk: qcom: Add MSM8996 Global Clock Control (GCC) driverStephen Boyd1-0/+1
Add support for the global clock controller found on MSM8996 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-11-30clk: qcom: Add Alpha PLL supportStephen Boyd1-0/+1
Add support for configuring rates of, enabling, and disabling Alpha PLLs. This is sufficient for the types of PLLs found in the global and multimedia clock controllers. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-09-16clk: qcom: Add support for GDSCsStephen Boyd1-0/+1
GDSCs (Global Distributed Switch Controllers) are responsible for safely collapsing and restoring power to peripherals in the SoC. These are best modelled as power domains using genpd and given the registers are scattered throughout the clock controller register space, its best to have the support added through the clock driver. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-03-23clk: qcom: Add MSM8916 Global Clock Controller supportGeorgi Djakov1-0/+1
This patch adds support for the global clock controller found on the MSM8916 based devices. It allows the various device drivers to probe and control their clocks and resets. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> [sboyd@codeaurora.org: Removed NULL entry from parent_maps] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-01-27clk: qcom: Add MSM8960/APQ8064 LPASS clock controller (LCC) driverStephen Boyd1-0/+1
Add an LCC driver for MSM8960/APQ8064 that supports the i2s, slimbus, and pcm clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-27clk: qcom: Add IPQ806X LPASS clock controller (LCC) driverRajendra Nayak1-0/+1
Add an LCC driver for IPQ806x that supports the i2s, S/PDIF, and pcm clocks. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Josh Cartwright <joshc@codeaurora.org> [sboyd@codeaurora.org: Reworded commit text, added Kconfig select, fleshed out Kconfig description a bit more, added pll4 configuration and reworked probe for it, added muxes, split out dt-binding file] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-27clk: qcom: Add simple regmap based muxesStephen Boyd1-0/+1
Add support for muxes that use regmap instead of readl/writel directly. We don't support as many features as clk-mux.c, but this is good enough to support getting and setting parents. Adding a table based lookup can be added in the future if needed. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-27clk: qcom: Add support for regmap divider clocksJosh Cartwright1-0/+1
Add support for dividers that use regmap instead of readl/writel. Signed-off-by: Josh Cartwright <joshc@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> [sboyd@codeaurora.org: Switch to using generic divider code, drop enable/disable, reword commit text] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-07-15clk: qcom: Add support for IPQ8064's global clock controller (GCC)Kumar Gala1-0/+1
Add a driver for the global clock controller found on IPQ8064 based platforms. This should allow most non-multimedia device drivers to probe and control their clocks. This is currently missing clocks for USB HSIC and networking devices. Signed-off-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-07-15clk: qcom: Add APQ8084 Multimedia Clock Controller (MMCC) supportGeorgi Djakov1-0/+1
Add support for the multimedia clock controller found on the APQ8084 based platforms. This will allow the multimedia device drivers to control their clocks. Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com> [sboyd: Rework parent mapping to avoid conflicts] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-07-11clk: qcom: Add APQ8084 Global Clock Controller supportGeorgi Djakov1-0/+1
This patch adds support for the global clock controller found on the APQ8084 based devices. This includes UART, I2C, SPI etc. Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-04-30clk: qcom: Consolidate common probe codeStephen Boyd1-0/+1
Most of the probe code is the same between all the different clock controllers. Consolidate the code into a common.c file. This makes changes to the common probe parts easier and reduces chances for bugs. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-17clk: qcom: Fix modular buildStephen Boyd1-6/+6
According to Documentation/kbuild/makefiles.txt these symbols should be clk-qcom-y. Otherwise the build will fail if CONFIG_COMMON_CLK_QCOM=m. Fix it. Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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