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path: root/drivers/clk/renesas/r9a06g032-clocks.c (follow)
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2019-04-02clk: renesas: r9a06g032: Add missing PCI USB clockGareth Williams1-0/+1
The clock driver is missing support for the clk_pci_usb clock that is present on the SoC. This is added to allow the clock to be supported. Signed-off-by: Gareth Williams <gareth.williams.jx@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-12-10clk: renesas: Remove usage of CLK_IS_BASICStephen Boyd1-4/+4
This flag doesn't look to be used by any code, just set in various clk init structures and then never tested again. Remove it from these drivers as it doesn't provide any benefit. Cc: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: <linux-renesas-soc@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-09-11clk: renesas: r9a06g032: Fix UART34567 clock ratePhil Edworthy1-1/+2
The clock for UARTs 0 through 2 is UART012, the clock for UARTs 3 through 7 is UART34567. For UART012, we stop the clock driver from changing the clock rate. This is because the Synopsys UART driver simply sets the reference clock to 16x the baud rate, but doesn't check if the actual rate is within the required tolerance. The RZ/N1 clock divider can't provide this (we have to rely on the UART's internal divider to set the correct clock rate), so you end up with a clock rate that is way off what you wanted. In addition, since the clock is shared between multiple UARTs, you don't want the driver trying to change the clock rate as it may affect the other UARTs (which may not have been configured yet, so you don't know what baud rate they will use). Normally, the clock rate is set early on before Linux to some very high rate that supports all of the clock rates you want. This change stops the UART34567 clock rate from changing for the same reasons. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Fixes: 4c3d88526eba2143 ("clk: renesas: Renesas R9A06G032 clock driver") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-06-25clk: renesas: Renesas R9A06G032 clock driverMichel Pollet1-0/+893
This provides a clock driver for the Renesas R09A06G032. This uses a structure derived from both the R-Car Gen2 driver as well as the renesas-cpg-mssr driver. Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>