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path: root/drivers/clk/samsung/clk-exynos5250.c (follow)
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2016-06-02clk: samsung: exynos5250: Move sleep init function to init sectionKrzysztof Kozlowski1-2/+2
The exynos5250_clk_sleep_init() function can be moved to init section because it is referenced only from other init-level calls. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-06-02clk: samsung: exynos5250: Constify all clock initializersKrzysztof Kozlowski1-10/+10
All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-06-02clk: samsung: Remove useless check for return value of samsung_clk_initKrzysztof Kozlowski1-2/+1
The samsung_clk_init() cannot return NULL. Either it returns allocated memory or it panics. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-03-02clk: samsung: Remove CLK_IS_ROOTStephen Boyd1-5/+5
This flag is a no-op now. Remove usage of the flag. Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-24clk: samsung: exynos5250: Add DISP1 clocksTomeu Vizoso1-1/+13
When the DISP1 power domain is powered off, there's two clocks that need to be temporarily reparented to OSC, and back to their original parents when the domain is powered on again. We expose these two clocks in the DT bindings so that the DT node of the power domain can reference them. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
2015-07-28Merge branch 'v4.3-topic/clk-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into clk-nextMichael Turquette1-0/+31
2015-07-24clk: exynos5250: add cpu clock configuration data and instantiate cpu clockThomas Abraham1-0/+31
With the addition of the new Samsung specific cpu-clock type, the arm clock can be represented as a cpu-clock type. Add the CPU clock configuration data and instantiate the CPU clock type for Exynos5250. Cc: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> [b.zolnierkie: split exynos5250 support from the original patch] [b.zolnierkie: moved E5250_CPU_DIV[0,1] macros to clk-exynos5250.c] Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org> Tested-by: Javier Martinez Canillas <javier@dowhile0.org> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
2015-07-20clk: samsung: Properly include clk.h and clkdev.hStephen Boyd1-2/+0
Clock provider drivers generally shouldn't include clk.h because it's the consumer API. Only include clk.h in files that are using it. The clkdev.h header isn't always used either, so remove it and add in slab.h where files were relying on it to include slab for them. Cc: Chanwoo Choi <cw00.choi@samsung.com> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-07-26clk: samsung: Make of_device_id array constKrzysztof Kozlowski1-1/+1
Array of struct of_device_id may be be const as expected by of_match_table field and of_find_matching_node_and_match() function. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-30clk: samsung: Register clk provider only after registering its all clocksSylwester Nawrocki1-0/+2
Ensure the clock provider is not registered until after all its related clocks were created and are ready to use. Currently there are races possible and any (of_)clk_get() call right after a clock provider's clk_init_cb callback call may fail. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-06-30clk/exynos5250: fix bit number for tv sysmmu clockRahul Sharma1-1/+1
Change bit from 2 to 9 for tv (mixer) sysmmu clock. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Reviewed-by: Sachin Kamat <sachin.kamat@samsung.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-30Merge tag 'samsung-drivers-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/driversOlof Johansson1-0/+35
Merge "Samsung 2nd drivers for 3.16" from Kukjin Kim: This is including fix exynos cpufreq driver compilation with ARCH_MULTIPLATFORM. Even though this is a work around, this is required for support exynos multiplatform for a while and will be updated in near future. This is based on tags/samsung-exynos. * tag 'samsung-drivers-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (24 commits) cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM ARM: EXYNOS: Enable multi-platform build support ARM: EXYNOS: Consolidate Kconfig entries ARM: EXYNOS: Add support for EXYNOS5410 SoC ARM: EXYNOS: Support secondary CPU boot of Exynos3250 ARM: EXYNOS: Add Exynos3250 SoC ID ARM: EXYNOS: Add 5800 SoC support ARM: EXYNOS: initial board support for exynos5260 SoC clk: exynos5250: Add missing sysmmu clocks for DISP and ISP blocks cpufreq: exynos: Fix the compile error ARM: S3C24XX: move debug-macro.S into the common space ARM: S3C24XX: use generic DEBUG_UART_PHY/_VIRT in debug macro ARM: S3C24XX: trim down debug uart handling ARM: compressed/head.S: remove s3c24xx special case ARM: EXYNOS: Remove unnecessary inclusion of cpu.h ARM: EXYNOS: Migrate Exynos specific macros from plat to mach ARM: EXYNOS: Remove exynos_subsys registration ARM: EXYNOS: Remove duplicate lines in Makefile ARM: EXYNOS: use v7_exit_coherency_flush macro for cache disabling ARM: dts: Remove g2d_pd node for exynos5420 ... Signed-off-by: Olof Johansson <olof@lixom.net>
2014-05-26clk: exynos5250: Add missing sysmmu clocks for DISP and ISP blocksCho KyongHo1-0/+35
This patch adds the missing sysmmu clocks for Display and ISP blocks. Signed-off-by: Cho KyongHo <pullip.cho@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-05-26ARM: EXYNOS: Move arm core power down clock to exynos5250 common clockAmit Daniel Kachhap1-0/+42
Now with common clock support added for exynos5250 it is necessary to move this code to exynos5250 common clock driver as clock registers should be handled there. This change is tested in exynos5250 based arndale platform. Cc: Abhilash Kesavan <a.kesavan@samsung.com> Cc: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsugn.com> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com> [t.figa: Rebased onto current kernel sources.] Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-05-14clk: samsung: exynos5250: Add clocks for G3DArun Kumar K1-1/+14
This patch adds the required clocks for ARM Mali IP in Exynos5250. Signed-off-by: Arun Kumar K <arun.kk@samsung.com> [t.figa: Changed clock ID to avoid conflict with CLK_SSS] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14clk: samsung: exynos5250/5420: Add gate clock for SSS moduleNaveen Krishna Chatradhi1-0/+1
This patch adds gating clock for SSS(Security SubSystem) module on Exynos5250/5420. Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> [t.figa: Fixed sort order and group name.] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14clk/samsung: add support for multiple clock providersRahul Sharma1-10/+15
Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation, SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer. This layer is modified accordingly to enable the support for multiple clock providers. Clock file for exynos4, exynos5250, exynos5420, exynos5440, S3c64xx, S3c24xx are also modified as per changed helper functions. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> [t.figa: Modified s3c2410 clock driver as well] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-02-14clk: samsung: Drop old suspend/resume codeTomasz Figa1-1/+1
Since all SoC drivers have been moved to local suspend/resume handling, the old code can be safely dropped. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-02-14clk: samsung: exynos5250: Move suspend/resume handling to SoC driverTomasz Figa1-5/+44
Since there are multiple differences in how suspend/resume of particular Exynos SoCs must be handled, SoC driver is better place for suspend/resume handlers and so this patch moves them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-01-08clk: exynos5250: add clock ID for div_pcm0Andrew Bresticker1-1/+1
There is no gate for the PCM clock input to the AudioSS block, so the parent of sclk_pcm is div_pcm0. Add a clock ID for it so that we can reference it in device trees. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-08clk: exynos5250: replace clock ID private enums with IDs from DT headerAndrzej Hajda1-295/+264
The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-08clk: exynos5250: register APLL rate tableAndrew Bresticker1-1/+24
Register the APLL rate table so that we can set the APLL rate from the cpufreq driver. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30clk: exynos5250: Add CLK_SET_RATE_PARENT flag to mout_apllSachin Kamat1-1/+2
Add CLK_SET_RATE_PARENT flag to mout_apll clock. This will let us set the clock rate in the cpufreq driver. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30clk: samsung: exynos5250: Fix parents of gate clocks from MFC domainTomasz Figa1-3/+5
This patch adds mout_aclk333_sub mux clock and updates gate clocks from MFC domain to have it as their parent as specified in SoC documentation. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30clk: samsung: exynos5250: Correct parent list of audio muxesTomasz Figa1-3/+3
According to SoC documentation, input 5 of mout_audio muxes is connected to xxti (named fin_pll in the driver). This patch corrects defined parent arrays to match SoC documentation. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30clk: samsung: exynos5250: Add missing unpopulated mux parentsTomasz Figa1-4/+12
This patch updates mux parent arrays with unpopulated mux inputs, as all inputs need to be specified in parent arrays passed to clk_register_mux(), otherwise clk_set_parent() can generate out of bound accesses to the array. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30clk: samsung: exynos5250: Fix parent of gate clocks from DISP1 domainTomasz Figa1-6/+8
This patch adds mux_aclk_200_disp1_sub mux clock, which according to SoC documentation is the correct parent of DISP1 gate clocks. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30clk: samsung: exynos5250: Fix parents of gate clocks from GSCL domainTomasz Figa1-8/+17
This patch adds mout_aclk266_gscl_sub mux clock and adjusts definitions of GSCL domain gate clocks to use it as their parent, as specified in SoC documentation. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30clk: samsung: exynos5250: Make names of mux and div clocks consistentTomasz Figa1-122/+123
This patch renames all mux clocks to start with mout_ prefix and all div clocks to start with div_ prefix for consistency with other clocks already defined this way. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30clk: samsung: exynos5250: Sort definitions by registers and bitfieldTomasz Figa1-102/+188
This patch reorders clock definitions, so they are sorted by register addresses and bitfield shifts. When at it, blank lines are added to separate definitions of clocks from different registers. Overall this should make the driver more readable and reduce the number of potential conflicts when adding new entries. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clockAbhilash Kesavan1-1/+2
The sysreg (system register) generates control signals for various blocks like disp1blk, i2c, mipi, usb etc. However, it gets disabled as an unused clock at boot-up. This can lead to failures in operation of above blocks, because they can not be configured properly if this clock is disabled. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> [t.figa: Updated patch description.] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30clk: samsung: exynos5250: Add MDMA0 clocksAbhilash Kesavan1-1/+4
Adds gate clock for MDMA0 on Exynos5250 SoC. This is needed to ensure that the clock is enabled when MDMA0 is used on systems on which firmware gates the clockby default. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> [t.figa: Updated patch description.] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30clk: samsung: exynos5250: Fix ACP gate register offsetAbhilash Kesavan1-1/+1
The CLK_GATE_IP_ACP register offset is incorrectly listed making definition of g2d clock incorrect, which may lead to system failures when trying to use G2D on systems on which firmware gates this clock by default. Fix this and the register ordering as well. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> [t.figa: Updated patch description.] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30clk: exynos5250: fix sysmmu_mfc{l,r} gate clocksAndrew Bresticker1-2/+2
The gate clocks for the MFC sysmmus appear to be flipped, i.e. GATE_IP_MFC[2] gates sysmmu_mfcl and GATE_IP_MFC[1] gates sysmmu_mfcr. Fix this so that the MFC will start up. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2013-09-06clk: samsung: exynos5250: Simplify registration of PLL rate tablesTomasz Figa1-10/+2
Since the _get_rate() helper has been modified to use __clk_lookup() internally, checking of PLL input rates can be done using it and so the registration code can be simplified. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-28clk/exynos5250: change parent to aclk200_disp1 for hdmi subsystemRahul Sharma1-2/+2
parent of hdmi and mixer block is mentioned as aclk200 which is not correct. It is clocked by the ouput of aclk200_disp1. Hence parent for mixer and hdmi clocks is changed to aclk200_disp1. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-08clk: exynos5250: Fix incorrect placement of __initdataSachin Kamat1-5/+5
__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-08clk: exynos5250: Make exynos5250_plls staticSachin Kamat1-1/+1
exynos5250_plls is used only in this file. Make it static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-02clk: samsung: Add EPLL and VPLL freq table for exynos5250 SoCVikas Sajjan1-0/+38
Adds the EPLL and VPLL freq table for exynos5250 SoC. Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-02clk: samsung: Reorder MUX registration for mout_vpllsrcVikas Sajjan1-1/+6
While trying to get rate of "mout_vpllsrc" MUX (parent) for registering the "fout_vpll" (child), we found get rate was failing. So this patch moves the mout_vpllsrc MUX out of the existing common list and registers the mout_vpllsrc MUX before the PLL registrations. Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-02clk: samsung: Add support to register rate_table for samsung pllsYadwinder Singh Brar1-7/+7
This patch defines a common rate_table which will contain recommended p, m, s, k values for supported rates that needs to be changed for changing corresponding PLL's rate. Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-02clk: samsung: Migrate exynos5250 to use common samsung_clk_register_pll()Yadwinder Singh Brar1-19/+41
This patch migrates exynos5250 pll registeration to use common samsung_clk_register_pll() by intialising table of PLLs and adding PLLs to unique id list of clocks. Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-07-30clk/exynos5250: add sclk_hdmiphy in the list of special clocksRahul Sharma1-2/+2
hdmi driver needs hdmiphy clock which is one of the parent for hdmi mux clock. This is required while changing the parent of mux clock. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-07-30clk/exynos5250: add mout_hdmi mux clock for hdmiRahul Sharma1-1/+4
hdmi driver needs to change the parent of hdmi clock frequently between pixel clock and hdmiphy clock. hdmiphy is not stable after power on and for a short interval while changing the phy configuration. For this duration pixel clock is used to clock hdmi. This patch is exposing the mux for changing parent. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-07-29clk: exynos5250: Add G2D gate clockSachin Kamat1-1/+4
Adds gate clock for G2D IP for Exynos5250 SoC. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-07-25clk: exynos5250: Staticize local symbolsSachin Kamat1-7/+7
Symbols referenced only in this file are made static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-07-02Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds1-2/+3
Pull ARM SoC driver specific changes from Arnd Bergmann: "These changes are all driver specific and cross over between arm-soc contents and some other subsystem, in these cases cpufreq, crypto, dma, pinctrl, mailbox and usb, and the subsystem owners agreed to have these changes merged through arm-soc. As we proceed to untangle the dependencies between platform code and driver code, the amount of changes in this category is fortunately shrinking, for 3.11 we have 16 branches here and 101 non-merge changesets, the majority of which are for the stedma40 dma engine driver used in the ux500 platform. Cleaning up that code touches multiple subsystems, but gets rid of the dependency in the end. The mailbox code moved out from mach-omap2 to drivers/mailbox is an intermediate step and is still omap specific at the moment. Patches exist to generalize the subsystem and add other drivers with the same API, but those did not make it for 3.11." * tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (101 commits) crypto: ux500: use dmaengine_submit API crypto: ux500: use dmaengine_prep_slave_sg API crypto: ux500: use dmaengine_device_control API crypto: ux500/crypt: add missing __iomem qualifiers crypto: ux500/hash: add missing static qualifiers crypto: ux500/hash: use readl on iomem addresses dmaengine: ste_dma40: Declare memcpy config as static ARM: ux500: Remove mop500_snowball_ethernet_clock_enable() ARM: ux500: Correct the EN_3v3 regulator's on/off GPIO ARM: ux500: Provide a AB8500 GPIO Device Tree node gpio: rcar: fix gpio_rcar_of_table gpio-rcar: Remove #ifdef CONFIG_OF around OF-specific sections gpio-rcar: Reference core gpio documentation in the DT bindings clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2 ARM: dts: Update Samsung I2S documentation ARM: dts: add clock provider information for i2s controllers in Exynos5250 ARM: dts: add Exynos audio subsystem clock controller node clk: samsung: register audio subsystem clocks using common clock framework ARM: dts: use #include for all device trees for Samsung pinctrl: s3c24xx: use correct header for chained_irq functions ...
2013-06-19clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2Padmavathi Venna1-2/+3
This patch adds enum entries for div_i2s1 and div_i2s2 which are required for i2s1 and i2s2 controllers. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-06-11clk: exynos5250: Add CLK_IGNORE_UNUSED flag for pmu clockTushar Behera1-1/+1
Currently 'pmu' clock is not handled by any of the drivers. Also before the introduction of CCF, this clock was not defined, hence was left enabled always. When this clock is disabled, software reset register becomes inaccessible and system reboot doesn't work. Upon restoring the default behaviour, system reboot starts working. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-10clk: exynos5250: Add sclk_mpll to the parent list of mout_cpu clockTushar Behera1-1/+1
'mout_mpll' is added the list of parent clocks for 'mout_cpu'. 'mout_mpll' is an alias to the clock 'sclk_mpll'. Hence 'sclk_mpll' should be added to the list of parent clocks. This results in an error when cpufreq driver for EXYNOS5250 tries to set 'mout_mpll' as a parent for 'mout_cpu'. clk_set_parent: clk sclk_mpll can not be parent of clk mout_cpu Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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