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2015-09-29clk: atlas7: fix noc/socket disconnect/reconnect for unit clksGuo Zeng1-146/+188
Power management on of NoC(Notwork On Chip) requires that disconnect and reconnect routine should been done during clk disable/enable. also there are different types of clocks, For NoC Macro clocks, write idle_bit and wait for hardward ACK; For Socket clocks, write idle_bit; For others, do nothing. Signed-off-by: Guo Zeng <Guo.Zeng@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-09-29clk: atlas7: move variable-definition togetherGuo Zeng1-12/+12
re-order the codes more reasonable by moving variable-definition together. Signed-off-by: Guo Zeng <Guo.Zeng@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-08-24clk: atlas7: fix pll missed divide NR in fraction modeGuo Zeng1-0/+1
PLL VCO frequency is given by Fvco = Fref * 2 * NF / NR in integer-N mode, or by Fvco = Fref * SSN / NR in Spread Spectrum (fractional-N) mode. Thus fix the missing part of NR Signed-off-by: Guo Zeng <guo.zeng@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24clk: atlas7: fix bit field and its root clk for coresight_tpiuGuo Zeng1-1/+1
bit4 thcpum_cpudiv4_clken r/w thcpum_cpudiv4_clk clock enable (default: 1) Root clock CPU_CLK must be enabled for this clock to be enabled bit3 coresight_tpiu_clken r/w coresight_tpiu_clk clock enable (default: 0) Root clock TPIU_CLK must be enabled for this clock to be enabled Signed-off-by: Guo Zeng <guo.zeng@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24clk: atlas7: replace dto resolution magic number by macroYibo Cai1-5/+8
Signed-off-by: Yibo Cai <yibo.cai@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24clk: atlas7: fix integer overflow in dto rate calculationYibo Cai1-2/+2
I cannot believe that I spend quite a lot time in finding this bug. It seems a pitfall people tend to fall in. In "int64 = int32 * int32", conversion from 32-bits to 64-bits comes after the multiplication. So this statement may not work as expected. Signed-off-by: Yibo Cai <yibo.cai@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24clk: atlas7: export mux clks so that consumers can get themGuo Zeng1-2/+3
this patch makes mux clks can be referenced by device drivers. Signed-off-by: Guo Zeng <guo.zeng@csr.com> Signed-off-by: Barry Song <Barry.Song@csr.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24clk: atlas7: add lost pwm unit clksGuo Zeng1-0/+4
Signed-off-by: Guo Zeng <Guo.Zeng@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24clk: sirf: Convert to clk_hw based provider APIsStephen Boyd1-6/+6
We're removing struct clk from the clk provider API, so switch this code to using the clk_hw based provider APIs. Cc: Barry Song <Baohua.Song@csr.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-20clk: sirf: Properly include clk.hStephen Boyd3-2/+2
Clock provider drivers generally shouldn't include clk.h because it's the consumer API. Move the include of clk.h into clk-common.c because that's the only file that's really using clk.h, even if it's included into the atlas6 and prima2 files. Cc: Barry Song <Baohua.Song@csr.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-20clk: sirf: add CSR atlas7 clk and reset supportZhiwu Song2-1/+1633
the hardware node includes both clock and reset support, so it is named as "car". this patch implements Flexible clocks(mux, divider, gate), Selectable clock(mux, divider, gate), root clock(gate),leaf clock(gate), others. it also implements the reset controller functionality. Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com> Signed-off-by: Guo Zeng <Guo.Zeng@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-14clk: sirf: Silence sparse warningsStephen Boyd1-2/+2
These are __iomem pointers. Mark them appropriately so we don't get sparse errors like drivers/clk/sirf/clk-common.c:60:16: warning: incorrect type in argument 1 (different address spaces) drivers/clk/sirf/clk-common.c:60:16: expected void const volatile [noderef] <asn:2>*addr drivers/clk/sirf/clk-common.c:60:16: got void * Cc: Barry Song <Baohua.Song@csr.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-05clk: sirf: Constify parent names in clock init dataKrzysztof Kozlowski1-6/+6
The array of parent names can be made as array of const pointers to const strings. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-03-26clk: sirf: update copyright years to 2014Barry Song3-3/+6
Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-16clk: sirf: re-arch to make the codes support both prima2 and atlas6Barry Song6-0/+1395
sirfprima2 and sirfatlas6 are two different SoCs in CSR SiRF series. for prima2 and atlas6, there are many shared clocks but there are still some different register layout and hardware clocks, then result in different clock table. here we re-arch the driver to 1. clk-common.c provides common clocks for prima2 and atlas6, 2. clk-prima2.h describles registers of prima2 and clk-prima2.c provides prima2 specific clocks and clock table. 3. clk-atlas6.h describles registers of atlas6 and clk-atlas6.c provides atlas6 specific clocks and clock table. 4. clk.h and clk.c expose external interfaces and provide uniform entry for both prima2 and atlas6. so both prima2 and atlas6 will get support by drivers/clk/sirf. Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Rongjun Ying <Rongjun.Ying@csr.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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