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path: root/drivers/clk/tegra/clk-tegra20.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2013-04-04Merge branch 'for-3.10/soc' into for-3.10/clkStephen Warren1-34/+2
2013-04-01clk: tegra: Allow PLLE training to succeedThierry Reding1-1/+1
2013-03-11clk: tegra: No 7.1 super clk dividers on Tegra20Peter De Schrijver1-34/+2
2013-03-04clk: Tegra: Remove duplicate smp_twd clockPrashant Gaikwad1-1/+0
2013-02-13clk: tegra: initialise parent of uart clocksLaxman Dewangan1-2/+5
2013-02-13clk: tegra: fix driver to match DT bindingStephen Warren1-2/+2
2013-02-12clk: tegra: Add missing spinlock for hclk and pclkPeter De Schrijver1-4/+7
2013-01-28clk: tegra20: Implementing CPU low-power function for tegra_cpu_car_opsJoseph Lo1-0/+93
2013-01-28clk: tegra20: remove unused TEGRA_CLK_DUPLICATE()sPrashant Gaikwad1-17/+0
2013-01-28clk: tegra: add clock support for Tegra20Prashant Gaikwad1-0/+1273