Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2013-04-04 | Merge branch 'for-3.10/soc' into for-3.10/clk | 1 | -34/+2 | |
2013-04-01 | clk: tegra: Allow PLLE training to succeed | 1 | -1/+1 | |
2013-03-11 | clk: tegra: No 7.1 super clk dividers on Tegra20 | 1 | -34/+2 | |
2013-03-04 | clk: Tegra: Remove duplicate smp_twd clock | 1 | -1/+0 | |
2013-02-13 | clk: tegra: initialise parent of uart clocks | 1 | -2/+5 | |
2013-02-13 | clk: tegra: fix driver to match DT binding | 1 | -2/+2 | |
2013-02-12 | clk: tegra: Add missing spinlock for hclk and pclk | 1 | -4/+7 | |
2013-01-28 | clk: tegra20: Implementing CPU low-power function for tegra_cpu_car_ops | 1 | -0/+93 | |
2013-01-28 | clk: tegra20: remove unused TEGRA_CLK_DUPLICATE()s | 1 | -17/+0 | |
2013-01-28 | clk: tegra: add clock support for Tegra20 | 1 | -0/+1273 |