aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/clk/tegra (follow)
AgeCommit message (Collapse)AuthorFilesLines
2014-11-26clk: tegra: Implement memory-controller clockThierry Reding6-4/+40
The memory controller clock runs either at half or the same frequency as the EMC clock. Reviewed-By: Tomeu Vizoso <tomeu.vizoso@collabora.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-09-18clk: tegra: Make clock initialization more robustTomeu Vizoso1-2/+7
Don't abort clock initialization if we cannot match an entry in tegra_clk_init_table to a valid entry in the clk array. Also log a corresponding error message. This was discovered when testing a patch that removed the EMC clock from tegra124_clks but left a mention in tegra_clk_init_table. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2014-09-18clk: tegra124: Add PLL_M_UD and PLL_C_UD clocksMikko Perttunen1-0/+8
These clocks are used as parents for some EMC timings. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
2014-08-08Merge tag 'cleanup-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds3-3/+8
Pull ARM SoC cleanups from Olof Johansson: "This merge window brings a good size of cleanups on various platforms. Among the bigger ones: - Removal of Samsung s5pc100 and s5p64xx platforms. Both of these have lacked active support for quite a while, and after asking around nobody showed interest in keeping them around. If needed, they could be resurrected in the future but it's more likely that we would prefer reintroduction of them as DT and multiplatform-enabled platforms instead. - OMAP4 controller code register define diet. They defined a lot of registers that were never actually used, etc. - Move of some of the Tegra platform code (PMC, APBIO, fuse, powergate) to drivers/soc so it can be shared with 64-bit code. This also converts them over to traditional driver models where possible. - Removal of legacy gpio-samsung driver, since the last users have been removed (moved to pinctrl) Plus a bunch of smaller changes for various platforms that sort of dissapear in the diffstat for the above. clps711x cleanups, shmobile header file refactoring/moves for multiplatform friendliness, some misc cleanups, etc" * tag 'cleanup-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (117 commits) drivers: CCI: Correct use of ! and & video: clcd-versatile: Depend on ARM video: fix up versatile CLCD helper move MAINTAINERS: Add sdhci-st file to ARCH/STI architecture ARM: EXYNOS: Fix build breakge with PM_SLEEP=n MAINTAINERS: Remove Kirkwood ARM: tegra: Convert PMC to a driver soc/tegra: fuse: Set up in early initcall ARM: tegra: Always lock the CPU reset vector ARM: tegra: Setup CPU hotplug in a pure initcall soc/tegra: Implement runtime check for Tegra SoCs soc/tegra: fuse: fix dummy functions soc/tegra: fuse: move APB DMA into Tegra20 fuse driver soc/tegra: Add efuse and apbmisc bindings soc/tegra: Add efuse driver for Tegra ARM: tegra: move fuse exports to soc/tegra/fuse.h ARM: tegra: export apb dma readl/writel ARM: tegra: Use a function to get the chip ID ARM: tegra: Sort includes alphabetically ARM: tegra: Move includes to include/soc/tegra ...
2014-07-17ARM: tegra: Convert PMC to a driverThierry Reding1-1/+1
This commit converts the PMC support code to a platform driver. Because the boot process needs to call into this driver very early, also set up a minimal environment via an early initcall. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-17ARM: tegra: Move includes to include/soc/tegraThierry Reding3-3/+8
In order to not clutter the include/linux directory with SoC specific headers, move the Tegra-specific headers out into a separate directory. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-08clk: tegra: Use XUSB-compatible SATA PLL sequenceMikko Perttunen1-0/+11
Use a sequence for enabling hardware control of the SATA PLL that works both when using the SATA lane with SATA and when using it with XUSB. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
2014-06-30clk: tegra: export clock names for debuggingPeter De Schrijver1-0/+6
When writing a module for testing or debugging purposes, there is no way to get hold of clk handles. This patch solves this by exposing all valid clocks as clkdev's for the virtual device tegra-clk-debug. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2014-06-27clk: tegra124: init table updatesPeter De Schrijver1-0/+6
Ensure some clocks critical for system operation are always. Also enable csite for JTAG debugging and set the tsensor and soc_therm clock frequencies for the upcoming soctherm driver. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2014-06-25clk: tegra: Add SATA clocks to Tegra124 initialization tableMikko Perttunen1-0/+2
This adds two clocks, SATA and SATA_OOB, to the Tegra124 clock initialization table. The clocks are needed for working SATA support. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2014-06-25clk: tegra: Enable hardware control of SATA PLLMikko Perttunen1-0/+8
This makes the SATA PLL be controlled by hardware instead of software. This is required for working SATA support. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2014-06-25clk: tegra: fix vi_sensor clocks on Tegra124Peter De Schrijver3-4/+33
vi_sensor and vi_sensor2 have a wrong hw clkid on Tegra124. Fix this by correcting the hw clkid for Tegra124 and creating the Tegra114 vi_sensor clock from its own data. Tegra124 was also using the wrong internal clock id. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2014-05-28Merge branch 'clk-fixes' into clk-nextMike Turquette1-21/+43
2014-05-27Merge tag 'clk-tegra-fixes-3.15' of git://nv-tegra.nvidia.com/user/pdeschrijver/linux into clk-fixesMike Turquette1-21/+43
PLLE fixes for 3.15
2014-05-22clk: tegra: Initialize xusb clocksAndrew Bresticker2-1/+12
Initialize the XUSB-related clocks with appropriate parents and rates for both Tegra114 and Tegra124. Signed-off-by: Jim Lin <jilin@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-05-22clk: tegra: Fix xusb_hs_src clock hierarchyAndrew Bresticker4-20/+17
Currently the Tegra1x4 clock init code hard-codes the mux setting for xusb_hs_src and treats it as a fixed-factor clock. It is, however, a mux which can be parented by either xusb_ss_src/2 or pll_u_60M. Add the fixed-factor clock xusb_ss_div2 and put an entry in periph_clks[] for the xusb_hs_src mux. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-05-22clk: tegra: Fix xusb_fs_src muxJim Lin1-1/+3
The parent-to-index mapping for xusb_fs_src is incorrect. Fix it by adding a mux table. Signed-off-by: Jim Lin <jilin@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-05-22clk: tegra: Enable hardware control of PLLEJim Lin1-1/+32
Enable hardware control of PLLE spread-spectrum, IDDQ, and enable controls when enabling PLLE. The hardware (e.g. XUSB) using PLLE will use these controls for power-saving optimizations. Signed-off-by: Jim Lin <jilin@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-05-16clk: tegra: Fix wrong value written to PLLE_AUXTuomas Tynkkynen1-1/+1
The value written to PLLE_AUX was incorrect due to a wrong variable being used. Without this fix SATA does not work. Cc: stable@vger.kernel.org Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: improved changelog]
2014-04-24clk: tegra: remove non-existent clocksStephen Warren1-3/+0
The Tegra124 clock driver currently provides 3 clocks that don't actually exist; 2 for NAND and one for UART5/UARTE. Delete these. Cc: <stable@vger.kernel.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-04-17clk: tegra: Fix enabling of PLLEThierry Reding1-1/+1
When enabling the PLLE as its final step, clk_plle_enable() would accidentally OR in the value previously written to the PLLE_SS_CTRL register. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-04-17clk: tegra: Introduce divider mask and shift helpersThierry Reding1-20/+24
Add div{m,n,p}_shift() and div{m,n,p}_mask_shifted() helpers to make the code that modifies the m-, n- and p-divider fields of PLLs shorter and easier to read. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-04-17clk: tegra: Fix PLLE programmingThierry Reding1-6/+24
PLLE has M, N and P divider shift and width parameters that differ from the defaults. Furthermore, when clearing the M, N and P divider fields the corresponding masks were never shifted, thereby clearing only the lowest bits of the register. This lead to a situation where the PLLE programming would only work if the register hadn't been touched before. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2014-02-24Merge branch 'clk-fixes' into clk-nextMike Turquette7-31/+45
2014-02-23clk: tegra: Staticize tegra_clk_periph_no_gate_opsSachin Kamat1-1/+1
tegra_clk_periph_no_gate_ops is a local symbol. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-20clk: tegra124: remove gr2d and gr3d clocksPeter De Schrijver1-2/+0
Tegra124 does not have gr2d and gr3d clocks. They have been replaced by the vic03 and gpu clocks respectively. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2014-02-20clk: tegra: Fix vic03 mux indexPeter De Schrijver1-3/+1
The vic03 mux uses a linear mapping. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2014-02-17clk: tegra: use max divider if divider overflowsAndrew Bresticker1-1/+1
When requesting a rate less than the minimum clock rate for a divider, use the maximum divider value instead of bailing out with an error. This matches the behavior of the generic clock divider. Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17clk: tegra: cclk_lp has a pllx/2 dividerAndrew Bresticker1-1/+1
When pll_x is the parent of cclk_lp, PLLX_DIV2_BYPASS_LP determines whether cclk_lp output is divided by 2. Set TEGRA_DIVIDER_2 so that the clk_super driver is aware of this. Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17clk: tegra: fix sdmmc clks on Tegra1x4Andrew Bresticker4-8/+16
The sdmmc clocks on Tegra114 and Tegra124 are 3-bit wide muxes with 6 parents. Add support for tegra_clk_sdmmc*_8 and switch Tegra114 and Tegra124 to use these clocks instead. Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17clk: tegra: fix host1x clock on Tegra124Mark Zhang1-1/+1
The host1x clock on Tegra124 is a 3-bit wide mux with 6 parents. Change thte id to tegra_clk_host1x_8 so that the correct clock gets registered. Signed-off-by: Mark Zhang <markz@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17clk: tegra: PLLD2 fixes for hdmiDavid Ung1-8/+7
Set correct pll_d2_out0 divider and correct the p div values for pll_d2. Signed-off-by: David Ung <davidu@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17clk: tegra: Fix PLLD mnp tableRhyland Klein1-1/+10
PLLD was using the same mnp table as PLLP. Fix it to use its own table which is different from PLLP's. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17clk: tegra: Fix PLLP rate tableGabe Black1-5/+5
This table had settings for 216MHz, but PLLP is (and is supposed to be) configured at 408MHz. If that table is used and PLLP_BASE_OVRRIDE is not set, the kernel will panic in clk_pll_recalc_rate(). Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17clk: tegra: Correct clock number for UARTEThierry Reding1-1/+1
UARTE has clock number 66. Number 65 is the right one for UARTD. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-02-17clk: tegra: Add missing Tegra20 fuse clksPeter De Schrijver1-0/+2
Add clocks required for accessing fuses on Tegra20. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2014-01-23Merge tag 'clk-for-linus-3.14-part1' of git://git.linaro.org/people/mike.turquette/linuxLinus Torvalds2-7/+7
Pull clk framework changes from Mike Turquette: "The first half of the clk framework pull request is made up almost entirely of new platform/driver support. There are some conversions of existing drivers to the common-clock Device Tree binding, and a few non-critical fixes to the framework. Due to an entirely unnecessary cyclical dependency with the arm-soc tree this pull request is broken into two pieces. The second piece will be sent out after arm-soc sends you the pull request that merged in core support for the HiSilicon 3620 platform. That same pull request from arm-soc depends on this pull request to merge in those HiSilicon bits without causing build failures" [ Just did the ARM SoC merges, so getting ready for the second clk tree pull request - Linus ] * tag 'clk-for-linus-3.14-part1' of git://git.linaro.org/people/mike.turquette/linux: (97 commits) devicetree: bindings: Document qcom,mmcc devicetree: bindings: Document qcom,gcc clk: qcom: Add support for MSM8660's global clock controller (GCC) clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC) clk: qcom: Add support for MSM8974's global clock controller (GCC) clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC) clk: qcom: Add support for MSM8960's global clock controller (GCC) clk: qcom: Add reset controller support clk: qcom: Add support for branches/gate clocks clk: qcom: Add support for root clock generators (RCGs) clk: qcom: Add support for phase locked loops (PLLs) clk: qcom: Add a regmap type clock struct clk: Add set_rate_and_parent() op reset: Silence warning in reset-controller.h clk: sirf: re-arch to make the codes support both prima2 and atlas6 clk: composite: pass mux_hw into determine_rate clk: shmobile: Fix MSTP clock array initialization clk: shmobile: Fix MSTP clock index ARM: dts: Add clock provider specific properties to max77686 node clk: max77686: Register OF clock provider ...
2013-12-19clk: tegra: Staticize tegra_clk_periph_nodiv_opsSachin Kamat1-1/+1
tegra_clk_periph_nodiv_ops is used only in this file. Make it static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-12-19clk: tegra: Staticize local variables in clk-pll.cSachin Kamat1-6/+6
Local variables used only in this file are made static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-12-11clk: tegra: remove bogus PCIE_XCLKStephen Warren2-13/+0
The "pcie_xclk" clock is not actually a clock at all, but rather a reset domain. Now that the custom Tegra module reset API has been removed, we can remove the definition of any "clocks" that existed solely to support it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-12-11clk: tegra: remove legacy reset APIsStephen Warren3-63/+0
Now that no code uses the custom Tegra module reset API, we can remove its implementation. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-12-11clk: tegra: implement a reset driverStephen Warren6-6/+57
The Tegra CAR module implements both a clock and reset controller. So far, the driver exposes the clock feature via the common clock API and the reset feature using a custom API. This patch adds an implementation of the common reset framework API (include/linux/reset*.h). The legacy reset implementation will be removed once all drivers have been converted. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-28clk: tegra: fix __clk_lookup() return value checksWei Yongjun1-4/+4
In case of error, the function __clk_lookup() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-28clk: tegra: Do not print errors for clk_round_rate()Thierry Reding1-6/+3
clk_round_rate() can be used by drivers to determine whether or not a frequency is supported by the clock. The current Tegra clock driver outputs an error message and a stacktrace when the requested rate isn't supported. That's fine for clk_set_rate(), but it's confusing when all the driver does is query whether or not a frequency is supported. Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-11-26clk: tegra: Initialize DSI low-power clocksThierry Reding1-0/+2
The low-power DSI clocks are used during host-driven transactions on the DSI bus. Documentation recommends that they be children of PLLP and run at a frequency of at least 52 MHz. Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-11-26clk: tegra: add FUSE clock deviceAlexandre Courbot4-1/+4
This clock is needed to ensure the FUSE registers can be accessed without freezing the system. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
2013-11-26clk: tegra: Properly setup PWM clock on Tegra30Thierry Reding1-1/+3
The clock for the PWM controller is slightly different from other peripheral clocks on Tegra30. The clock source mux field start at bit position 28 rather than 30. Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-11-26clk: tegra: Initialize secondary gr3d clock on Tegra30Thierry Reding1-0/+1
There are two GPUs on Tegra30 and each of them uses a separate clock, so the secondary clock needs to be initialized in order for the gr3d module to work properly. Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-11-26clk: tegra114: Initialize clocks needed for HDMIMikko Perttunen1-0/+2
Add disp1 and disp2 clocks to the clock initialization table. These clocks are required for display and HDMI support. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-11-26clk: tegra124: add suspend/resume function for tegra_cpu_car_opsJoseph Lo1-0/+27
Adding suspend/resume function for tegra_cpu_car_ops. We only save and restore the setting of the clock of CoreSight. Other clocks still need to be taken care by clock driver. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.