| Age | Commit message (Collapse) | Author | Files | Lines |
|---|
|
If a device is part of the CPG/MSSR Clock Domain and to be used as a
wakeup source, it must be kept active during system suspend.
Currently this is handled in device-specific drivers by explicitly
increasing the use count of the module clock when the device is
configured as a wakeup source. However, the proper way to prevent the
device from being stopped is to inform this requirement to the genpd
core, by setting the GENPD_FLAG_ACTIVE_WAKEUP flag.
Note that this will only affect devices configured as wakeup sources.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
|
|
If a device is part of the CPG/MSTP Clock Domain and to be used as a
wakeup source, it must be kept active during system suspend.
Currently this is handled in device-specific drivers by explicitly
increasing the use count of the module clock when the device is
configured as a wakeup source. However, the proper way to prevent the
device from being stopped is to inform this requirement to the genpd
core, by setting the GENPD_FLAG_ACTIVE_WAKEUP flag.
Note that this will only affect devices configured as wakeup sources.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
|
|
Add clock controller drivers for Amlogic Meson-AXG SoC.
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
|
|
Make the spinlock more specific, so better for lockdep
debugging and ctags/grep.
Suggested-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
|
|
Some of the divider settings are preconfigured and should not
be changed by the clock framework during frequency change. This
patch adds the read-only divider operation for QCOM alpha pll
post divider which is equivalent to generic divider operations in
'commit 79c6ab509558 ("clk: divider: add CLK_DIVIDER_READ_ONLY flag")'.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
Current PLL driver only supports 4 bit PLL post divider so
modified the PLL divider operations to support 2 bit PLL
post divider.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
The Brammo type of Alpha PLL doesn't allow configuration of a
VCO, but it does support dynamic update in which the frequency
can be changed dynamically without turning off the PLL.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
The Huayra type Alpha PLL has a 16 bit alpha value, and
depending on the alpha_mode, the alpha value can be treated as
M/N value or as a two’s compliment number. This PLL supports
dynamic programming.
Since the decoding of alpha val and dynamic programming are
completely different from other Alpha PLLs we add separate
functions for Huayra PLLs.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
Some of the Alpha PLLs support dynamic update in which the
frequency can be changed dynamically without turning off the PLL.
This dynamic update requires the following sequence:
1. Write the desired values to L_VAL and ALPHA_VAL registers
2. Toggle pll_latch_input from low to high
3. Wait for pll_ack_latch to transition from low to high
The new L and alpha values have been latched. It may
take some time for the PLL to fully settle with these
new values.
4. Pull pll_latch_input low
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
The current configuration does not fully configure PLL alpha mode
and values so this patch
1. Configures PLL_ALPHA_VAL_U for PLL which supports 40 bit alpha.
2. Adds alpha enable and alpha mode configuration support.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
Some of the Alpha PLLs (like Spark and Brammo) don't have a
CONFIG_CTL_U register. Add logic to detect when PLLs don't have
this second config register and skip programming it during PLL
initialization.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
The alpha value calculation has been written for 40-bit alpha
values which doesn't work work properly for 16-bit ones. The
alpha value is calculated on the basis of ALPHA_BITWIDTH to make
the computation easy for 40 bit alpha. After calculating the 32
bit alpha, it is converted to 40 bit alpha by making lower bits
zero. But if actual alpha register width is less than
ALPHA_BITWIDTH, then the actual width can be used for
calculation. This also means, during the 40 bit alpha pll set
rate path, the lower alpha register is not configured
Change the code to calculate the rate and register values from
'alpha_width' instead of hard-coding it so that it can work for
the different widths that are supported.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
Alpha PLL is a generic name used for QCOM PLLs which uses L and
Alpha values for configuring the integer and fractional part.
QCOM SoCs use different types of Alpha PLLs for which basic
software configuration part is common with following differences.
1. All these PLLs have the same basic registers like
PLL_MODE, L_VAL, ALPHA_VAL but some of the register offsets are
different between PLLs types.
2. The dynamic programming sequence is different in some
of the Alpha PLLs
3. Some of the PLLs don’t have 64 bit config control, 64 bit
user control, VCO configuration, etc.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
Remove CLK_IGNORE_UNUSED from mmc clocks. This was only needed while the
mmc driver incorrectly used the xtal as source instead of the mmc
clock. Now, the driver takes the correct clock, CCF is aware that the
clock is being used and we can remove this flag.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
|
|
I seem to have omitted the LVDS clock from the R8A77970 CPG/MSSR support
patch for some reason -- add it back...
Based on the original (and large) patch by Daisuke Matsushita
<daisuke.matsushita.ns@hitachi.com>.
Fixes: 8d46e28fb5081b49 ("clk: renesas: cpg-mssr: Add R8A77970 support")
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
|
The audio blocks require specific clock rates. Until now we were using
the closest clock rate possible with integer N-M factors. This resulted
in audio playback being slightly slower than it should be.
The vendor kernel gets around this (for newer SoCs) by using sigma-delta
modulation to generate a fractional-N factor. This patch copies the
parameters for the A83T.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
On the A83T, the audio PLL should have its div1 set to 0, or /1, and
div2 set to 1, or /2. This setting is the default, and is required
to match the sigma-delta modulation parameters from the BSP kernel.
This patch adds a /2 fixed post divider to the audio PLL, and fixes
the enforced d1 & d2 values. This also resolves the mismatch between
the values mentioned in the comment for the audio PLL, and the actual
enforced values.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
On the A83T, the audio PLL should have its div1 set to 0, or /1, and
div2 set to 1, or /2. This setting is the default, and is required
to match the sigma-delta modulation parameters from the BSP kernel.
To do this, we first add fixed post-divider to the NM style clocks,
which is the type of clock the audio PLL clock is modeled into.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
On the A64, the MMC module clocks are fixed in the new timing mode,
i.e. they do not have a bit to select the mode. These clocks have
a 2x divider somewhere between the clock and the MMC module.
To be consistent with other SoCs supporting the new timing mode,
we model the 2x divider as a fixed post-divider on the MMC module
clocks.
This patch adds the post-dividers to the MMC clocks.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
On the A64, the MMC module clocks are fixed in the new timing mode,
i.e. they do not have a bit to select the mode. These clocks have
a 2x divider somewhere between the clock and the MMC module.
To be consistent with other SoCs supporting the new timing mode,
we model the 2x divider as a fixed post-divider on the MMC module
clocks.
To do this, we first add fixed post-divider to the MP style clocks,
which the MMC module clocks are.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
* '4.15-rc1-clkctrl-driver' of https://github.com/t-kristo/linux-pm: (28 commits)
clk: ti: omap4: clkctrl data fixes for opt-clocks
clk: ti: dm816: add clkctrl clock data
dt-bindings: clk: add dm816 clkctrl definitions
clk: ti: dm814: add clkctrl clock data
dt-bindings: clk: add dm814 clkctrl definitions
clk: ti: am43xx: add clkctrl clock data
dt-bindings: clk: add am43xx clkctrl definitions
clk: ti: am33xx: add clkctrl clock data
dt-bindings: clk: add am33xx clkctrl definitions
clk: ti: dra7: add clkctrl clock data
dt-bindings: clk: add dra7 clkctrl definitions
clk: ti: omap5: add clkctrl clock data
dt-bindings: clk: add omap5 clkctrl definitions
clk: ti: omap3: cleanup unnecessary clock aliases
clk: ti: am43xx: cleanup unnecessary clock aliases
clk: ti: am33xx: cleanup unnecessary clock aliases
clk: ti: dm816x: cleanup unnecessary clock aliases
clk: ti: dm814x: cleanup unnecessary clock aliases
clk: ti: omap5: cleanup unnecessary clock aliases
clk: ti: dra7: drop unnecessary clock aliases
...
|
|
* clk-stm32-copyright:
clk: stm32-h7: fix copyright
|
|
Uniformize STMicroelectronics copyrights header
Add SPDX identifier
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
CC: Gabriel Fernandez <gabriel.fernandez@st.com>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Acked-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
* clk-hi3660-stub:
clk: hisilicon: Add support for Hi3660 stub clocks
dt-bindings: clk: Hi3660: Document stub clock
|
|
Hi3660 has four stub clocks, which are big and LITTLE cluster clocks,
GPU clock and DDR clock. These clocks ask MCU for frequency scaling
by sending message through mailbox.
This commit adds support for stub clocks, it requests the dedicated
mailbox channel at initialization; then later uses this channel to send
message to MCU to execute frequency scaling. The four stub clocks share
the same mailbox channel, but every stub clock has its own command id so
MCU can distinguish the requirement coming for which clock.
A shared memory is used to present effective frequency value, so the
clock driver uses I/O mapping for the memory and reads back rate value.
Reviewed-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Kai Zhao <zhaokai1@hisilicon.com>
Signed-off-by: Tao Wang <kevin.wangtao@hisilicon.com>
Signed-off-by: Ruyi Wang <wangruyi@huawei.com>
Signed-off-by: Kaihua Zhong <zhongkaihua@huawei.com>
[sboyd: Fix possible out of bounds access in hi3660_stub_clk_hw_get(),
use devm_of_clk_add_hw_provider(), devm_ioremap() returns
NULL not error pointers]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
* clk-pr-err:
clk: h8300: pr_err() strings should end with newlines
clk: h8s2678: pr_err() strings should end with newlines
SPEAr: clk: pr_err() strings should end with newlines
clk: SPEAr: pr_err() strings should end with newlines
clk: lpc32xx: pr_err() strings should end with newlines
clk: stm32f4: pr_err() strings should end with newlines
|
|
pr_err() messages should end with a new-line to avoid other messages
being concatenated.
Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
pr_err() messages should end with a new-line to avoid other messages
being concatenated.
Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
pr_err() messages should end with a new-line to avoid other messages
being concatenated.
Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
pr_err() messages should end with a new-line to avoid other messages
being concatenated.
Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
pr_err() messages should end with a new-line to avoid other messages
being concatenated.
Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
pr_err() messages should end with a new-line to avoid other messages
being concatenated.
Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
* clk-qcom-spmi-div:
clk: qcom: Add spmi_pmic clock divider support
dt-bindings: Add qcom spmi_pmic clock divider bindings
|
|
* clk-qcom-audio-fixes:
clk: qcom: msm8916: add 12.288 MHz support to codec dig clk
clk: qcom: msm8916: fix mnd_width for codec_digcodec
clk: qcom: msm8916: Fix i2s clk rates required for mclk
|
|
This patch adds 12.288 MHz suport to codec digital clk, this clock.
Some external PA requires a 12.288 MHz to work.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
This patch fixes missing mnd_width for codec_digital clk, this is now set to
8 inline with datasheet.
Fixes: 3966fab8b6ab ("clk: qcom: Add MSM8916 Global Clock Controller support")
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
lpaif i2s clk rates in the freq table are not accurate enough
for I2S mclk. Fix the inaccurate ones and add few more clock
rates that are used in LPASS audio driver.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
Clkdiv module provides a clock output on the PMIC with CXO as
the source. This clock can be routed through PMIC GPIOs. Add
a device driver to configure this clkdiv module.
Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
[sboyd: Simplified code and moved to devm clk provider APIs]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
clk_change_rate() propagates rate change down to all its children. Such
operation requires managing proper runtime PM state of each child, what
was missing. Add needed calls to clk_pm_runtime*() to ensure that
set_rate() clock callback is called on runtime active clock.
This fixes following issue found on Exynos5433 TM2 board with devfreq
enabled:
Synchronous External Abort: synchronous external abort (0x96000210) at 0xffffff80093f5600
Internal error: : 96000210 [#1] PREEMPT SMP
Modules linked in:
CPU: 0 PID: 5 Comm: kworker/u16:0 Not tainted 4.15.0-rc1-next-20171129+ #4
Hardware name: Samsung TM2 board (DT)
Workqueue: devfreq_wq devfreq_monitor
task: ffffffc0ca96b600 task.stack: ffffff80093a8000
pstate: a0000085 (NzCv daIf -PAN -UAO)
pc : clk_divider_set_rate+0x54/0x118
lr : clk_divider_set_rate+0x44/0x118
...
Process kworker/u16:0 (pid: 5, stack limit = 0xffffff80093a8000)
Call trace:
clk_divider_set_rate+0x54/0x118
clk_change_rate+0xfc/0x4e0
clk_change_rate+0x1f0/0x4e0
clk_change_rate+0x1f0/0x4e0
clk_change_rate+0x1f0/0x4e0
clk_core_set_rate_nolock+0x138/0x148
clk_set_rate+0x28/0x50
exynos_bus_passive_target+0x6c/0x11c
update_devfreq_passive+0x58/0xb4
devfreq_passive_notifier_call+0x50/0x5c
notifier_call_chain+0x4c/0x88
__srcu_notifier_call_chain+0x54/0x80
srcu_notifier_call_chain+0x14/0x1c
update_devfreq+0x100/0x1b4
devfreq_monitor+0x2c/0x88
process_one_work+0x148/0x3d8
worker_thread+0x13c/0x3f8
kthread+0x100/0x12c
ret_from_fork+0x10/0x18
Reported-by: Chanwoo Choi <cw00.choi@samsung.com>
Fixes: 9a34b45397e5 ("clk: Add support for runtime PM")
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
Re-route all opt-clocks to use the new clkctrl clocks also, instead of
depending on the old dt clocks. Also, add aliases for certain clkctrl
clocks that hwmod core depends upon. The alias list can be stripped
down once hwmod database no longer needs these.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
|
|
Add data for dm816 clkctrl clocks, and register it within the clkctrl
driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
|
|
Add data for dm814 clkctrl clocks, and register it within the clkctrl
driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
|
|
Add data for am43xx clkctrl clocks, and register it within the clkctrl
driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
Add data for am33xx clkctrl clocks, and register it within the clkctrl
driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
|
|
Add data for dra7 clkctrl clocks, and register it within the clkctrl
driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
|
|
Add data for omap5 clkctrl clocks, and register it within the clkctrl
driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
|
|
Most of the clock aliases are no longer needed, only leave the ones
required by OMAP timer code in place.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
|
|
Most of the clock aliases are no longer needed, only leave the ones
required by OMAP timer code in place.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
|
|
Most of the clock aliases are no longer needed, only leave the ones
required by OMAP timer code in place.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
|
|
Most of the clock aliases are no longer needed, only leave the ones
required by OMAP timer code in place.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
|
Geert Uytterhoeven
Qiufang Dai
Yixun Lan
Abhishek Sahu
Jerome Brunet
Sergei Shtylyov
Chen-Yu Tsai
Stephen Boyd
Benjamin Gaignard
Kaihua Zhong
Arvind Yadav
Srinivas Kandagatla
Tirupathi Reddy
Marek Szyprowski
Tero Kristo