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path: root/drivers/clk (follow)
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2017-04-13clk: sunxi-ng: Fix round_rate/set_rate multiplier minimum mismatchChen-Yu Tsai2-3/+3
2017-04-13clk: sunxi-ng: use 1 as fallback for minimum multiplierChen-Yu Tsai4-11/+11
2017-04-13clk: sunxi-ng: a33: gate then ungate PLL CPU clk after rate changeChen-Yu Tsai1-0/+11
2017-04-13clk: sunxi-ng: Add clk notifier to gate then ungate PLL clocksChen-Yu Tsai2-0/+61
2017-04-13clk: sunxi-ng: fix build failure in ccu-sun9i-a80 driverTobias Regnery1-0/+1
2017-04-13clk: sunxi-ng: fix build error without CONFIG_RESET_CONTROLLERTobias Regnery1-0/+1
2017-04-12clk: cs2000: use existing priv_to_dev() to getting struct deviceKuninori Morimoto1-5/+3
2017-04-12Merge tag 'meson-clk-for-4.12' of git://github.com/BayLibre/clk-meson into clk-nextMichael Turquette6-13/+322
2017-04-12Merge tag 'amlogic-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into clk-nextMichael Turquette7-55/+854
2017-04-12clk: aggregate return codes of notify chainsPeter De Schrijver1-0/+2
2017-04-12clk: add clk_possible_parents debugfs filePeter De Schrijver1-0/+32
2017-04-12clk: imx: correct uart4_serial clock name in driver for i.MX6ULRobin van der Gracht1-1/+1
2017-04-12clk: zte: Mark pll config tables as constStephen Boyd1-2/+2
2017-04-12clk: zte: add pll_vga clock for zx296718Shawn Guo1-0/+24
2017-04-12clk: zte: pd_bit is not 0 on zx296718Shawn Guo2-2/+16
2017-04-12clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocksShawn Guo1-3/+3
2017-04-12clk: imx: clk-imx6ul: The i.mx6ul has no aips_tz3 clockRobin van der Gracht1-4/+5
2017-04-12Merge tag 'tegra-for-4.12-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-nextMichael Turquette14-253/+699
2017-04-12cs-2000-cp: keep Reserved bit on each registerKuninori Morimoto1-3/+22
2017-04-12clk: qcom: msm8996: Fix the vfe1 powerdomain nameRajendra Nayak1-1/+1
2017-04-12clk: stm32f4: fix timeout management for pll and ready gateGabriel Fernandez1-14/+29
2017-04-12clk: iproc: Remove redundant checkRay Jui1-1/+1
2017-04-12Merge tag 'v4.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-nextMichael Turquette7-238/+253
2017-04-12Merge tag 'clk-renesas-for-v4.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-nextMichael Turquette6-78/+299
2017-04-12Merge branch 'clk-fixes' into clk-nextStephen Boyd1-3/+10
2017-04-12clk: stm32f4: fix: exclude values 0 and 1 for PLLQGabriel Fernandez1-3/+10
2017-04-12Merge branch 'for-4.12-ti-clk-cleanups' of https://github.com/t-kristo/linux-pm into clk-nextStephen Boyd20-522/+501
2017-04-12clk: hi6220: add debug APB clockLeo Yan1-0/+1
2017-04-10clk: sunxi-ng: fix PRCM CCU CLK_NUMBER valueIcenowy Zheng1-1/+1
2017-04-10clk: sunxi-ng: fix PRCM CCU ir clk parentIcenowy Zheng1-1/+1
2017-04-07clk: meson: mpll: use 64bit math in rate_from_paramsMartin Blumenstingl1-1/+1
2017-04-07clk: meson: mpll: fix division by zero in rate_from_paramsMartin Blumenstingl1-11/+15
2017-04-07clk: meson: gxbb: add cts_i958 clockJerome Brunet2-1/+23
2017-04-07clk: meson: gxbb: add cts_mclk_i958Jerome Brunet2-1/+56
2017-04-07clk: meson: gxbb: add cts_amclkJerome Brunet2-1/+71
2017-04-07clk: meson: add audio clock divider supportJerome Brunet3-1/+155
2017-04-07clk: meson: gxbb: protect against holes in the onecell_data arrayJerome Brunet1-0/+4
2017-04-07ARM/clk: move the ICST library to drivers/clkLinus Walleij9-3/+170
2017-04-06clk: sunxi-ng: Display index when clock registration failsPriit Laes1-2/+2
2017-04-05clk: sunxi-ng: a33: Add offset and minimum value for DDR1 PLL N factorChen-Yu Tsai1-7/+11
2017-04-05clk: sunxi-ng: a80: Remodel CPU cluster PLLs as N-type multiplier clocksChen-Yu Tsai1-18/+52
2017-04-05clk: sunxi-ng: mult: Support PLL lock detectionChen-Yu Tsai2-0/+4
2017-04-04Merge branch 'v4.12/clk-drivers' into v4.12/clkKevin Hilman7-48/+840
2017-04-04clk: meson-gxbb: Add GXL/GXM GP0 VariantNeil Armstrong2-28/+275
2017-04-04clk: meson-gxbb: Add GP0 PLL init parametersNeil Armstrong1-0/+13
2017-04-04clk: meson: Add support for parameters for specific PLLsNeil Armstrong2-2/+74
2017-04-04clk: meson-gxbb: Add MALI clocksNeil Armstrong1-0/+139
2017-04-04clk: meson-gxbb: Expose GP0 dt-bindings clock idNeil Armstrong1-1/+1
2017-04-04clk: meson-gxbb: Add MALI clock IDSNeil Armstrong1-1/+8
2017-04-04dt-bindings: clk: gxbb: expose i2s output clock gatesJerome Brunet1-5/+5