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2013-06-11clk: tegra: pllp_out2 divider is int onlyPeter De Schrijver1-2/+2
The pllp_out2 should be integer only, the fractional bit should always be 0. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11ARM: socfpga: Add support to gate peripheral clocksDinh Nguyen1-9/+185
Add support to gate the clocks that directly feed peripherals. For clocks with multiple parents, add the ability to determine the correct parent, and also set parents. Also add support to calculate and set the clocks' rate. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Acked-by: Mike Turquette <mturquette@linaro.org> Cc: Mike Turquette <mturquette@linaro.org> CC: Arnd Bergmann <arnd@arndb.de> CC: Olof Johansson <olof@lixom.net> Cc: Pavel Machek <pavel@denx.de> CC: <linux@arm.linux.org.uk> v4: - Add Acked-by: Mike Turquette v3: - Addressed comments from Pavel v2: - Fix space/indent errors - Add streq for strcmp == 0 Signed-off-by: Olof Johansson <olof@lixom.net>
2013-06-11clk: tegra: pllc and pllxc should use pdiv_mapPeter De Schrijver1-80/+82
The pllc and pllxc code weren't always using the correct pdiv_map to map between the post divider value and the hw p field. This could result in illegal values being programmed in the hw. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11Merge branch 'clps711x/soc' into next/socOlof Johansson6-6/+25
From Alexander Shiyan, this is a series of cleanups of clps711x, movig it closer to multiplatform and cleans up a bunch of old code. * clps711x/soc: ARM: clps711x: Update defconfig ARM: clps711x: Add support for SYSCON driver ARM: clps711x: edb7211: Control LCD backlight via PWM ARM: clps711x: edb7211: Add support for I2C ARM: clps711x: Optimize interrupt handling ARM: clps711x: Add clocksource framework ARM: clps711x: Replace "arch_initcall" in common code with ".init_early" ARM: clps711x: Move specific definitions from hardware.h to boards files ARM: clps711x: p720t: Define PLD registers as GPIOs ARM: clps711x: autcpu12: Move remaining specific definitions to board file ARM: clps711x: autcpu12: Special driver for handling memory is removed ARM: clps711x: autcpu12: Add support for NOR flash ARM: clps711x: autcpu12: Move LCD DPOT definitions to board file ARM: clps711x: Set PLL clock to zero if we work from 13 mHz source ARM: clps711x: Remove NEED_MACH_MEMORY_H dependency ARM: clps711x: Re-add GPIO support GPIO: clps711x: Add DT support GPIO: clps711x: Rewrite driver for using generic GPIO code + Linux 3.10-rc4 Signed-off-by: Olof Johansson <olof@lixom.net>
2013-06-11clk: spear: fix build error for spear3xxArnd Bergmann1-1/+1
This patch is required to be able to disable spear320 support after the spear320_clk_init() prototype changed for the real function but not for the dummy. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-12clk: exynos4: Add additional G2D clocksSachin Kamat1-2/+7
Add G2D clocks for Exynos4x12 SoC and sclk_fimg2d required by G2D IP. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Cc: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-06-11clk: samsung: Fix pll36xx_recalc_rate to handle kdiv properlyDoug Anderson1-2/+3
The KDIV value is often listed as unsigned but it needs to be treated as a 16-bit signed value when using it in calculations. Fix our rate recalculation to do this correctly. Before doing this, I tried setting EPLL on exynos5250 to: rate, m, p, s, k = 80000000, 107, 2, 4, 43691 This rate is exactly from the table in the exynos5250 user manual. I read this back as 80750003 with: cat /sys/kernel/debug/clk/fin_pll/fout_epll/clk_rate After this patch, it reads back as 80000003 Signed-off-by: Doug Anderson <dianders@chromium.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Reviewed-by: Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-10clk: divider: do not propagate rate change request when unnecessaryShawn Guo1-0/+10
If the current rate of parent clock is sufficient to provide child a requested rate with a proper divider setting, the rate change request should not be propagated. Instead, changing the divider setting is good enough to get child clock run at the requested rate. On an imx6q clock configuration illustrated below, ahb --> ipg --> ipg_per 132M 66M 66M calling clk_set_rate(ipg_per, 22M) with the current clk_divider_bestdiv() implementation will result in the rate change up to ahb level like the following, because of the unnecessary/incorrect rate change propagation. ahb --> ipg --> ipg_per 66M 22M 22M Fix the problem by trying to see if the requested rate can be achieved by simply changing the divider value, and in that case return the divider immediately from function clk_divider_bestdiv() as the best one, so that all those unnecessary rate change propagation can be saved. Reported-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-10clk: exynos5250: Add sclk_mpll to the parent list of mout_cpu clockTushar Behera1-1/+1
'mout_mpll' is added the list of parent clocks for 'mout_cpu'. 'mout_mpll' is an alias to the clock 'sclk_mpll'. Hence 'sclk_mpll' should be added to the list of parent clocks. This results in an error when cpufreq driver for EXYNOS5250 tries to set 'mout_mpll' as a parent for 'mout_cpu'. clk_set_parent: clk sclk_mpll can not be parent of clk mout_cpu Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-10clk: exynos5250: Update cpufreq related clocks for EXYNOS5250Tushar Behera1-3/+3
cpufreq driver for EXYNOS5250 is not a platform driver, hence we cannot currently pass the clock names through a device tree node. Instead, we need to make them available through a global alias. cpufreq driver for EXYNOS5250 requires four clocks - 'armclk', 'mout_cpu', 'mout_mpll' and 'mout_apll'. 'armclk' has already been defined with an alias, 'mout_cpu', 'mout_mpll' and 'mout_apll' are now defined with an alias. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-07Merge tag 'zynq-clk-for-3.11' of git://git.xilinx.com/linux-xlnx into next/socOlof Johansson5-379/+772
From Michal Simek: arm: Xilinx Zynq clock changes for v3.11 Change Xilinx Zynq DT clock description which reflects logical abstraction of Zynq's clock tree. - Refactor PLL driver - Use new clock controller driver - Change timer and uart drivers * tag 'zynq-clk-for-3.11' of git://git.xilinx.com/linux-xlnx: clk: zynq: Remove deprecated clock code arm: zynq: Migrate platform to clock controller clk: zynq: Add clock controller driver clk: zynq: Factor out PLL driver Signed-off-by: Olof Johansson <olof@lixom.net>
2013-06-06clk: remove notifier from list before freeing itLai Jiangshan1-0/+1
The @cn is stay in @clk_notifier_list after it is freed, it cause memory corruption. Example, if @clk is registered(first), unregistered(first), registered(second), unregistered(second). The freed @cn will be used when @clk is registered(second), and the bug will be happened when @clk is unregistered(second): [ 517.040000] clk_notif_dbg clk_notif_dbg.1: clk_notifier_unregister() [ 517.040000] Unable to handle kernel paging request at virtual address 00df3008 [ 517.050000] pgd = ed858000 [ 517.050000] [00df3008] *pgd=00000000 [ 517.060000] Internal error: Oops: 5 [#1] PREEMPT SMP ARM [ 517.060000] Modules linked in: clk_notif_dbg(O-) [last unloaded: clk_notif_dbg] [ 517.060000] CPU: 1 PID: 499 Comm: modprobe Tainted: G O 3.10.0-rc3-00119-ga93cb29-dirty #85 [ 517.060000] task: ee1e0180 ti: ee3e6000 task.ti: ee3e6000 [ 517.060000] PC is at srcu_readers_seq_idx+0x48/0x84 [ 517.060000] LR is at srcu_readers_seq_idx+0x60/0x84 [ 517.060000] pc : [<c0052720>] lr : [<c0052738>] psr: 80070013 [ 517.060000] sp : ee3e7d48 ip : 00000000 fp : ee3e7d6c [ 517.060000] r10: 00000000 r9 : ee3e6000 r8 : 00000000 [ 517.060000] r7 : ed84fe4c r6 : c068ec90 r5 : c068e430 r4 : 00000000 [ 517.060000] r3 : 00df3000 r2 : 00000000 r1 : 00000002 r0 : 00000000 [ 517.060000] Flags: Nzcv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user [ 517.060000] Control: 18c5387d Table: 2d85804a DAC: 00000015 [ 517.060000] Process modprobe (pid: 499, stack limit = 0xee3e6238) [ 517.060000] Stack: (0xee3e7d48 to 0xee3e8000) .... [ 517.060000] [<c0052720>] (srcu_readers_seq_idx+0x48/0x84) from [<c0052790>] (try_check_zero+0x34/0xfc) [ 517.060000] [<c0052790>] (try_check_zero+0x34/0xfc) from [<c00528b0>] (srcu_advance_batches+0x58/0x114) [ 517.060000] [<c00528b0>] (srcu_advance_batches+0x58/0x114) from [<c0052c30>] (__synchronize_srcu+0x114/0x1ac) [ 517.060000] [<c0052c30>] (__synchronize_srcu+0x114/0x1ac) from [<c0052d14>] (synchronize_srcu+0x2c/0x34) [ 517.060000] [<c0052d14>] (synchronize_srcu+0x2c/0x34) from [<c0053a08>] (srcu_notifier_chain_unregister+0x68/0x74) [ 517.060000] [<c0053a08>] (srcu_notifier_chain_unregister+0x68/0x74) from [<c0375a78>] (clk_notifier_unregister+0x7c/0xc0) [ 517.060000] [<c0375a78>] (clk_notifier_unregister+0x7c/0xc0) from [<bf008034>] (clk_notif_dbg_remove+0x34/0x9c [clk_notif_dbg]) [ 517.060000] [<bf008034>] (clk_notif_dbg_remove+0x34/0x9c [clk_notif_dbg]) from [<c02bb974>] (platform_drv_remove+0x24/0x28) [ 517.060000] [<c02bb974>] (platform_drv_remove+0x24/0x28) from [<c02b9bf8>] (__device_release_driver+0x8c/0xd4) [ 517.060000] [<c02b9bf8>] (__device_release_driver+0x8c/0xd4) from [<c02ba680>] (driver_detach+0x9c/0xc4) [ 517.060000] [<c02ba680>] (driver_detach+0x9c/0xc4) from [<c02b99c4>] (bus_remove_driver+0xcc/0xfc) [ 517.060000] [<c02b99c4>] (bus_remove_driver+0xcc/0xfc) from [<c02bace4>] (driver_unregister+0x54/0x78) [ 517.060000] [<c02bace4>] (driver_unregister+0x54/0x78) from [<c02bbb44>] (platform_driver_unregister+0x1c/0x20) [ 517.060000] [<c02bbb44>] (platform_driver_unregister+0x1c/0x20) from [<bf0081f8>] (clk_notif_dbg_driver_exit+0x14/0x1c [clk_notif_dbg]) [ 517.060000] [<bf0081f8>] (clk_notif_dbg_driver_exit+0x14/0x1c [clk_notif_dbg]) from [<c00835e4>] (SyS_delete_module+0x200/0x28c) [ 517.060000] [<c00835e4>] (SyS_delete_module+0x200/0x28c) from [<c000edc0>] (ret_fast_syscall+0x0/0x48) [ 517.060000] Code: e5973004 e7911102 e0833001 e2881002 (e7933101) Cc: stable@kernel.org Reported-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Lai Jiangshan <laijs@cn.fujitsu.com> Tested-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: shortened $SUBJECT]
2013-06-06clk: ux500: Clocks definition for u8540Philippe Begnic1-1/+559
First clocks definition version of PRCMU and PRCC clocks for u8540 platform Signed-off-by: Philippe Begnic <philippe.begnic@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-06clk: ux500: Pass clock base adresses in initcall for u8540 and u9540Philippe Begnic2-4/+4
Align on u8500 version, pass clock base address in clk_init functions for u8540 and u9540. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Philippe Begnic <philippe.begnic@st.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-04clk: tegra114: Fix msenc clock registerMikko Perttunen1-1/+1
The msenc clock's register was set to the usb3 clock's register. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-31Merge tag 'seb_clk-3.11' of git://git.infradead.org/users/jcooper/linux into next/socOlof Johansson13-1001/+1064
From Jason Cooper: mvebu clock restructuring for v3.11 - clk: mvebu - reorganize by SoC to remove built up #ifdefs - add clk flags per clock gate * tag 'seb_clk-3.11' of git://git.infradead.org/users/jcooper/linux: clk: mvebu: disintegrate obsolete file ARM: mvebu: move DT boards to SoC-centric clock init ARM: kirkwood: move DT boards to SoC-centric clock init ARM: dove: move DT boards to SoC-centric clock init clk: mvebu: add Armada XP SoC-centric clock init clk: mvebu: add Armada 370 SoC-centric clock init clk: mvebu: add Kirkwood SoC-centric clock init clk: mvebu: add Dove SoC-centric clock init clk: mvebu: add common clock functions for core clk and clk gating clk: mvebu: introduce per-clock-gate flags
2013-05-31Merge tag 'pcie-3.11-2' of git://git.infradead.org/users/jcooper/linux into next/socOlof Johansson1-6/+12
PCI-e driver for mvebu. * tag 'pcie-3.11-2' of git://git.infradead.org/users/jcooper/linux: pci: mvebu: fix return value check in mvebu_pcie_probe() arm: mvebu: PCIe support is now available on mvebu pci: PCIe driver for Marvell Armada 370/XP systems clk: mvebu: add more PCIe clocks for Armada XP clk: mvebu: create parent-child relation for PCIe clocks on Armada 370 of/pci: Add of_pci_parse_bus_range() function of/pci: Add of_pci_get_devfn() function of/pci: Provide support for parsing PCI DT ranges property Signed-off-by: Olof Johansson <olof@lixom.net>
2013-05-31clk: tegra: Use common of_clk_init functionPrashant Gaikwad5-33/+6
Use common of_clk_init() function for clocks initialization. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Thierry Reding <thierry.reding@gmail.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-31clk: tegra114: correctly output clk_32kAlexandre Courbot1-0/+3
Tegra has a blink timer register that allows to modulate the clk_32k clock before outputting it. Since clk_32k is presented to the kernel as a fixed clock, make sure this register does not tamper with the clock frequency and that clk_32k is outputted as-is, similarly to what is done on t20 and t30. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-31clk: tegra: fix clk_out parents listPrashant Gaikwad2-4/+4
Number of parents for clk_out_2 and clk_out_3 was incorrectly set to clk_out1_parents. Even though it did not break anything since the size was same better to fix. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Thierry Reding <thierry.reding@gmail.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-31clk: Add TI-Nspire clock driversDaniel Tang2-0/+154
This patch adds a basic clock driver for the TI-Nspire calculator series. Changes from v1: * Removed filename in header comment * Removed unnecessary #undef EXTRACT statement Signed-off-by: Daniel Tang <dt.tangr@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: fixed $SUBJECT and changelog max width]
2013-05-30clk: mxs: Include clk mxs header fileFabio Estevam1-0/+1
Fix the following sparse warnings: drivers/clk/mxs/clk-imx28.c:72:5: warning: symbol 'mxs_saif_clkmux_select' was not declared. Should it be static? drivers/clk/mxs/clk-imx28.c:156:12: warning: symbol 'mx28_clocks_init' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: fixed $SUBJECT line]
2013-05-30clk: use platform_{get,set}_drvdata()Jingoo Han2-3/+3
Use the wrapper functions for getting and setting the driver data using platform_device instead of using dev_{get,set}_drvdata() with &pdev->dev, so we can directly pass a struct platform_device. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-30clk: mpc85xx: Update the compatible stringTang Yuantian1-1/+1
The compatible string of clock is changed from *-2 to *-2.0 on chassis 2. So updated it accordingly. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: improved $SUBJECT line]
2013-05-29clk: vt8500: Fix unbalanced spinlock in vt8500_dclk_set_rate()Tony Prisk1-1/+1
With the addition of a DVO clock, a bug is now evident in the vt8500 clock code: [ 0.290000] WARNING: at init/main.c:698 do_one_initcall+0x158/0x18c() [ 0.300000] initcall wm8505fb_driver_init+0x0/0xc returned with disabled int This is caused by an unbalanced spinlock in vt8500_dclk_set_rate(). Replace the second call to spin_lock_irqsave() with spin_unlock_irqrestore(). Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-29clk: sunxi: "cpu_data" is defined in header files of some architecturesGiacomo A. Catenazzi1-2/+2
In some architectures, the #define cpu_data is not a "macro-function", so the compiler will substitute the identifier with probably something wrong. Signed-off-by: Giacomo A. Catenazzi <cate@cateee.net> Signed-off-by: Emilio López <emilio@elopez.com.ar> [emilio@elopez.com.ar: use cpu_mux_data instead of this_cpu_data] Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-29clk: exynos5250: Add sclk_mpll to the parent list of mout_cpu clockTushar Behera1-1/+1
'mout_mpll' is added the list of parent clocks for 'mout_cpu'. 'mout_mpll' is an alias to the clock 'sclk_mpll'. Hence 'sclk_mpll' should be added to the list of parent clocks. This results in an error when cpufreq driver for EXYNOS5250 tries to set 'mout_mpll' as a parent for 'mout_cpu'. clk_set_parent: clk sclk_mpll can not be parent of clk mout_cpu Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-29clk: exynos5250: Update cpufreq related clocks for EXYNOS5250Tushar Behera1-3/+3
cpufreq driver for EXYNOS5250 is not a platform driver, hence we cannot currently pass the clock names through a device tree node. Instead, we need to make them available through a global alias. cpufreq driver for EXYNOS5250 requires four clocks - 'armclk', 'mout_cpu', 'mout_mpll' and 'mout_apll'. 'armclk' has already been defined with an alias, 'mout_cpu', 'mout_mpll' and 'mout_apll' are now defined with an alias. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-29clk: si5351: Set initial clkout rate when defined in platform data.Marek Belisko1-0/+10
clock-frequency property from platform data was read but never used. Apply defined rate when clock is registered. Signed-off-by: Marek Belisko <marek.belisko@streamunlimited.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: add missing changelog] Cc: stable@kernel.org Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-29clk: si5351: Fix clkout rate computation.Marek Belisko1-1/+1
Rate was incorrectly computed because we read from wrong divider register. Signed-off-by: Marek Belisko <marek.belisko@streamunlimited.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> Cc: stable@kernel.org
2013-05-29clk: vt8500: Remove unnecessary divisor adjustment in vtwm_dclk_set_rate()Tony Prisk1-4/+0
The divisor adjustment code to ensure that a divisor is not rounded down, thereby giving a rate higher than requested, is unnecessary and in some instances results in the actual rate being much lower than requested due to rounding errors. The test is already performed in vtwm_dclk_round_rate(), which is always called when clk_set_rate is called. Due to rounding errors in the line: divisor = parent_rate / rate (clk-vt8500.c:160) we will sometimes end up adjusting the divisor twice - first in round_rate and then again in set_rate. This patch removes the test/adjustment in vtwm_dclk_set_rate. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-29clk: vt8500: Add support for clocks on the WM8850 SoCsTony Prisk1-0/+71
The WM8850 has a different PLL clock to the previous versions. This patch adds support for the WM8850-style PLL clocks. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-29clk: mvebu: disintegrate obsolete fileSebastian Hesselbarth7-995/+2
Switch from function-centric to soc-centric clock drivers now makes a bunch of files obsolete. This deletes all files and Kconfig options that are not required anymore. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-29clk: mvebu: add Armada XP SoC-centric clock initSebastian Hesselbarth3-0/+216
This is moving core clock and clock gating init for Armada XP to its own file and adds a Kconfig option. Also init functions are added and declared so they get called on of_clk_init. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-29clk: mvebu: add Armada 370 SoC-centric clock initSebastian Hesselbarth3-0/+182
This is moving core clock and clock gating init for Armada 370 to its own file and adds a Kconfig option. Also init functions are added and declared so they get called on of_clk_init. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-29clk: mvebu: add Kirkwood SoC-centric clock initSebastian Hesselbarth3-0/+252
This is moving core clock and clock gating init for Kirkwood to its own file and adds a Kconfig option. Also init functions are added and declared so they get called on of_clk_init. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-29clk: mvebu: add Dove SoC-centric clock initSebastian Hesselbarth3-0/+200
This is moving core clock and clock gating init for Dove to its own file and adds a Kconfig option. Also init functions are added and declared so they get called on of_clk_init. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-29clk: mvebu: add common clock functions for core clk and clk gatingSebastian Hesselbarth4-0/+215
Based on the current common functions for core clocks and clock gating control, new common functions are joined in a single file. Given the opportunity, names of functions and structs are unified, and also a Kconfig entry is added. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-29clk: mvebu: introduce per-clock-gate flagsSebastian Hesselbarth1-87/+78
Clock gates found on MVEBU SoCs get registered by a common function. To allow specific SoCs to provide tweaks introduce flags to the clock gate descriptor instead of filling up the common function SoC specific tweaks. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-29clk: samsung: Add CLK_IGNORE_UNUSED flag for the sysreg clocksSylwester Nawrocki1-2/+4
Currently no driver *) handles the sysreg clock, with an assumption that this clock is always left in its default state (enabled). Before commit 6e6aac7590f902d14d90bace3fd499 ARM: EXYNOS: Migrate clock support to common clock framework the sysreg clock was not even defined and hence wasn't handled explicitly in the kernel. To restore the previous behaviour disable masking the sysreg clock off in the clock core by default. *) Except the Exynos4x12 FIMC-IS driver, which will be modified to not touch the sysreg clock. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-29clk: ux500: clk-sysctrl: handle clocks with no parentsFabio Baltieri1-1/+7
Fix clk_reg_sysctrl() to set main clock registers of new struct clk_sysctrl even if the registered clock has no parents. This fixes an issue where "ulpclk" was registered with all clk->reg_* fields uninitialized, causing a -EINVAL error from clk_prepare(). Signed-off-by: Fabio Baltieri <fabio.baltieri@linaro.org> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-29clk: ux500: Provide device enumeration number suffix for SMSC911xLee Jones1-1/+1
First Ethernet device has a ".0" appended onto the device name. It appears that we need this in order to obtain the correct clock. Without this fix Ethernet does not function on Ux500 devices, which is a regression. Cc: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: improved changelog]
2013-05-29clk: Disable unused clocks after deferred probing is doneSaravana Kannan1-1/+1
With deferred probing, late_initcall() is too soon to declare a clock as unused. Wait for deferred probing to finish before declaring a clock as unused. Since deferred probing is done in late_initcall(), do the unused check to late_initcall_sync. Signed-off-by: Saravana Kannan <skannan@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-28clk: wm831x: Fix wm831x_clkout_get_parentAxel Lin1-3/+3
Current code looks strange because calling wm831x_clkout_set_parent() with 0 as parent parameter, wm831x_clkout_get_parent() will return 1. According to the datasheet: R16528 (4090h) Clock Control1 BIT 0: CLKOUT output source select 0 = FLL output 1 = 32.768kHz oscillator Thus fix the entry order in wm831x_clkout_parents[] to make it has the same meaning as the datasheet and make the return value of wm831x_clkout_get_parent() consistent with the parent pass to wm831x_clkout_set_parent(). Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-28clk: wm831x: Fix update wrong register for enable/disable FLLAxel Lin1-3/+3
According to the datasheet, FLL Enable is controlled by R16530 (4092h) FLL Control1 BIT 0: FLL Enable 0 = Disable 1 = Enable Thus the code should update WM831X_FLL_CONTROL_1 register rather than WM831X_FLL_CONTROL_2 register. Also fixes a trivial typo in dev_crit message. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-28clk: si5351: Allow to build without CONFIG_OFSebastian Hesselbarth1-1/+0
With of_clk_provider stubs for CONFIG_OF not set, we can now also enable clk-si5351 on those architectures. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-28clk: Fix race condition between clk_set_parent and clk_enable()Saravana Kannan1-45/+44
Without this patch, the following race condition is possible. * clk-A has two parents - clk-X and clk-Y. * All three are disabled and clk-X is current parent. * Thread A: clk_set_parent(clk-A, clk-Y). * Thread A: <snip execution flow> * Thread A: Grabs enable lock. * Thread A: Sees enable count of clk-A is 0, so doesn't enable clk-Y. * Thread A: Updates clk-A SW parent to clk-Y * Thread A: Releases enable lock. * Thread B: clk_enable(clk-A). * Thread B: clk_enable() enables clk-Y, then enabled clk-A and returns. clk-A is now enabled in software, but not clocking in hardware since the hardware parent is still clk-X. The only way to avoid race conditions between clk_set_parent() and clk_enable/disable() is to ensure that clk_enable/disable() calls don't require changes to hardware enable state between changes to software clock topology and hardware clock topology. The options to achieve the above are: 1. Grab the enable lock before changing software/hardware topology and release it afterwards. 2. Keep the clock enabled for the duration of software/hardware topology change so that any additional enable/disable calls don't try to change the hardware state. Once the topology change is complete, the clock can be put back in its original enable state. Option (1) is not an acceptable solution since the set_parent() ops might need to sleep. Therefore, this patch implements option (2). This patch doesn't violate any API semantics. clk_disable() doesn't guarantee that the clock is actually disabled. So, no clients of a clock can assume that a clock is disabled after their last call to clk_disable(). So, enabling the clock during a parent change is not a violation of any API semantics. This also has the nice side effect of simplifying the error handling code. Signed-off-by: Saravana Kannan <skannan@codeaurora.org> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: fixed up whitespace issue]
2013-05-28clk: si5351: declare all device IDs for module loadingJean-Francois Moine1-1/+4
When the si5351 driver is a kernel module, it is loaded into memory from its i2c device IDs, but not from its DT compatible properties. This patch declares the i2c device IDs of all chip variants. Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-28clk: sun5i: Add compatibles for Allwinner A13Maxime Ripard1-8/+23
The A13 has a lot less clocks than the one found in the Allwinner A10. Add these stripped down clocks to the clock driver and in the documentation. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-05-28clk: ux500: abx500-clk: rename ux500 audio codec aliasesFabio Baltieri1-4/+4
Change soc-audio related clk_register_clkdev() device names to reflect the ones actually used in current snd-soc-mop500 and ab8500-codec drivers. Cc: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Fabio Baltieri <fabio.baltieri@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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