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2018-07-09clk: meson: add clk-phase clock driverJerome Brunet3-0/+72
2018-07-09clk: meson: clean-up meson clock configurationJerome Brunet1-9/+5
2018-07-09clk: meson: remove obsolete register accessJerome Brunet2-69/+4
2018-07-08clk: tegra: emc: Avoid out-of-bounds bugDmitry Osipenko1-1/+1
2018-07-08clk: tegra: Mark Memory Controller clock as criticalDmitry Osipenko1-2/+3
2018-07-08clk: tegra: Make vde a child of pll_c3Thierry Reding1-1/+1
2018-07-08clk: tegra: Make vic03 a child of pll_c3Thierry Reding1-0/+1
2018-07-08clk: tegra: bpmp: Don't crash when a clock fails to registerMikko Perttunen1-3/+9
2018-07-08clk: rockchip: fix clk_i2sout parent selection bits on rk3399Alberto Panizzo1-1/+1
2018-07-06clk: qcom: Move frequency table macro to common fileTaniya Das14-26/+2
2018-07-06clk: imx51-imx53: Include sizes.h to silence compile errorsStephen Boyd1-0/+1
2018-07-06clk: imx51-imx53: Annotate critical clocks as CLK_IS_CRITICALFabio Estevam1-29/+14
2018-07-06clk: imx6sll: add GPIO LPCGsAnson Huang1-0/+6
2018-07-06clk: aspeed: Fix SDCLK nameLei YU1-1/+1
2018-07-06clk: pxa: export 32kHz PLLRobert Jarzmik3-8/+12
2018-07-06clk: aspeed: Mark bclk (PCIe) and dclk (VGA) as criticalJoel Stanley1-2/+2
2018-07-06clk: Add driver for MAX9485Daniel Mack3-0/+394
2018-07-06clk: ingenic: Add missing flag for UDC clockPaul Cercueil1-1/+1
2018-07-06clk: ingenic: Fix incorrect data for the i2s clockPaul Cercueil1-1/+1
2018-07-06clk/mmcc-msm8996: Make mmagic_bimc_gdsc ALWAYS_ONVivek Gautam1-0/+1
2018-07-06clk: at91: add I2S clock mux driverCodrin Ciubotariu2-0/+117
2018-07-06clk: socfpga: stratix10: fix the sdmmc_free_clk muxDinh Nguyen1-1/+1
2018-07-06clk: socfpga: stratix10: fix the parents of mpu_free_clkDinh Nguyen1-1/+6
2018-07-06Merge tag 'meson-clk-fixes-4.18-1' of https://github.com/BayLibre/clk-meson into clk-fixesStephen Boyd2-1/+2
2018-07-06clk: aspeed: Treat a gate in reset as disabledBenjamin Herrenschmidt1-0/+13
2018-07-06clk: Really show symbolic clock flags in debugfsGeert Uytterhoeven1-2/+1
2018-07-06clk: qcom: gcc-msm8996: Disable halt check on UFS tx clockVinod Koul1-0/+1
2018-07-06clk: rockchip: add clock controller for px30Elaine Zhang3-1/+1080
2018-07-06clk: rockchip: add support for half dividerElaine Zhang4-0/+323
2018-07-03clk: qcom: Enable clocks which needs to be always on for SDM845Amit Nischal1-4/+39
2018-06-29clk: imx6: fix video_27m parent for IMX6QDL_CLK_CKO1_SELPhilipp Puschmann1-1/+1
2018-06-29clk: imx6ul: remove clks_init_on arrayAnson Huang1-17/+6
2018-06-29clk: imx6ul: add GPIO clock gatesAnson Huang1-0/+5
2018-06-29clk: imx6sx: remove clks_init_on arrayAnson Huang1-26/+14
2018-06-29clk: imx6sl: remove clks_init_on arrayAnson Huang1-12/+0
2018-06-29clk: imx6q: remove clks_init_on arrayAnson Huang1-12/+2
2018-06-29clk-si514, clk-si544: Implement prepare/unprepare/is_prepared operationsMike Looijmans2-2/+74
2018-06-27clk: sunxi-ng: add A64 compatible stringIcenowy Zheng1-7/+4
2018-06-27Merge tag 'clk-davinci-fixes-4.18' of https://github.com/dlech/linux into clk-fixesStephen Boyd2-2/+2
2018-06-27clk: sunxi-ng: r40: Export video PLLsJernej Skrabec1-2/+6
2018-06-27clk: sunxi-ng: r40: Allow setting parent rate to display related clocksJernej Skrabec1-4/+8
2018-06-27clk: sunxi-ng: r40: Add minimal rate for video PLLsJernej Skrabec1-22/+24
2018-06-25clk: davinci: fix a typo (which leads to build failures)Bartosz Golaszewski1-1/+1
2018-06-25clk: davinci: cfgchip: testing the wrong variableDan Carpenter1-1/+1
2018-06-25clk: renesas: Renesas R9A06G032 clock driverMichel Pollet3-0/+900
2018-06-21clk: sunxi-ng: replace lib-y with obj-yMasahiro Yamada2-25/+16
2018-06-21clk: meson: audio-divider is one basedJerome Brunet1-1/+1
2018-06-19clk: add duty cycle supportJerome Brunet1-5/+194
2018-06-19clk: fix CLK_SET_RATE_GATE with clock rate protectionJerome Brunet1-3/+13
2018-06-19clk: qcom: drop CLK_SET_RATE_GATE from sdc clocksJerome Brunet4-15/+0