linux-dev - Linux kernel development work

Age	Commit message (Expand)	Author	Files	Lines
2016-05-06	clk: mediatek: make dpi0_sel propagate rate changes	Philipp Zabel	2	-3/+18
2016-05-03	clk: imx7d: fix ahb clock mux 1	Stefan Agner	1	-1/+1
2016-05-02	clk: fix comment of devm_clk_hw_register()	Masahiro Yamada	1	-1/+1
2016-05-02	Merge tag 'clk-renesas-for-v4.7-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next	Stephen Boyd	3	-3/+15
2016-05-02	Merge tag 'sunxi-clocks-for-4.7' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next	Stephen Boyd	6	-13/+470
2016-05-02	Merge tag 'tegra-for-4.7-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next	Stephen Boyd	19	-114/+427
2016-05-02	Merge tag 'v4.7-rockchip-clk3' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next	Stephen Boyd	2	-169/+179
2016-04-28	clk: tegra: dfll: Reformat CVB frequency table	Thierry Reding	1	-25/+25
2016-04-28	clk: tegra: dfll: Properly clean up on failure and removal	Thierry Reding	4	-4/+48
2016-04-28	clk: tegra: dfll: Make code more comprehensible	Thierry Reding	3	-41/+37
2016-04-28	clk: tegra: dfll: Reference CVB table instead of copying data	Thierry Reding	3	-27/+17
2016-04-28	clk: tegra: dfll: Update kerneldoc	Thierry Reding	1	-5/+5
2016-04-28	clk: tegra: Fix PLL_U post divider and initial rate on Tegra30	Lucas Stach	1	-5/+6
2016-04-28	clk: tegra: Initialize PLL_C to sane rate on Tegra30	Lucas Stach	1	-0/+1
2016-04-28	clk: tegra: Fix pllre Tegra210 and add pll_re_out1	Rhyland Klein	3	-2/+66
2016-04-28	clk: tegra: Add sor_safe clock	Thierry Reding	2	-0/+5
2016-04-28	clk: tegra: dpaux and dpaux1 are fixed factor clocks	Thierry Reding	3	-2/+12
2016-04-28	clk: tegra: Add dpaux1 clock	Thierry Reding	3	-0/+3
2016-04-28	clk: tegra: Use correct parent for dpaux clock	Thierry Reding	1	-1/+1
2016-04-28	clk: tegra: Add fixed factor peripheral clock type	Thierry Reding	3	-0/+138
2016-04-28	clk: tegra: Special-case mipi-cal parent on Tegra114	Thierry Reding	2	-2/+6
2016-04-28	clk: tegra: Remove trailing blank line	Thierry Reding	1	-1/+0
2016-04-28	clk: tegra: Constify peripheral clock registers	Thierry Reding	5	-7/+7
2016-04-28	clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs	Andrew Bresticker	1	-0/+58
2016-04-28	treewide: Fix typos in printk	Masanari Iida	1	-1/+1
2016-04-28	clk: renesas: cpg-mssr: Use always-on governor for Clock Domain	Geert Uytterhoeven	1	-1/+1
2016-04-28	clk: renesas: cpg-mssr: Postpone call to pm_genpd_init()	Geert Uytterhoeven	1	-1/+1
2016-04-28	clk: renesas: mstp: Use always-on governor for Clock Domain	Geert Uytterhoeven	1	-1/+1
2016-04-28	clk: renesas: mstp: Postpone call to pm_genpd_init()	Geert Uytterhoeven	1	-2/+1
2016-04-27	clk: imx: return correct frequency for Ethernet PLL	Stefan Agner	1	-1/+8
2016-04-26	Merge tag 'renesas-rcar-sysc2-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers	Arnd Bergmann	7	-47/+90
2016-04-26	clk: renesas: r8a7795: Add VIN clocks	Niklas Söderlund	1	-0/+8
2016-04-26	clk: renesas: r8a7795: Add CSI2 clocks	Niklas Söderlund	1	-0/+5
2016-04-25	clk: rockchip: fix the rk3399 cifout clock	Xing Zheng	1	-5/+6
2016-04-25	clk: rockchip: drop unnecessary CLK_IGNORE_UNUSED flags from rk3399	Xing Zheng	1	-157/+157
2016-04-25	clk: rockchip: add some frequencies on the rk3399 PLL table	Xing Zheng	1	-1/+10
2016-04-25	clk: rockchip: assign more necessary rk3399 clock ids	Xing Zheng	1	-6/+6
2016-04-25	clk: rockchip: fix the gate bit for i2c4 and i2c8 on rk3399	Xing Zheng	1	-2/+2
2016-04-25	clk: sunxi: Let divs clocks read the base factor clock name from devicetree	Jens Kuske	1	-11/+30
2016-04-25	clk: rockchip: fix of spelling mistake on unsuccessful in pll clock type	Colin Ian King	1	-2/+2
2016-04-24	Merge tag 'omap-for-v4.7/dt-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt	Arnd Bergmann	1	-1/+1
2016-04-24	Merge tag 'samsung-dt-exynos3250-artik5-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt	Arnd Bergmann	1	-0/+15
2016-04-22	clk: sunxi: Add TCON channel1 clock	Maxime Ripard	2	-0/+301
2016-04-22	clk: sunxi: Add PLL3 clock	Maxime Ripard	2	-0/+99
2016-04-22	clk: sunxi: Use resource_size	Vaishali Thakkar	1	-1/+1
2016-04-22	clk: sunxi: Add sun6i/8i display support	Jean-Francois Moine	1	-0/+38
2016-04-22	clk: sunxi: mod1 clock should modify it's parent	Andrea Venturi	1	-1/+1
2016-04-21	Merge branch 'clk-hw-register' (early part) into clk-next	Stephen Boyd	10	-87/+573
2016-04-21	Merge branch 'clk-composite-unregister' into clk-next	Stephen Boyd	1	-0/+15
2016-04-21	clk: composite: Add unregister function	Maxime Ripard	1	-0/+15