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2021-06-02clk: qcom: dispcc-sm8250: Add EDP clocksBjorn Andersson1-2/+184
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210511041719.591969-2-bjorn.andersson@linaro.org Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-02clk: qcom: dispcc-sm8250: Add sc8180x supportBjorn Andersson1-1/+3
The display clock controller in SC8180x is reused from SM8150, so add the necessary compatible and wire up the driver to enable this. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210511041719.591969-1-bjorn.andersson@linaro.org Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-02clk: qcom: smd-rpm: De-duplicate identical entriesKonrad Dybcio1-405/+247
It makes negative sense to keep repeating the same definitions over and over and over and over again, just with changed names.. De-duplicate to make for a drastically smaller file size. This makes the object file size 55% smaller according to bloat-o-meter: Total: Before=70713, After=31353, chg -55.66% Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210524225456.398817-2-konrad.dybcio@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-02clk: qcom: smd-rpm: Switch to parent_dataKonrad Dybcio1-4/+16
Switch to parent_data and with that fix the longstanding issue where if there wasn't a clock precisely named "xo_board", rpmcc would not play along well. This started to show lately when "xo_board" was being changed to "xo-board" so as to align with DTS naming spec. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210524225456.398817-1-konrad.dybcio@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-02clk: qcom: Add MDM9607 GCC driverKonrad Dybcio3-0/+1663
Add Global Clock Controller (GCC) support for MDM9607 SoC. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210313020310.386152-2-konrad.dybcio@somainline.org [sboyd@kernel.org: Drop clk.h include] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-01clk: analogbits: fix doc warning in wrpll-cln28hpc.cYang Yingliang1-1/+1
Fix the following make W=1 warning: drivers/clk/analogbits/wrpll-cln28hpc.c:227: warning: expecting prototype for wrpll_configure(). Prototype was for wrpll_configure_for_rate() instead Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20210601114154.3163327-1-yangyingliang@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-01clk: sifive: Fix kernel-docYang Li1-1/+1
Fix function name in sifive-prci.c kernel-doc comment to remove a warning. drivers/clk/sifive/sifive-prci.c:573: warning: expecting prototype for sifive_prci_init(). Prototype was for sifive_prci_probe() instead Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Link: https://lore.kernel.org/r/1621851730-32287-1-git-send-email-yang.lee@linux.alibaba.com Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-01clk: versatile: remove dependency on ARCH_*Peter Collingbourne1-2/+0
It is now possible to build a modular kernel for vexpress by not setting CONFIG_ARCH_VEXPRESS=y and instead setting =m on the drivers that it normally implies. This is with the exception of CLK_VEXPRESS_OSC which is currently hidden behind a dependency on one of several ARCH_* variables. Remove that dependency so that CLK_VEXPRESS_OSC may be enabled without it. Signed-off-by: Peter Collingbourne <pcc@google.com> Link: https://linux-review.googlesource.com/id/I435a21e2e5f6187db54f4ef2079b60028ab2ea69 Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20210520161702.3746174-1-lee.jones@linaro.org Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-01clk: qcom: cleanup some dev_err_probe() callsDan Carpenter1-2/+4
The dev_err_probe() function prints an error message if the error code is not -EPROBE_DEFER. If we know the error code in is -ENODEV then there is no reason to check. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/YJotlJBJ1CVAgvMT@mwanda Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-01clk: qcom: Simplify usage of dev_err_probe()Uwe Kleine-König1-14/+8
dev_err_probe() returns the error code passed as second parameter. Also if the error code is -EPROBE_DEFER dev_err_probe() is silent, so there is no need to check for this value before calling dev_err_probe(). Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org> Link: https://lore.kernel.org/r/20210427164522.2886825-1-uwe@kleine-koenig.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-05-31clk: tegra: Don't deassert reset on enabling clocksDmitry Osipenko3-13/+1
The Tegra clock driver contains legacy code which deasserts hardware reset when peripheral clocks are enabled. This behaviour comes from a pre-CCF era of the Tegra drivers. This is unacceptable for modern kernel drivers which use generic CCF and reset-control APIs because it breaks assumptions of the drivers about clk/reset sequences and about reset-propagation delays. Hence remove the awkward legacy behaviour from the clk driver. In particular PMC driver assumes that hardware blocks remains in reset while power domain is turning on, but the clk driver deasserts the reset before power clamp is removed, hence breaking the driver's assumption. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-05-31clk: tegra: Mark external clocks as not having reset controlDmitry Osipenko1-3/+3
The external clocks don't have reset bits as they don't belong to any specific hardware unit. Mark them as not having reset control for consistency. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-05-31clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttlingDmitry Osipenko2-3/+15
Check whether thermal DIV2 throttle is active in order to report the CPU frequency properly. This very useful for userspace tools like cpufreq-info which show actual frequency asserted from hardware. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-05-31clk: tegra: Don't allow zero clock rate for PLLsDmitry Osipenko1-0/+3
Zero clock rate doesn't make sense for PLLs and tegra-clk driver enters into infinite loop on trying to calculate PLL parameters for zero rate. Make code to error out if requested rate is zero. Originally this trouble was found by Robert Yang while he was trying to bring up upstream kernel on Samsung Galaxy Tab, which happened due to a bug in Tegra DRM driver that erroneously sets PLL rate to zero. This issues came over again recently during of kernel bring up on ASUS TF700T. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-05-31clk: tegra: Halve SCLK rate on Tegra20Dmitry Osipenko1-3/+3
Higher SCLK rates on Tegra20 require high core voltage. The higher clock rate may have a positive performance effect only for AHB DMA transfers and AVP CPU, but both aren't used by upstream kernel at all. Halve SCLK rate on Tegra20 in order to remove the high core voltage requirement. Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-05-31clk: tegra: Ensure that PLLU configuration is applied properlyDmitry Osipenko1-5/+4
The PLLU (USB) consists of the PLL configuration itself and configuration of the PLLU outputs. The PLLU programming is inconsistent on T30 vs T114, where T114 immediately bails out if PLLU is enabled and T30 re-enables a potentially already enabled PLL (left after bootloader) and then fully reprograms it, which could be unsafe to do. The correct way should be to skip enabling of the PLL if it's already enabled and then apply configuration to the outputs. This patch doesn't fix any known problems, it's a minor improvement. Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-05-31clk: tegra: Fix refcounting of gate clocksDmitry Osipenko2-25/+58
The refcounting of the gate clocks has a bug causing the enable_refcnt to underflow when unused clocks are disabled. This happens because clk provider erroneously bumps the refcount if clock is enabled at a boot time, which it shouldn't be doing, and it does this only for the gate clocks, while peripheral clocks are using the same gate ops and the peripheral clocks are missing the initial bump. Hence the refcount of the peripheral clocks is 0 when unused clocks are disabled and then the counter is decremented further by the gate ops, causing the integer underflow. Fix this problem by removing the erroneous bump and by implementing the disable_unused() callback, which disables the unused gates properly. The visible effect of the bug is such that the unused clocks are never gated if a loaded kernel module grabs the unused clocks and starts to use them. In practice this shouldn't cause any real problems for the drivers and boards supported by the kernel today. Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-05-31clk: tegra30: Use 300MHz for video decoder by defaultDmitry Osipenko1-1/+1
The 600MHz is a too high clock rate for some SoC versions for the video decoder hardware and this may cause stability issues. Use 300MHz for the video decoder by default, which is supported by all hardware versions. Fixes: ed1a2459e20c ("clk: tegra: Add Tegra20/30 EMC clock implementation") Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-05-28clk: rockchip: export ACLK_VCODEC for RK3036Alex Bee1-1/+1
It is required for the series at [1] to let hantro driver aquire the clock and set the rate for RK3036 correctly, but I didn't want to add a patch for yet another subsystem to this series. [1] https://lore.kernel.org/linux-media/20210525152225.154302-1-knaerzche@gmail.com/ Signed-off-by: Alex Bee <knaerzche@gmail.com> Link: https://lore.kernel.org/r/20210528140736.79686-1-knaerzche@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-05-27clk: renesas: r8a77995: Add ZA2 clockKuninori Morimoto1-0/+1
R-Car D3 ZA2 clock is from PLL0D3 or S0, and it can be controlled by ZA2CKCR. It is needed for R-Car Sound, but is not used so far. Using default settings is very enough at this point. This patch adds it by DEF_FIXED(). Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87pmxclrmy.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-05-27clk: renesas: cpg-mssr: Make srstclr[] comment block consistentGeert Uytterhoeven1-1/+3
Make the style of the comment block for the Software Reset Clearing Register offsets consistent with the comment blocks for the other register offsets. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/97dde75fe3ff27b9639c59a43cddbd9d5c405d0c.1620119700.git.geert+renesas@glider.be
2021-05-27clk: renesas: cpg-mssr: Remove unused [RM]MSTPCR() definitionsGeert Uytterhoeven1-6/+0
The Realtime Module Stop Control Register definitions (RMSTPCR(i)) are incorrect for i >= 8 on R-Car Gen2 and Gen3. As these are unused, and not planned to be used, just like the corresponding Modem Module Stop Control Register definitions (MMSTPCR()) on R-Mobile APE6 (they are intended for the software running on the Real-Time and Modem CPU cores), they can just be removed. Reported-by: Hai Nguyen Pham <hai.pham.ud@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/2d8bc4d9806b419ebb06030d2f31b2ea1e59b1d6.1620119700.git.geert+renesas@glider.be
2021-05-25clk: qcom: clk-rcg2: Add support for duty-cycle for RCGTaniya Das1-0/+81
The root clock generators with MND divider has the capability to support change in duty-cycle by updating the 'D'. Add the clock ops which would check all the boundary conditions and enable setting the desired duty-cycle as per the consumer. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1619334502-9880-2-git-send-email-tdas@codeaurora.org [sboyd@kernel.org: Remove _val everywhere] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-05-24clk: sunxi-ng: v3s: fix incorrect postdivider on pll-audioTobias Schramm1-2/+2
Commit 46060be6d840 ("clk: sunxi-ng: v3s: use sigma-delta modulation for audio-pll") changed the audio pll on the Allwinner V3s and V3 SoCs to use sigma-delta modulation. In the process the declaration of fixed postdivider providing "pll-audio" was adjusted to provide the desired clock rates from the now sigma-delta modulated pll. However, while the divider used for calculations by the clock framework was adjusted the actual divider programmed into the hardware in sun8i_v3_v3s_ccu_init was left at "divide by four". This broke the "pll-audio" clock, now only providing quater the expected clock rate. It would in general be desirable to program the postdivider for "pll-audio" to four, such that a broader range of frequencies were available on the pll outputs. But the clock for the integrated codec "ac-dig" does not feature a mux that allows to select from all pll outputs as it is just a simple clock gate connected to "pll-audio". Thus we need to set the postdivider to one to be able to provide the 22.5792MHz and 24.576MHz rates required by the internal sun4i codec. This patches fixes the incorrect clock rate by forcing the postdivider to one in sun8i_v3_v3s_ccu_init. Fixes: 46060be6d840 ("clk: sunxi-ng: v3s: use sigma-delta modulation for audio-pll") Signed-off-by: Tobias Schramm <t.schramm@manjaro.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210513131315.2059451-1-t.schramm@manjaro.org
2021-05-24clk: meson: axg-audio: improve deferral handlingJerome Brunet1-3/+2
Use dev_err_probe() for clock and reset resources to indicate the deferral reason through sysfs when waiting for the resource to come up. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20210520073136.272925-1-jbrunet@baylibre.com
2021-05-24clk: rockchip: fix rk3568 cpll clk gate bitsPeter Geis1-5/+5
The cpll clk gate bits had an ordering issue. This led to the loss of the boot sdmmc controller when the gmac was shut down with: `ip link set eth0 down` as the cpll_100m was shut off instead of the cpll_62p5. cpll_62p5, cpll_50m, cpll_25m were all off by one with cpll_100m misplaced. Fixes: cf911d89c4c5 ("clk: rockchip: add clock controller for rk3568") Signed-off-by: Peter Geis <pgwipeout@gmail.com> Reviewed-by: Elaine Zhang<zhangqing@rock-chips.com> Link: https://lore.kernel.org/r/20210519174149.3691335-1-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-05-20clk: meson: g12a: fix gp0 and hifi rangesJerome Brunet1-1/+1
While some SoC samples are able to lock with a PLL factor of 55, others samples can't. ATM, a minimum of 60 appears to work on all the samples I have tried. Even with 60, it sometimes takes a long time for the PLL to eventually lock. The documentation says that the minimum rate of these PLLs DCO should be 3GHz, a factor of 125. Let's use that to be on the safe side. With factor range changed, the PLL seems to lock quickly (enough) so far. It is still unclear if the range was the only reason for the delay. Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20210429090325.60970-1-jbrunet@baylibre.com
2021-05-19clk: meson: pll: switch to determine_rate for the PLL opsMartin Blumenstingl1-11/+15
This increases the maxmium supported frequency on 32-bit systems from 2^31 (signed long as used by clk_ops.round_rate, maximum value: approx. 2.14GHz) to 2^32 (unsigned long as used by clk_ops.determine_rate, maximum value: approx. 4.29GHz). On Meson8/8b/8m2 the HDMI PLL and it's OD (post-dividers) are capable of running at up to 2.97GHz. So switch the divider implementation in clk-regmap to clk_ops.determine_rate to support these higher frequencies on 32-bit systems. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20210517203724.1006254-4-martin.blumenstingl@googlemail.com
2021-05-11clk: rockchip: Optimize PLL table memory usageElaine Zhang1-11/+18
Before the change: The sizeof rk3568_pll_rates = 2544 Use union: The sizeof rk3568_pll_rates = 1696 In future Soc, more PLL types will be added, and the rockchip_pll_rate_table will add more members, and the space savings will be even more pronounced by using union. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Link: https://lore.kernel.org/r/20210511090726.15146-1-zhangqing@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-05-11clk: renesas: r9a06g032: Switch to .determine_rate()Geert Uytterhoeven1-12/+13
As the .round_rate() callback returns a long clock rate, it cannot return clock rates that do not fit in signed long, but do fit in unsigned long. Hence switch the divider clocks on RZ/N1 from the old .round_rate() callback to the newer .determine_rate() callback, which does not suffer from this limitation. Note that range checking is not yet implemented. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/7a384d02b85cdaac4a0e2b357582c8244b9a6f98.1617282116.git.geert+renesas@glider.be
2021-05-11clk: renesas: div6: Implement range checkingGeert Uytterhoeven1-1/+7
Consider the minimum and maximum clock rates imposed by clock users when calculating the most appropriate clock rate in the .determine_rate() callback. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/35ceb262c71f1b2e9864a39bde9dafd78b2981f4.1617281699.git.geert+renesas@glider.be
2021-05-11clk: renesas: div6: Consider all parents for requested rateGeert Uytterhoeven1-3/+32
Currently the .determine_rate() callback considers only the current parent clock, limiting the range of achievable clock rates on DIV6 clocks with multiple parents, as found on SH/R-Mobile SoCs. Extend the callback to consider all available parent clocks. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/60e639692b462f99e0b6ab868c3675b3d97dbdb0.1617281699.git.geert+renesas@glider.be
2021-05-11clk: renesas: div6: Switch to .determine_rate()Geert Uytterhoeven1-5/+7
As the .round_rate() callback returns a long clock rate, it cannot return clock rates that do not fit in signed long, but do fit in unsigned long. Hence switch the DIV6 clocks on SH/R-Mobile and R-Car SoCs from the old .round_rate() callback to the newer .determine_rate() callback, which does not suffer from this limitation. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/7fd8c45cd8bf5c6d928ca69c8b669be35b93de09.1617281699.git.geert+renesas@glider.be
2021-05-11clk: renesas: div6: Simplify src mask handlingGeert Uytterhoeven1-20/+11
Simplify the handling of the register bits to select the parent clock, by storing a bitmask instead of separate shift and width values. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/5f05a5110d222ce5a113e683fe2aa726f4100b73.1617281699.git.geert+renesas@glider.be
2021-05-11clk: renesas: div6: Use clamp() instead of clamp_t()Geert Uytterhoeven1-1/+1
As "div" is already "unsigned int", adding "U" suffixes to the constants "1" and "64" allows us to replace the call to clamp_t() by a call to clamp(). This removes hidden casts, and thus helps the compiler doing a better job at type-checking. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/2670c1e3c82a245666578cbbd1fb20d37932fd8e.1617281699.git.geert+renesas@glider.be
2021-05-11clk: renesas: rcar-usb2-clock-sel: Fix error handling in .probe()Dinghao Liu1-9/+15
The error handling paths after pm_runtime_get_sync() have no refcount decrement, which leads to refcount leak. Signed-off-by: Dinghao Liu <dinghao.liu@zju.edu.cn> Link: https://lore.kernel.org/r/20210415073338.22287-1-dinghao.liu@zju.edu.cn [geert: Remove now unused variable priv] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-05-11clk: renesas: r8a779a0: Add ISPCS clocksNiklas Söderlund1-0/+4
Add support for the ISPCS clocks on R-Car V3U. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210329223220.1139211-1-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-05-11clk: renesas: rcar-gen3: Add boost support to Z clocksGeert Uytterhoeven1-4/+20
Add support for switching the Z and Z2 clocks between normal and boost modes, by requesting clock rate changes to parent PLLs. Inspired by a patch in the BSP by Takeshi Kihara <takeshi.kihara.df@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20210326120100.1577596-8-geert+renesas@glider.be
2021-05-11clk: renesas: rcar-gen3: Add custom clock for PLLsGeert Uytterhoeven1-19/+128
Currently the PLLs are modeled as fixed factor clocks, based on initial settings. However, enabling CPU boost clock rates requires increasing the PLL clock rates. Add a custom clock driver to model the PLL clocks. This will allow the Z (CPU) clock driver to request changing the PLL clock rate. Based on a patch in the BSP by Takeshi Kihara <takeshi.kihara.df@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20210326120100.1577596-7-geert+renesas@glider.be
2021-05-11clk: renesas: rcar-gen3: Increase Z clock accuracyGeert Uytterhoeven1-2/+2
Improve accuracy in the .determine_rate() callback for Z and Z2 clocks by using rounded divisions. This is similar to the calculation of rates and multipliers in the .recalc_rate() resp. set_rate() callbacks. Sample impact for a few requested clock rates: - R-Car H3: - Z 500 MHz: 468 MHz => 515 MHz - Z2 1000 MHz: 973 MHz => 1011 MHz - R-Car M3-W: - Z 500 MHz: 422 MHz => 516 MHz - Z2 800 MHz: 750 MHz => 788 MHz Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20210326120100.1577596-6-geert+renesas@glider.be
2021-05-11clk: renesas: rcar-gen3: Grammar s/dependent of/dependent on/Geert Uytterhoeven1-1/+1
Fix grammar in comments for cpg_z_clk_set_rate(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20210326120100.1577596-5-geert+renesas@glider.be
2021-05-11clk: renesas: rcar-gen3: Remove superfluous masking in cpg_z_clk_set_rate()Geert Uytterhoeven1-2/+1
Due to the clamping of mult, "(32 - mult) << __ffs(zclk->mask)" can never exceed the mask. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20210326120100.1577596-4-geert+renesas@glider.be
2021-05-11clk: renesas: rcar-gen3: Make cpg_z_clk.mask u32Geert Uytterhoeven1-1/+1
cpg_z_clk.mask contains a mask for a 32-bit register. Hence its size can be reduced from unsigned long to u32. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20210326120100.1577596-3-geert+renesas@glider.be
2021-05-11clk: renesas: rcar-gen3: Update Z clock rate formula in commentsGeert Uytterhoeven1-1/+2
The fixed divider in the calculation of the Z and Z2 clock rates was generalized from a hardcoded value of two to a parameterized value, but the comments were not updated accordingly. Fixes: 20cc05ba04a93f05 ("clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20210326120100.1577596-2-geert+renesas@glider.be
2021-05-11clk: Skip clk provider registration when np is NULLTudor Ambarus1-0/+9
commit 6579c8d97ad7 ("clk: Mark fwnodes when their clock provider is added") revealed that clk/bcm/clk-raspberrypi.c driver calls devm_of_clk_add_hw_provider(), with a NULL dev->of_node, which resulted in a NULL pointer dereference in of_clk_add_hw_provider() when calling fwnode_dev_initialized(). Returning 0 is reducing the if conditions in driver code and is being consistent with the CONFIG_OF=n inline stub that returns 0 when CONFIG_OF is disabled. The downside is that drivers will maybe register clkdev lookups when they don't need to and waste some memory. Fixes: 6579c8d97ad7 ("clk: Mark fwnodes when their clock provider is added") Fixes: 3c9ea42802a1 ("clk: Mark fwnodes when their clock provider is added/removed") Reported-by: Marek Szyprowski <m.szyprowski@samsung.com> Tested-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Saravana Kannan <saravanak@google.com> Reviewed-by: Nicolas Saenz Julienne <nsaenz@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20210426065618.588144-1-tudor.ambarus@microchip.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-05-05Merge tag 'pci-v5.13-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pciLinus Torvalds5-1/+81
Pull pci updates from Bjorn Helgaas: "Enumeration: - Release OF node when pci_scan_device() fails (Dmitry Baryshkov) - Add pci_disable_parity() (Bjorn Helgaas) - Disable Mellanox Tavor parity reporting (Heiner Kallweit) - Disable N2100 r8169 parity reporting (Heiner Kallweit) - Fix RCiEP device to RCEC association (Qiuxu Zhuo) - Convert sysfs "config", "rom", "reset", "label", "index", "acpi_index" to static attributes to help fix races in device enumeration (Krzysztof Wilczyński) - Convert sysfs "vpd" to static attribute (Heiner Kallweit, Krzysztof Wilczyński) - Use sysfs_emit() in "show" functions (Krzysztof Wilczyński) - Remove unused alloc_pci_root_info() return value (Krzysztof Wilczyński) PCI device hotplug: - Fix acpiphp reference count leak (Feilong Lin) Power management: - Fix acpi_pci_set_power_state() debug message (Rafael J. Wysocki) - Fix runtime PM imbalance (Dinghao Liu) Virtualization: - Increase delay after FLR to work around Intel DC P4510 NVMe erratum (Raphael Norwitz) MSI: - Convert rcar, tegra, xilinx to MSI domains (Marc Zyngier) - For rcar, xilinx, use controller address as MSI doorbell (Marc Zyngier) - Remove unused hv msi_controller struct (Marc Zyngier) - Remove unused PCI core msi_controller support (Marc Zyngier) - Remove struct msi_controller altogether (Marc Zyngier) - Remove unused default_teardown_msi_irqs() (Marc Zyngier) - Let host bridges declare their reliance on MSI domains (Marc Zyngier) - Make pci_host_common_probe() declare its reliance on MSI domains (Marc Zyngier) - Advertise mediatek lack of built-in MSI handling (Thomas Gleixner) - Document ways of ending up with NO_MSI (Marc Zyngier) - Refactor HT advertising of NO_MSI flag (Marc Zyngier) VPD: - Remove obsolete Broadcom NIC VPD length-limiting quirk (Heiner Kallweit) - Remove sysfs VPD size checking dead code (Heiner Kallweit) - Convert VPF sysfs file to static attribute (Heiner Kallweit) - Remove unnecessary pci_set_vpd_size() (Heiner Kallweit) - Tone down "missing VPD" message (Heiner Kallweit) Endpoint framework: - Fix NULL pointer dereference when epc_features not implemented (Shradha Todi) - Add missing destroy_workqueue() in endpoint test (Yang Yingliang) Amazon Annapurna Labs PCIe controller driver: - Fix compile testing without CONFIG_PCI_ECAM (Arnd Bergmann) - Fix "no symbols" warnings when compile testing with CONFIG_TRIM_UNUSED_KSYMS (Arnd Bergmann) APM X-Gene PCIe controller driver: - Fix cfg resource mapping regression (Dejin Zheng) Broadcom iProc PCIe controller driver: - Return zero for success of iproc_msi_irq_domain_alloc() (Pali Rohár) Broadcom STB PCIe controller driver: - Add reset_control_rearm() stub for !CONFIG_RESET_CONTROLLER (Jim Quinlan) - Fix use of BCM7216 reset controller (Jim Quinlan) - Use reset/rearm for Broadcom STB pulse reset instead of deassert/assert (Jim Quinlan) - Fix brcm_pcie_probe() error return for unsupported revision (Wei Yongjun) Cavium ThunderX PCIe controller driver: - Fix compile testing (Arnd Bergmann) - Fix "no symbols" warnings when compile testing with CONFIG_TRIM_UNUSED_KSYMS (Arnd Bergmann) Freescale Layerscape PCIe controller driver: - Fix ls_pcie_ep_probe() syntax error (comma for semicolon) (Krzysztof Wilczyński) - Remove layerscape-gen4 dependencies on OF and ARM64, add dependency on ARCH_LAYERSCAPE (Geert Uytterhoeven) HiSilicon HIP PCIe controller driver: - Remove obsolete HiSilicon PCIe DT description (Dongdong Liu) Intel Gateway PCIe controller driver: - Remove unused pcie_app_rd() (Jiapeng Chong) Intel VMD host bridge driver: - Program IRTE with Requester ID of VMD endpoint, not child device (Jon Derrick) - Disable VMD MSI-X remapping when possible so children can use more MSI-X vectors (Jon Derrick) MediaTek PCIe controller driver: - Configure FC and FTS for functions other than 0 (Ryder Lee) - Add YAML schema for MediaTek (Jianjun Wang) - Export pci_pio_to_address() for module use (Jianjun Wang) - Add MediaTek MT8192 PCIe controller driver (Jianjun Wang) - Add MediaTek MT8192 INTx support (Jianjun Wang) - Add MediaTek MT8192 MSI support (Jianjun Wang) - Add MediaTek MT8192 system power management support (Jianjun Wang) - Add missing MODULE_DEVICE_TABLE (Qiheng Lin) Microchip PolarFlare PCIe controller driver: - Make several symbols static (Wei Yongjun) NVIDIA Tegra PCIe controller driver: - Add MCFG quirks for Tegra194 ECAM errata (Vidya Sagar) - Make several symbols const (Rikard Falkeborn) - Fix Kconfig host/endpoint typo (Wesley Sheng) SiFive FU740 PCIe controller driver: - Add pcie_aux clock to prci driver (Greentime Hu) - Use reset-simple in prci driver for PCIe (Greentime Hu) - Add SiFive FU740 PCIe host controller driver and DT binding (Paul Walmsley, Greentime Hu) Synopsys DesignWare PCIe controller driver: - Move MSI Receiver init to dw_pcie_host_init() so it is re-initialized along with the RC in resume (Jisheng Zhang) - Move iATU detection earlier to fix regression (Hou Zhiqiang) TI J721E PCIe driver: - Add DT binding and TI j721e support for refclk to PCIe connector (Kishon Vijay Abraham I) - Add host mode and endpoint mode DT bindings for TI AM64 SoC (Kishon Vijay Abraham I) TI Keystone PCIe controller driver: - Use generic config accessors for TI AM65x (K3) to fix regression (Kishon Vijay Abraham I) Xilinx NWL PCIe controller driver: - Add support for coherent PCIe DMA traffic using CCI (Bharat Kumar Gogada) - Add optional "dma-coherent" DT property (Bharat Kumar Gogada) Miscellaneous: - Fix kernel-doc warnings (Krzysztof Wilczyński) - Remove unused MicroGate SyncLink device IDs (Jiri Slaby) - Remove redundant dev_err() for devm_ioremap_resource() failure (Chen Hui) - Remove redundant initialization (Colin Ian King) - Drop redundant dev_err() for platform_get_irq() errors (Krzysztof Wilczyński)" * tag 'pci-v5.13-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (98 commits) riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC PCI: fu740: Add SiFive FU740 PCIe host controller driver dt-bindings: PCI: Add SiFive FU740 PCIe host controller MAINTAINERS: Add maintainers for SiFive FU740 PCIe driver clk: sifive: Use reset-simple in prci driver for PCIe driver clk: sifive: Add pcie_aux clock in prci driver for PCIe driver PCI: brcmstb: Use reset/rearm instead of deassert/assert ata: ahci_brcm: Fix use of BCM7216 reset controller reset: add missing empty function reset_control_rearm() PCI: Allow VPD access for QLogic ISP2722 PCI/VPD: Add helper pci_get_func0_dev() PCI/VPD: Remove pci_vpd_find_tag() SRDT handling PCI/VPD: Remove pci_vpd_find_tag() 'offset' argument PCI/VPD: Change pci_vpd_init() return type to void PCI/VPD: Make missing VPD message less alarming PCI/VPD: Remove pci_set_vpd_size() x86/PCI: Remove unused alloc_pci_root_info() return value MAINTAINERS: Add Jianjun Wang as MediaTek PCI co-maintainer PCI: mediatek-gen3: Add system PM support PCI: mediatek-gen3: Add MSI support ...
2021-05-04clk: sifive: Use reset-simple in prci driver for PCIe driverGreentime Hu3-0/+19
We use reset-simple in this patch so that pcie driver can use devm_reset_control_get() to get this reset data structure and use reset_control_deassert() to deassert pcie_power_up_rst_n. Link: https://lore.kernel.org/r/20210504105940.100004-3-greentime.hu@sifive.com Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Stephen Boyd <sboyd@kernel.org>
2021-05-04clk: sifive: Add pcie_aux clock in prci driver for PCIe driverGreentime Hu4-1/+62
We add pcie_aux clock in this patch so that pcie driver can use clk_prepare_enable() and clk_disable_unprepare() to enable and disable pcie_aux clock. Link: https://lore.kernel.org/r/20210504105940.100004-2-greentime.hu@sifive.com Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Stephen Boyd <sboyd@kernel.org>
2021-04-28Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linuxLinus Torvalds98-1970/+4056
Pull clk updates from Stephen Boyd: "Here's a collection of largely clk driver updates. The usual suspects are here: i.MX, Qualcomm, Renesas, Allwinner, Samsung, and Rockchip, but it feels pretty light on commits. There's only one real commit to the framework core and that's to consolidate code. Otherwise the diffstat is dominated by many Qualcomm clk driver patches that modernize the driver for the proper way of speciying clk parents. That's shifting data around, which could subtly break things so I'll be on the lookout for fixes. New Drivers: - Proper clk driver for Mediatek MT7621 SoCs - Support for the clock controller on the new Rockchip rk3568 Updates: - Simplify Zynq Kconfig dependencies - Use clk_hw pointers in socfpga driver - Cleanup parent data in qcom clk drivers - Some cleanups for rk3399 modularization - Fix reparenting of i.MX UART clocks by initializing only the ones associated to stdout - Correct the PCIE clocks for i.MX8MP and i.MX8MQ - Make i.MX LPCG and SCU clocks return on registering failure - Kernel doc fixes - Add DAB hardware accelerator clocks on Renesas R-Car E3 and M3-N - Add timer (TMU) clocks on Renesas R-Car H3 ES1.0 - Add Timer (TMU & CMT) and thermal sensor (TSC) clocks on Renesas R-Car V3U - Sigma-delta modulation on Allwinner V3s audio PLL" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (82 commits) MAINTAINERS: add MT7621 CLOCK maintainer staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk' staging: mt7621-dts: make use of new 'mt7621-clk' clk: ralink: add clock driver for mt7621 SoC clk: uniphier: Fix potential infinite loop clk: qcom: rpmh: add support for SDX55 rpmh IPA clock clk: qcom: gcc-sdm845: get rid of the test clock clk: qcom: convert SDM845 Global Clock Controller to parent_data dt-bindings: clock: separate SDM845 GCC clock bindings clk: qcom: apss-ipq-pll: Add missing MODULE_DEVICE_TABLE clk: qcom: a53-pll: Add missing MODULE_DEVICE_TABLE clk: qcom: a7-pll: Add missing MODULE_DEVICE_TABLE dt: bindings: add mt7621-sysc device tree binding documentation dt-bindings: clock: add dt binding header for mt7621 clocks clk: samsung: Remove redundant dev_err calls clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enable clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callback clk: zynqmp: Drop dependency on ARCH_ZYNQMP clk: zynqmp: Enable the driver if ZYNQMP_FIRMWARE is selected clk: qcom: gcc-sm8350: use ARRAY_SIZE instead of specifying num_parents ...
2021-04-28Merge tag 'mfd-next-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfdLinus Torvalds1-1/+8
Pull MFD updates from Lee Jones: "Core Framework: - Add support for Software Nodes to MFD Core - Remove support for Device Properties from MFD Core - Use standard APIs in MFD Core New Drivers: - Add support for ROHM BD9576MUF and BD9573MUF PMICs - Add support for Netronix Embedded Controller, PWM and RTC - Add support for Actions Semi ATC260x PMICs and OnKey New Device Support: - Add support for DG1 PCIe Graphics Card to Intel PMT - Add support for ROHM BD71815 PMIC to ROHM BD71828 - Add support for Tolino Shine 2 HD to Netronix Embedded Controller - Add support for AX10 BMC Secure Updates to Intel M10 BMC Removed Device Support: - Remove Arizona Extcon support from MFD - Remove ST-E AB8500 Power Supply code from MFD - Remove AB3100 altogether New Functionality: - Add support for SMBus and I2C modes to Dialog DA9063 - Switch to using Software Nodes in Intel (various) New/converted Device Tree bindings: - rohm bd71815-pmic, rohm bd9576-pmic, netronix ntxec, actions atc260x, ricoh rn5t618, qcom pm8xxx - Fix-ups: - Fix error handling/path; intel_pmt - Simplify code; rohm-bd718x7, ab8500-core, intel-m10-bmc - Trivial clean-ups (reordering, spelling); rohm-generic, rn5t618, max8997 - Use correct data-type; db8500-prcmu - Remove superfluous code; lp87565, intel_quark_i2c_gpi, lpc_sch, twl - Use generic APIs/defines; lm3533-core, intel_quark_i2c_gpio - Regmap related fix-ups; intel-m10-bmc, sec-core - Reorder resource freeing during remove; intel_quark_i2c_gpio - Make table indexing more robust; intel_quark_i2c_gpio - Fix reference imbalances; arizona-irq - Staticify and (un)constify things; arizona-spi, stmpe, ene-kb3930, intel-lpss-acpi, intel-lpss-pci, atc260x-i2c, intel_quark_i2c_gpio Bug Fixes: - Fix incorrect (register) values; intel-m10-bmc - Kconfig related fixes; ABX500_CORE - Do not clear the Auto Reload Register; stm32-timers" * tag 'mfd-next-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (84 commits) mfd: intel-m10-bmc: Add support for MAX10 BMC Secure Updates Revert "mfd: max8997: Add of_compatible to Extcon and Charger mfd_cell" mfd: twl: Remove unused inline function twl4030charger_usb_en() dt-bindings: mfd: Convert pm8xxx bindings to yaml dt-bindings: mfd: Add compatible for pmk8350 rtc i2c: designware: Get rid of legacy platform data mfd: intel_quark_i2c_gpio: Convert I²C to use software nodes mfd: lpc_sch: Partially revert "Add support for Intel Quark X1000" mfd: arizona: Fix rumtime PM imbalance on error mfd: max8997: Replace 8998 with 8997 mfd: core: Use acpi_find_child_device() for child devices lookup mfd: intel_quark_i2c_gpio: Don't play dirty trick with const mfd: intel_quark_i2c_gpio: Enable MSI interrupt mfd: intel_quark_i2c_gpio: Reuse BAR definitions for MFD cell indexing mfd: ntxec: Support for EC in Tolino Shine 2 HD mfd: stm32-timers: Avoid clearing auto reload register mfd: intel_quark_i2c_gpio: Replace I²C speeds with descriptive definitions mfd: intel_quark_i2c_gpio: Remove unused struct device member mfd: intel_quark_i2c_gpio: Unregister resources in reversed order mfd: Kconfig: ABX500_CORE should depend on ARCH_U8500 ...
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