aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/clk
AgeCommit message (Collapse)AuthorFilesLines
2017-03-20clk: tegra: Add super clock mux/dividerPeter De Schrijver2-5/+89
Add a super clock type which implements both mux and divider. This is used for aclk. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-20clk: tegra: Define Tegra210 DMIC clocksPeter De Schrijver3-1/+28
Tegra210 has 3 inputs for Digital Microphones (DMICs). Provide the required clocks for them. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-20clk: tegra: Fix constness for peripheral clocksPeter De Schrijver2-4/+4
checkpatch now warns for const ** and expects const * const * to be used instead. This means we have to update the prototypes and function declarations to handle this change. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-20clk: tegra: Define Tegra210 DMIC sync clocksPeter De Schrijver3-24/+73
Tegra210 has 3 DMIC inputs which can be clocked from the recovered clock of several other audio inputs (eg. i2s0, i2s1, ...). To model this, we add a 3 new clocks similar to the audio* clocks which handle the same function for the I2S and SPDIF clocks. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-20clk: tegra: Add CEC clockPeter De Schrijver6-0/+6
This clock is used to clock the HDMI CEC interface. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-20clk: tegra: Fix type for m fieldPeter De Schrijver1-1/+1
When used as part of fractional ndiv calculations, the current range is not enough because the denominator of the fraction is multiplied with m. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-20clk: tegra: Correct tegra210_pll_fixed_mdiv_cfg rate calculationPeter De Schrijver1-1/+7
Return the actually achieved rate in cfg->output_rate rather than just the requested rate. This is important to make clk_round_rate() return the correct result. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-20clk: tegra: Don't warn for PLL defaults unnecessarilyPeter De Schrijver1-6/+12
If the PLL is on, only warn if the defaults are not yet set. Otherwise be silent. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-20clk: tegra: Remove non-existing pll_m_out1 clockPeter De Schrijver1-5/+0
This clock doesn't actually exist, so remove it. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-20clk: tegra: Correct afi clock parentPeter De Schrijver1-1/+1
The parent for afi is actually mselect, not clk_m. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-20clk: tegra: Fix ISP clock modellingPeter De Schrijver3-2/+11
The 2 ISP clocks (ispa and ispb) share a mux/divider control. So model this as 1 mux/divider clock and child gate clocks. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-20clk: tegra: Fix pll_a1 iddq register, add pll_a1Peter De Schrijver1-1/+2
pll_a1 was using CLK_RST_CONTROLLER_PLLA1_MISC_0 for IDDQ control rather than the correct register CLK_RST_CONTROLLER_PLLA1_MISC_1. Also add pll_a1 to the set of clocks defined for Tegra210. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-20clk: sunxi-ng: fix recalc_rate formula of NKMP clocksIcenowy Zheng1-1/+1
In commit e66f81bbd746 ("clk: sunxi-ng: Implement factors offsets"), the final formula of NKMP clocks' recalc_rate is refactored; however, the refactored formula broke the calculation due to some C language operand priority problem -- the priority of operand >> is lower than * and /, makes the formula being parsed as "(parent_rate * n * k) >> (p / m)", but it should be "(parent_rate * n * k >> p) / m". Add the pair of parentheses to fix up this issue. This pair of parentheses used to exist in the old formula. Fixes: e66f81bbd746 ("clk: sunxi-ng: Implement factors offsets") Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-20clk: sunxi-ng: Fix div/mult settings for osc12M on A64Philipp Tomsich1-1/+1
The mult/div for osc12M was previously backwards (giving a 48M rate for osc12M). Fix it. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-16clk: meson-gxbb: expose clock CLKID_RNG0Heiner Kallweit1-1/+1
Expose clock CLKID_RNG0 which is needed for the HW random number generator. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-03-10clk: rockchip: mark some rk3368 core-clks as criticalElaine Zhang1-0/+3
Mark pclk_pd_alive, pclk_peri, hclk_peri as critical Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-03-10clk: rockchip: export SCLK_TIMERXX id for timers on rk3368Elaine Zhang1-12/+12
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-03-10clk: rockchip: describe clk_gmac using the new muxgrf type on rk3328Elaine Zhang1-0/+9
With the newly introduced clk type for muxes in the grf we now can describe some missing clocks, like the clk_gmac2io and clk_gmac2phy that selects between clk_mac2io_src and gmac_clkin based on a bit set in the general register files. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-03-08clk: ti: convert to use proper register definition for all accessesTero Kristo16-276/+225
Currently, TI clock driver uses an encapsulated struct that is cast into a void pointer to store all register addresses. This can be considered as rather nasty hackery, and prevents from expanding the register address field also. Instead, replace all the code to use proper struct in place for this, which contains all the previously used data. This patch is rather large as it is touching multiple files, but this can't be split up as we need to avoid any boot breakage. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
2017-03-08clk: ti: dpll44xx: fix clksel register initializationTero Kristo1-0/+15
clksel register pointer should be used for the DPLL-MX autoidle handling. Currently this is not setup at all. Fix by adding proper handling for the register. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
2017-03-08clk: ti: gate: export gate_clk_ops locallyTero Kristo2-1/+2
These are going to be used by the clkctrl support that will be introduced later. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
2017-03-08clk: ti: divider: add driver internal API for parsing divider dataTero Kristo2-22/+45
This can be used from the divider itself, and also from the clkctrl clocks once this is introduced. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
2017-03-08clk: ti: divider: convert TI divider clock to use its own data representationTero Kristo3-13/+24
Instead of using the generic clock driver data struct, use one internal for the TI clock driver itself. This allows modifying the register access parts in subsequent patch. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
2017-03-08clk: ti: mux: convert TI mux clock to use its internal data representationTero Kristo2-5/+16
Instead of using the generic clock driver data struct, use one internal for the TI clock driver itself. This allows modifying the register access parts in subsequent patch. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
2017-03-08clk: ti: drop unnecessary MEMMAP_ADDRESSING flagTero Kristo4-7/+1
This has been superceded by the usage of ti_clk_ll_ops for now. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
2017-03-08clk: ti: omap4: cleanup unnecessary clock aliasesTero Kristo1-186/+2
Cleanup any unnecessary DT_CLK() alias entries from the OMAP4 clock file. Most of these are now handled dynamically by the driver code. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
2017-03-08clk: ti: enforce const types on string arraysTero Kristo3-6/+6
Constant string arrays should use const char * const instead of just const char *. Change the implementations using these to proper type. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
2017-03-08clk: ti: move omap2_init_clk_clkdm under TI clock driverTero Kristo2-0/+31
This is not needed outside the driver, so move it inside it and remove the prototype from the public header also. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
2017-03-08clk: ti: use automatic clock alias generation frameworkTero Kristo10-15/+49
Generate clock aliases automatically for all TI clock drivers. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
2017-03-08clk: ti: add API for creating aliases automatically for simple clock typesTero Kristo2-0/+27
This API generates clock aliases automatically for simple clock types (fixed-clock, fixed-factor-clock), so that we don't need to add the data for these statically into tables. Shall be called from the SoC specific clock init. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
2017-03-08clk: ti: add support for automatic clock alias generationTero Kristo2-0/+67
Large portions of the OMAP framework still depend on the support of having clock aliases in place, so add support functions for generating these automatically. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
2017-03-07clk: rockchip: Make uartpll a child of the gpll on rk3036Heiko Stuebner1-0/+7
The shared uart-pll is on boot a child of the apll that can get changed by cpu frequency scaling. So move it away to the more stable gpll to make sure the uart doesn't break on cpu frequency changes. This turned up during the 4.11 merge-window when commit 6a171b299379 ("serial: 8250_dw: Allow hardware flow control to be used") added general termios enablement making the uart on rk3036 change frequency and thus making it susceptible for the frequency scaling issue. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-03-07clk: rockchip: add "," to mux_pll_src_apll_dpll_gpll_usb480m_p on rk3036Heiko Stuebner1-1/+1
The mux_pll_src_apll_dpll_gpll_usb480m_p parent list was missing a "," between the 3rd and 4th parent names, making them fall together and thus lookups fail. Fix that. Fixes: 5190c08b2989 ("clk: rockchip: add clock controller for rk3036") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-03-07clk: core: Copy connection idLeonard Crestez1-1/+2
Some drivers use sprintf to build clk connection id names but the clk core will save those strings and occasionally print them back. Duplicate the con_id strings instead of fixing all the users. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-03-06clk: renesas: r8a7796: Add IMR clocksSergei Shtylyov1-0/+2
Add the IMR[0-1] clocks to the R8A7796 CPG/MSSR driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> [geert: Correct parent clocks] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-03-06clk: renesas: r8a7795: Add IMR clocksSergei Shtylyov1-0/+4
Add the IMR[0-3] clocks to the R8A7795 CPG/MSSR driver. Based on the original (and large) patch by Konstantin Kozhevnikov <Konstantin.Kozhevnikov@cogentembedded.com>. Signed-off-by: Konstantin Kozhevnikov <Konstantin.Kozhevnikov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-03-06clk: sunxi-ng: sun5i: Fix mux width for csi clockPriit Laes1-1/+1
Mux for CSI clock is 3 bits, not 2. Signed-off-by: Priit Laes <plaes@plaes.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-06clk: sunxi-ng: tighten SoC deps on explicit AllWinner SoCsPeter Robinson1-0/+8
Tighten the depends on the various AllWinn SoCs so we don't inadvertantly get clock drivers when we're not wanting them like 32 bit SoC clocks for 64 bit configs. Ensure there's still test coverage though. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-06clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driverIcenowy Zheng3-9/+323
Allwinner H5 is a SoC that features a design which keeps the peripheral compatible with H3, so that it have also a CCU like the one on H3 -- only one bus gate/reset is added, and the mmc sample/output phases are removed because of MMC controller update. Add its support in our existing H3 CCU driver. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-06clk: sunxi-ng: gate: Support common pre-dividersChen-Yu Tsai1-0/+47
Some clock gates have a pre-divider between the source input and the gate itself. A notable example is the HSIC 12 MHz clock found on the A83T, which has the 24 MHz main oscillator as its input, and a /2 pre-divider. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-06clk: sunxi-ng: sun6i: Fix enable bit offset for hdmi-ddc module clockChen-Yu Tsai1-1/+1
The enable bit offset for the hdmi-ddc module clock is wrong. It is pointing to the main hdmi module clock enable bit. Reported-by: Bob Ham <rah@settrans.net> Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks") Cc: stable@vger.kernel.org # 4.9.x- Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-06clk: sunxi: ccu-sun5i needs nkmpArnd Bergmann1-0/+1
A randconfig build ran into this rare link error: drivers/clk/sunxi-ng/ccu-sun5i.o:(.data.__compound_literal.1+0x4): undefined reference to `ccu_nkmp_ops' drivers/clk/sunxi-ng/ccu-sun5i.o:(.data.__compound_literal.7+0x4): undefined reference to `ccu_nkmp_ops' This adds the missing 'select'. Fixes: 5e73761786d6 ("clk: sunxi-ng: Add sun5i CCU driver") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-06clk: sunxi-ng: mp: Adjust parent rate for pre-dividersChen-Yu Tsai1-0/+8
The MP style clocks support an mux with pre-dividers. While the driver correctly accounted for them in the .determine_rate callback, it did not in the .recalc_rate and .set_rate callbacks. This means when calculating the factors in the .set_rate callback, they would be off by a factor of the active pre-divider. Same goes for reading back the clock rate after it is set. Cc: stable@vger.kernel.org Fixes: 2ab836db5097 ("clk: sunxi-ng: Add M-P factor clock support") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-03-06clk: rockchip: Set "ignore unused" for PMU M0 clocks on rk3399Douglas Anderson1-4/+4
The PMU Cortex M0 on rk3399 is intended to be used for things like DDRFreq transitions, suspend/resume, and other things that are the purview of ARM Trusted Firmware and not the kernel. As such, the kernel shouldn't be messing with the clocks. Add CLK_IGNORE_UNUSED to these clocks. Without this change, the following was observed on a Chromebook with a rk3399 (using not-yet-upstream ARM Trusted Firmware code and not-yet-upstream kernel code based on kernel-4.4): 1. We init the clock framework. 2. We start up "DDRFreq", which causes ATF to occasionally fire up the M0 for transitions. Each time ATF fires up the M0 it will turn on these clocks and each time it is done it will turn them off. 3. We finally get to the the part of the kernel that calls clk_disable_unused() and we disables the clocks. You can see the race above. Basically everything is fine as long as ARM Trusted Firmware isn't starting up the M0 at exactly the same time that the kernel is disabling unused clocks. ...but if the race happens then we go boom. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-03-03Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds2-6/+57
Pull ARM SoC late DT updates from Arnd Bergmann: "These updates have been kept in a separate branch mostly because they rely on updates to the respective clk drivers to keep the shared header files in sync. This includes two branches for arm64 dt updates, both following up on earlier changes for the same platforms that are already merged: Samsung: - add USB3 support in Exynos7 - minor PM related updates Amlogic: - new machines: WeTek Set-top-boxes - various devices added to DT There are also a couple of bugfixes that trickled in since the start of the merge window: - The moxart_defconfig was not building the intended platform - CPU-hotplug was broken on ux500 - Coresight was broken on Juno (never worked)" * tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (26 commits) ARM: deconfig: fix the moxart defconfig ARM: ux500: resume the second core properly arm64: dts: juno: update definition for programmable replicator arm64: dts: exynos: Add regulators for Vbus and Vbus-Boost arm64: dts: exynos: Add USB 3.0 controller node for Exynos7 arm64: dts: exynos: Use macros for pinctrl configuration on Exynos7 pinctrl: dt-bindings: samsung: Add Exynos7 specific pinctrl macro definitions arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e ARM64: dts: meson-gxbb-p200: add ADC laddered keys ARM64: dts: meson: meson-gx: add the SAR ADC ARM64: dts: meson-gxl: add the pwm_ao_b pin ARM64: dts: meson-gx: add the missing pwm_AO_ab node clk: gxbb: fix CLKID_ETH defined twice ARM64: dts: meson-gxl: rename Nexbox A95x for consistency clk: gxbb: add the SAR ADC clocks and expose them dt-bindings: amlogic: Add WeTek boards ARM64: dts: meson-gxbb: Add support for WeTek Hub and Play dt-bindings: vendor-prefix: Add wetek vendor prefix ARM64: dts: meson-gxm: Rename q200 and q201 DT files for consistency ARM64: dts: meson-gx: Add HDMI HPD/DDC pinctrl nodes ...
2017-03-02Merge branch 'next/late' with mainlineArnd Bergmann3-8/+63
* next/late: (25 commits) arm64: dts: exynos: Add regulators for Vbus and Vbus-Boost arm64: dts: exynos: Add USB 3.0 controller node for Exynos7 arm64: dts: exynos: Use macros for pinctrl configuration on Exynos7 pinctrl: dt-bindings: samsung: Add Exynos7 specific pinctrl macro definitions arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e ARM64: dts: meson-gxbb-p200: add ADC laddered keys ARM64: dts: meson: meson-gx: add the SAR ADC ARM64: dts: meson-gxl: add the pwm_ao_b pin ARM64: dts: meson-gx: add the missing pwm_AO_ab node clk: gxbb: fix CLKID_ETH defined twice clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks ARM64: dts: meson-gxl: rename Nexbox A95x for consistency clk: gxbb: add the SAR ADC clocks and expose them dt-bindings: amlogic: Add WeTek boards ARM64: dts: meson-gxbb: Add support for WeTek Hub and Play dt-bindings: vendor-prefix: Add wetek vendor prefix ARM64: dts: meson-gxm: Rename q200 and q201 DT files for consistency ARM64: dts: meson-gx: Add HDMI HPD/DDC pinctrl nodes ARM64: dts: meson-gxbb-vega-s95: Add LED ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-02-25Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linuxLinus Torvalds99-1376/+10103
Pull clk updates from Stephen Boyd: "The usual collection of new drivers, non-critical fixes, and updates to existing clk drivers. The bulk of the work is on Allwinner and Rockchip SoCs, but there's also an Intel Atom driver in here too. New Drivers: - Tegra BPMP firmware - Hisilicon hi3660 SoCs - Rockchip rk3328 SoCs - Intel Atom PMC - STM32F746 - IDT VersaClock 5P49V5923 and 5P49V5933 - Marvell mv98dx3236 SoCs - Allwinner V3s SoCs Removed Drivers: - Samsung Exynos4415 SoCs Updates: - Migrate ABx500 to OF - Qualcomm IPQ4019 CPU clks and general PLL support - Qualcomm MSM8974 RPM - Rockchip non-critical fixes and clk id additions - Samsung Exynos4412 CPUs - Socionext UniPhier NAND and eMMC support - ZTE zx296718 i2s and other audio clks - Renesas CAN and MSIOF clks for R-Car M3-W - Renesas resets for R-Car Gen2 and Gen3 and RZ/G1 - TI CDCE913, CDCE937, and CDCE949 clk generators - Marvell Armada ap806 CPU frequencies - STM32F4* I2S/SAI support - Broadcom BCM2835 DSI support - Allwinner sun5i and A80 conversion to new style clk bindings" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (130 commits) clk: renesas: mstp: ensure register writes complete clk: qcom: Do not drop device node twice clk: mvebu: adjust clock handling for the CP110 system controller clk: mvebu: Expand mv98dx3236-core-clock support clk: zte: add i2s clocks for zx296718 clk: sunxi-ng: sun9i-a80: Fix wrong pointer passed to PTR_ERR() clk: sunxi-ng: select SUNXI_CCU_MULT for sun5i clk: sunxi-ng: Check kzalloc() for errors and cleanup error path clk: tegra: Add BPMP clock driver clk: uniphier: add eMMC clock for LD11 and LD20 SoCs clk: uniphier: add NAND clock for all UniPhier SoCs ARM: dts: sun9i: Switch to new clock bindings clk: sunxi-ng: Add A80 Display Engine CCU clk: sunxi-ng: Add A80 USB CCU clk: sunxi-ng: Add A80 CCU clk: sunxi-ng: Support separately grouped PLL lock status register clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers clk: qcom: SDHCI enablement on Nexus 5X / 6P ...
2017-02-23Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds1-0/+4
Pull ARM DT updates from Arnd Bergmann: "A total of 380 patches this time, mostly adding support for more hardware in the device tree descriptions. There is not much exciting here for 4.11, but I've tried my best to condense the information from the pull requests I got into a readable summary. Noteworthy changes to existing platforms include: - The GIC memory map was a bit wrong almost everywhere and now gets fixed up - The Allwinner platforms convert to the generic pinmux properties - The Marvell EBU platforms now use the new DSA binding - Samsung Exynos4212 was unused and gets removed - The Renesas power management got improved New production machines: - Lego Mindstorms EV3: https://www.lego.com/en-us/mindstorms/about-ev3 - Beelink X2 Android media box: http://linux-sunxi.org/Beelink_X2 - "Romulus" baseboard management controller for OpenPower - Axentia TSE-850 Data Radio Channel (DARC) encoder: http://www.axentia.se/db/equipment.html - Luxul XAP-1410 and XWR-1200 wireless access points: https://luxul.com/xap-1410 New SoCs: - Allwinner H2+ and V3s, both minor variations of already supported chips: http://www.allwinnertech.com/index.php?c=product&a=index&id=38 - Marvell Prestera DX packet processors based on Armada XP architecture: http://www.marvell.com/switching/prestera-dx/ - Samsung Exynos4412 Prime gets added, a minor variation of Exynos4412 New developer and reference boards: - Lichee Pi One, Lichee Pi Zero and Orange Pi Zero, all based on Allwinner SoCs: http://linux-sunxi.org/LicheePi_One http://www.orangepi.org/orangepizero/ - SAMA5d36ek Reference platform: http://www.atmel.com/tools/sama5d36-ek.aspx - Beaglebone Green Wireless and Black Wireless: https://beagleboard.org/black-wireless https://beagleboard.org/green-wireless - phyCORE-AM335x System on Module: http://phytec.com/products/system-on-modules/phycore/am335x/ - New revision of "vf610-zii" Zodiac Inflight Innovations board - Various i.MX System-on-Module: Is.IoT MX6UL, SavageBoard, Engicam i.Core: http://www.opossom.com/english/index.html http://www.savageboard.org/ http://www.engicam.com/en/products/embedded/som/sodimm/is-iot-mx6ul http://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q - Liebherr (LWN) monitor 6 based on i.MX6 Quad, no idea what this is - Cleanups and bugfixes on at91, bcm53xx, i.MX, mvebu, omap, oxnas, qcom, rockchip, sti, stm32 and tegra New device supports added to some boards and SoCs, briefly by platform: - Allwinner: SPDIF, A33 cpufreq, A33 Mali GPU - Aspeed: network, ipmi bt, gpio, pinmux - Broadcom: video encoder for raspberry pi, qspi, ethernet, sd/mmc - TI DaVinci: gpio, lcdc, usb, video-in, uart - TI Keystone 2: MSM RAM, power/reset, uart - Mediatek MT2701: clocks, iommu, spi, nand, adc, thermal - Marvell EBU: ethernet switch on Turris Omnia - NXP i.MX: otp ram, USB, wifi, bluetooth, spdif, spi, pmic, eeprom, mmc, nand - TI OMAP: - Qualcomm: coresight, gyro/accelerometer, hdmi - Renesas: pmic, soc-id - Rockchip: qos - Samsung: audio on Odroid-X - Socfpga: FPGA manager, i2c, led, can, watchdog, nand, power monitor - STi: video in/out - STM32: timer, pwm, i2c, rtc, add, i2s - NVIDIA Tegra: tpm - Uniphier: mmc/sd pinmux" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (380 commits) ARM: dts: armada-385-linksys: fix DSA compatible property ARM: dts: Fix typo in armada-xp-98dx4251 ARM: DTS: Fix register map for virt-capable GIC dt-bindings: arm,gic: Fix binding example for a virt-capable GIC ARM: dts: sun8i: sinlinx: Enable audio nodes ARM: dts: sun8i: parrot: Enable audio nodes ARM: dts: sun8i: Add audio codec, dai and card for A33 ARM: dts: Add EMAC AXI settings for Arria10 ARM: dts: am335x-chiliboard: Support charger ARM: dts: am335x-chiliboard: Support power button ARM: sun8i: dt: Add mali node dt-bindings: gpu: Add Mali Utgard bindings ARM: dts: stm32: Add I2C1 support for STM32429 eval board ARM: dts: stm32: Add I2C1 support for STM32F429 SoC ARM: dts: stm32: Use clock DT binding definition on stm32f429 family dt-bindings: mfd: stm32f4: Add missing binding definition dt-bindings: mfd: stm32f4: Fix STM32F4_X_CLOCK() macro ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-disco ARM: dts: stm32: add Timers driver for stm32f429 MCU ARM: dts: add the AB8500 sysclk to the device trees ...
2017-02-16clk: renesas: mstp: ensure register writes completeChris Brandt1-0/+6
When there is no status bit, it is possible for the clock enable/disable operation to have not completed by the time the driver code resumes execution. This is due to the fact that write operations are sometimes queued and delayed internally. Doing a read ensures the write operations has completed. Fixes: b6face404f38 ("ARM: shmobile: r7s72100: add essential clock nodes to dtsi") Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-02-16Merge tag 'amlogic-dt64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/lateArnd Bergmann2-6/+57
Pull "Amlogic DT updates for v4.11, round 2" from Kevin Hilman: - add SAR ADC driver - add ADC laddered keys to meson-gxbb-p200 board * tag 'amlogic-dt64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: ARM64: dts: meson-gxbb-p200: add ADC laddered keys ARM64: dts: meson: meson-gx: add the SAR ADC ARM64: dts: meson-gxl: add the pwm_ao_b pin ARM64: dts: meson-gx: add the missing pwm_AO_ab node clk: gxbb: fix CLKID_ETH defined twice ARM64: dts: meson-gxl: rename Nexbox A95x for consistency clk: gxbb: add the SAR ADC clocks and expose them dt-bindings: amlogic: Add WeTek boards ARM64: dts: meson-gxbb: Add support for WeTek Hub and Play dt-bindings: vendor-prefix: Add wetek vendor prefix ARM64: dts: meson-gxm: Rename q200 and q201 DT files for consistency ARM64: dts: meson-gx: Add HDMI HPD/DDC pinctrl nodes ARM64: dts: meson-gxbb-vega-s95: Add LED ARM64: dts: meson-gx: add the serial CTS and RTS pin groups ARM64: dts: meson-gx: add the missing uart_AO_B clk: meson-gxbb: Export HDMI clocks ARM64: dts: meson-gxm: add SCPI configuration for GXM ARM64: dts: meson-gx: move the SCPI and SRAM nodes to meson-gx
Copyright © 1996 – 2026 Jason A. Donenfeld. All Rights Reverse Engineered.