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2017-01-26clk: stm32f7: Introduce stm32f7 clocks for STM32F746 boardsGabriel Fernandez1-6/+271
This patch enables clocks for STM32F746 boards. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-26clk: uniphier: continue probing even if some clocks fail to registerMasahiro Yamada1-5/+2
Do not let the entire probe function fail even if some clocks fail to register. Let's continue with succeeded clocks. This will give the system more chances to boot and allow us to investigate the cause of the failure. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-26Merge branch 'clk-imx7', 'clk-bcm2835' into clk-nextStephen Boyd2-49/+255
* clk-imx7: clk: imx7d: Add the OCOTP clock * clk-bcm2835: clk: bcm2835: Add leaf clock measurement support, disabled by default clk: bcm2835: Register the DSI0/DSI1 pixel clocks. clk: bcm2835: Don't rate change PLLs on behalf of DSI PLL dividers.
2017-01-23clk: gxbb: add the SAR ADC clocks and expose themMartin Blumenstingl2-3/+54
The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks: - a mux clock to choose between different ADC reference clocks (this is 2-bit wide, but the datasheet only lists the parents for the first bit) - a divider for the input/reference clock - a gate which enables the ADC clock Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and CLKID_SANA (which seems to enable the analog inputs, but unfortunately there is no documentation for this - we just mimic what the vendor driver does). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-01-23clk: sunxi-ng: Add sun5i CCU driverMaxime Ripard4-0/+1100
The Allwinner A10s, A13, R8 and NextThing GR8 are all based on the same silicon, and all share the same clocks. However, they're not packaged in the same way, and therefore not all the controllers are actually available on all these SoCs. Introduce a clock controller driver for all these SoCs with different compatibles to take that into account. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-23clk: sunxi-ng: Implement global pre-dividerMaxime Ripard2-1/+9
Some clocks have a global pre-divider that applies to all their parents. Since it might also apply to clocks that have a single parent, this is merged in the ccu_common structure, unlike the other pre-divider settings that are tied to a specific index, and thus a specific parent. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-23clk: sunxi-ng: Implement multiplier maximumMaxime Ripard6-20/+32
Some multipliers have a maximum rate that is lower than what the register width allows to. Add a field in the multiplier structure to allow CCU driver to set that maximum. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-23clk: sunxi-ng: mult: Fix minimum in round rateMaxime Ripard1-1/+1
The previous code was always taking 1 as the minimum in it's round_rate function, ignoring entirely what was set as minimum in the clock definition. Make sure that's not the case anymore. Fixes: 2beaa601c849 ("clk: sunxi-ng: Implement minimum for multipliers") Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-23clk: sunxi-ng: Implement factors offsetsMaxime Ripard8-29/+79
The factors we've seen so far all had an offset of one. However, on the earlier Allwinner SoCs, some factors could have no offset at all, meaning that the value computed to reach the rate we want to use was the one we had to program in the registers. Implement an additional field for the factors that can have such an offset (linears, not based on a power of two) to specify that offset. This offset is not linked to the extremums that can be specified in those structures too. The minimum and maximum are representing the range of values we can use to try to compute the best rate. The offset comes later on when we want to set the best value in the registers. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-23clk: sunxi-ng: multiplier: Add fractional supportMaxime Ripard2-0/+10
Some clocks on the earlier SoCs such as the video PLLs are multipliers with fractional settings. Support those cases. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2017-01-23clk: renesas: mstp: Make INTC-SYS a critical clockGeert Uytterhoeven1-0/+5
INTC-SYS is the module clock for the GIC. Accessing the GIC while it is disabled causes: Unhandled fault: asynchronous external abort (0x1211) at 0x00000000 Currently, the GIC-400 driver cannot enable its module clock for several reasons: - It does not use a platform device, so Runtime PM is not an option, - gic_of_init() runs before any clocks are registered, so it cannot enable the clock explicitly, - gic_of_init() cannot return -EPROBE_DEFER, as IRQCHIP_DECLARE() doesn't support deferred probing. Hence we have to keep on relying on the boot loader for enabling the module clock. To prevent the module clock from being disabled when the CCF core thinks it is unused, and thus causing a system lock-up, add a check to the MSTP clock driver and enable CLK_IS_CRITICAL. This will make sure the module clock is never disabled. This is a hard dependency for describing the INTC-SYS clock in DT on R-Mobile APE6 and R-Car Gen2. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-23clk: renesas: cpg-mssr: Migrate to CLK_IS_CRITICALGeert Uytterhoeven1-9/+2
When the Renesas CPG/MSSR driver was introduced, it was anticipated that critical clocks would be handled through a new CLK_ENABLE_HAND_OFF flag soon. However, CLK_ENABLE_HAND_OFF never made it upstream. Instead, commit 32b9b10961860860 ("clk: Allow clocks to be marked as CRITICAL") introduced CLK_IS_CRITICAL, a flag with slightly differing semantics. Still, it can be used to prevent e.g. the GIC module clock from being turned off, until the GIC-400 driver has full support for Runtime PM. Hence migrate the Renesas CPG/MSSR driver from CLK_ENABLE_HAND_OFF to CLK_IS_CRITICAL. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-23clk: rockchip: rk3288: make all niu clocks criticalJacob Chen1-7/+14
NIU clocks are related to the interconnect and it's important to other blocks. Since we don't have a driver to handle it, we should always enable it to avoid casually close. Make all of them critical,so that we don't have to each clock on its own once things break. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> [dropped the matching CLK_IGNORE_UNUSED flags] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-22clk: rockchip: use rk3288 vip_out clock idsJacob Chen1-1/+1
Reference the newly added vip clock-ids in the clock-tree. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-21Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linuxLinus Torvalds1-7/+7
Pull clk fix from Stephen Boyd: "One fix for Samsung Exynos524x SoCs where recent IOMMU patches have caused some of these clocks to turn off when they were always left on before" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk/samsung: exynos542x: mark some clocks as critical
2017-01-20clk: imx7d: Add the OCOTP clockFabio Estevam1-0/+1
Add the OCOTP so that this hardware block can be used. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-20clk: bcm2835: Add leaf clock measurement support, disabled by defaultEric Anholt1-25/+119
This proved incredibly useful during debugging of the DSI driver, to see if our clocks were running at rate we requested. Let's leave it here for the next person interacting with clocks on the platform (and so that hopefully we can just hook it up to debugfs some day). Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-20clk: bcm2835: Register the DSI0/DSI1 pixel clocks.Eric Anholt1-12/+109
The DSI pixel clocks are muxed from clocks generated in the analog phy by the DSI driver. In order to set them as parents, we need to do the same name lookup dance on them as we do for our root oscillator. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-20clk: bcm2835: Don't rate change PLLs on behalf of DSI PLL dividers.Eric Anholt1-14/+28
Our core PLLs are intended to be configured once and left alone. With the SET_RATE_PARENT, asking to set the PLLD_DSI1 clock rate would change PLLD just to get closer to the requested DSI clock, thus changing PLLD_PER, the UART and ethernet PHY clock rates downstream of it, and breaking ethernet. We *do* want PLLH to change so that PLLH_AUX can be exactly the value we want, though. Thus, we need to have a per-divider policy of whether to pass rate changes up. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-20clk: cs2000: add Suspend/Resume featureKhiem Nguyen1-0/+22
CS2000 needs re-setup when redume, otherwise, it can't handle correct clock rate. Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@rvc.renesas.com> [Kuninori: cleanup original patch] Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-20clk: vc5: Add support for IDT VersaClock 5P49V5923 and 5P49V5933Marek Vasut3-0/+802
Add driver for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These chips have two clock inputs, XTAL or CLK, which are muxed into single PLL/VCO input. In case of 5P49V5923, the XTAL in built into the chip while the 5P49V5923 requires external XTAL. The PLL feeds two fractional dividers. Each fractional divider feeds output mux, which allows selecting between clock from the fractional divider itself or from output mux on output N-1. In case of output mux 0, the output N-1 is instead connected to the output from the mux feeding the PLL. The driver thus far supports only the 5P49V5923 and 5P49V5933, while it should be easily extensible to the whole 5P49V59xx family of chips as they are all pretty similar. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Michael Turquette <mturquette@baylibre.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: linux-renesas-soc@vger.kernel.org Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-20Merge tag 'v4.11-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-nextStephen Boyd8-13/+1067
Pull Rockchip clk updates from Heiko Stuebner: A new clock-type for the 1-2 muxes per soc that are for whatever reason controlled through the General Register Files, support for the rk3328 clock-controller (including a new pll-type) and the usual clock ids and some fixes. * tag 'v4.11-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: dt-bindings: clk: add rockchip,grf property for RK3399 clk: rockchip: use clock ids for memory controller parts on rk3066/rk3188 clk: rockchip: use rk3288 isp_in clock ids clk: rockchip: add clock ids for memory controller parts on rk3066/rk3188 clk: rockchip: add rk3288 isp_in clock ids clk: rockchip: Remove useless init of "grf" to -EPROBE_DEFER clk: rockchip: add clock controller for rk3328 dt-bindings: add bindings for rk3328 clock controller clk: rockchip: add dt-binding header for rk3328 clk: rockchip: add new pll-type for rk3328 clk: rockchip: describe aclk_vcodec using the new muxgrf type on rk3288 clk: rockchip: add a clock-type for muxes based in the grf
2017-01-20Merge tag 'clk-v4.11-samsung' of git://linuxtv.org/snawrocki/samsung into clk-nextStephen Boyd5-1041/+18
Pull Samsung clk updates from Sylwester Nawrocki: - addition of the CPU clock configuration data for Exynos4412 Prime SoC variant, - removal of driver for deprecated Exynos4415 SoC, - switching from the syscore to regular system sleep PM ops in the audio subsystem clocks controller driver, - updates of the definitions of some "Network On Chip" related clocks. * tag 'clk-v4.11-samsung' of git://linuxtv.org/snawrocki/samsung: clk: samsung: Remove Exynos4415 driver (SoC not supported anymore) clk: samsung: exynos-audss: Replace syscore PM with platform device PM clk: samsung: exynos5433: Set NoC (Network On Chip) clocks as critical clk: samsung: Add CPU clk configuration data for Exynos4412 Prime
2017-01-20clk: imx6: don't restrict LDB mux changes on QuadPlusLucas Stach1-8/+13
The LDB mux/gate layout has been fixed on QuadPlus, so there is no need to restrict the LDB mux changes on this hardware, as the erratum preventing this from working properly is gone. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-20Merge tag 'clk-renesas-for-v4.11-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-nextStephen Boyd1-0/+9
Pull renesas clk updates from Geert Uytterhoeven: - Add CAN and MSIOF related clocks for R-Car M3-W. * tag 'clk-renesas-for-v4.11-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a7796: Add MSIOF controller clocks clk: renesas: r8a7796: Add CAN FD peripheral clock clk: renesas: r8a7796: Add CANFD clock clk: renesas: r8a7796: Add CAN peripheral clock
2017-01-20clk: sunxi-ng: add support for V3s CCUIcenowy Zheng4-0/+666
V3s has a similar but cut-down CCU to H3. Some muxes, especially clocks about CSI, are different, which makes it to need a new CCU driver. Add such a new driver for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-18clk: meson-gxbb: Export HDMI clocksNeil Armstrong1-2/+2
Export HDMI clock from internal to dt-bindings. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-01-18clk: rockchip: fix the incorrect pclk_edp div width for RK3399Xing Zheng1-1/+1
The range of the pclk_edp_div_con is [13:8] and 6 bits, not 5. Reported-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Tested-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-17clk: sunxi-ng: a33: Add CLK_SET_RATE_PARENT to ac-digMylène Josserand1-1/+1
The audio DAI needs to set the clock rates of the ac-dig clock. To make it possible, the parent PLL audio clock rates should also be changed. This is possible via "CLK_SET_RATE_PARENT" flag. Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-16Merge tag 'samsung-dt-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dtOlof Johansson1-0/+4
Samsung DeviceTree update for v4.11: 1. Fixes for initial audio clocks configuration. 2. Enable sound on Odroid-X board. 3. Enable DMA for UART modules on Exynos5 SoCs. 4. Add CPU OPPs for Exynos4412 Prime (newer version of Exynos4412). This pulls necessary change in the clocks. 5. Remove Exynos4212. We do not have any mainline boards with it. This will simplify few bits later. * tag 'samsung-dt-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: exynos: remove Exynos4212 support (dead code) ARM: dts: exynos: Add CPU OPPs for Exynos4412 Prime clk: samsung: Add CPU clk configuration data for Exynos4412 Prime ARM: dts: exynos: Enable DMA support for UART modules on Exynos5 SoCs ARM: dts: exynos: Cleanup Odroid-X2 and enable sound on Odroid-X ARM: dts: exynos: Fix initial audio clocks configuration on Exynos4 boards ARM: dts: exynos: Correct clocks for Exynos4 I2S module Signed-off-by: Olof Johansson <olof@lixom.net>
2017-01-16clk: samsung: Remove Exynos4415 driver (SoC not supported anymore)Krzysztof Kozlowski2-1023/+0
Support for Exynos4415 is going away because there are no internal nor external users. Since commit 46dcf0ff0de3 ("ARM: dts: exynos: Remove exynos4415.dtsi"), the platform cannot be instantiated so remove also the drivers. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Kukjin Kim <kgene@kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-01-13clk: rockchip: use clock ids for memory controller parts on rk3066/rk3188Heiko Stuebner1-2/+2
Add the newly added clock ids to the clock entries of the rk3066/rk3188 clock driver. We won't be needing them in the kernel for a bit yet but as they're used in the new u-boot ddr setup code/dts we should make sure the clock ids stay identical and do not differ. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-13clk: rockchip: use rk3288 isp_in clock idsJacob Chen1-1/+1
Reference the newly added isp clock-ids in the clock-tree. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-12clk: stm32f4: avoid uninitialized variable accessArnd Bergmann1-5/+7
The failure path in the newly added function tries to free an uninitialized pointer: drivers/clk/clk-stm32f4.c: In function 'stm32f4_rcc_init': drivers/clk/clk-stm32f4.c:1106:4: error: 'gate' may be used uninitialized in this function [-Werror=maybe-uninitialized] I'm adding an initialization to NULL here to make the kfree() succeed, and I'm also rearranging the cleanup so that the same kfree() is used for any error path, making the function slightly more robust against newly introduced bugs in the error handling. Fixes: daf2d117cbca ("clk: stm32f4: Add lcd-tft clock") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09Merge branch 'clk-fixes' into clk-nextStephen Boyd1-7/+7
* clk-fixes: clk/samsung: exynos542x: mark some clocks as critical
2017-01-09clk: cdce925: add support for CDCE913, CDCE937, and CDCE949Akinobu Mita2-30/+89
The CDCE925 is a member of the CDCE(L)9xx programmable clock generator family. There are also CDCE913, CDCE937, CDCE949 which have different number of PLLs and outputs. The clk-cdce925 driver supports only CDCE925 in the family. This adds support for the CDCE913, CDCE937, CDCE949, too. Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Cc: Mike Looijmans <mike.looijmans@topic.nl> Cc: Michael Turquette <mturquette@linaro.org> Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09clk: mdm9615: Add EBI2 clockZoran Markovic1-0/+30
Add definition of EBI2 clock used by MDM9615 NAND controller. Cc: Andy Gross <andy.gross@linaro.org> Cc: David Brown <david.brown@linaro.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-arm-msm@vger.kernel.org Cc: linux-soc@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Zoran Markovic <zmarkovic@sierrawireless.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> [sboyd@codeaurora.org: ebi2_clk halt bit is 24 not 23] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09clk: uniphier: remove unneeded #include <linux/delay.h>Masahiro Yamada1-1/+0
This include was needed to suppress build error when this driver was initially merged because <linux/regmap.h> did not include <linux/delay.h> at that time. (developers' headache across sub-systems) The root cause has been fixed by commit adf08d481b52 ("regmap: include <linux/delay.h> from include/linux/regmap.h"), so this line can be dropped now. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09clk: mvebu: adjust AP806 CPU clock frequencies to production chipThomas Petazzoni1-5/+23
This commit adjusts the list of possible "Sample At Reset" values that define the CPU clock frequency of the AP806 (part of Marvell Armada 7K/8K) to the values that have been validated with the production chip. Earlier values were preliminary. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09Merge branch 'clk-hi3660' into clk-nextStephen Boyd3-0/+575
* clk-hi3660: clk: hisilicon: Add clock driver for hi3660 SoC dt-bindings: Document the hi3660 clock bindings
2017-01-09clk: hisilicon: Add clock driver for hi3660 SoCZhangfei Gao3-0/+575
Add clock drivers for hi3660 SoC, this driver controls the SoC registers to supply different clocks to different IPs in the SoC. Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> [sboyd@codeaurora.org: Simplify probe with function pointer] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09clk/samsung: exynos542x: mark some clocks as criticalMarek Szyprowski1-7/+7
Some parent clocks of the Exynos542x clock blocks, which have separate power domains (like DISP, MFC, MSC, GSC, FSYS and G2D) must be always enabled to access any register related to power management unit or devices connected to it. For the time being, until a proper solution based on runtime PM is applied, mark those clocks as critical (instead of ignore unused or even no flags) to prevent disabling them. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com> [Exynos5800 Peach Pi Chromebook] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09clk: clk-conf: Do not print error messages if EPROBE_DEFERGeert Uytterhoeven1-6/+9
EPROBE_DEFER is not an error, hence printing an error message like clk: couldn't get clock 0 for /soc/display@feb00000 may confuse the user. Suppress error messages in case of probe deferral to fix this. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09clk: scpi: don't add cpufreq device if the scpi dvfs node is disabledSudeep Holla1-6/+8
Currently we add the virtual cpufreq device unconditionally even when the SCPI DVFS clock provider node is disabled. This will cause cpufreq driver to throw errors when it gets initailised on boot/modprobe and also when the CPUs are hot-plugged back in. This patch fixes the issue by adding the virtual cpufreq device only if the SCPI DVFS clock provider is available and registered. Fixes: 9490f01e2471 ("clk: scpi: add support for cpufreq virtual device") Reported-by: Michał Zegan <webczat_200@poczta.onet.pl> Cc: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Tested-by: Michał Zegan <webczat_200@poczta.onet.pl> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09clk: qcom: Add GCC_MSS_RESET supportAvaneesh Kumar Dwivedi1-0/+1
Add support to use reset control framework for resetting MSS with hexagon v56 1.5.0. Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09clk: zte: add audio clocks for zx296718Jun Nie3-0/+275
The audio related clock support is missing from the existing zx296718 clock driver. Let's add it, so that the upstream ZX SPDIF driver can work for HDMI audio support. Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> [sboyd@codeaurora.org: Staticize some more structures] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09clk: zx296718: do not panic on failureShawn Guo1-9/+18
Instead of using panic, we should give an error message and return error code when of_clk_add_hw_provider() call fails. Since we have error prompt for failures, the "init over" pr_info output isn't really necessary but becomes a debug noise. So let's clean it up along the way. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09clk: wm831x: fix usleep_range with bad rangeNicholas Mc Guire1-1/+2
The delay here is not in atomic context and does not seem critical with respect to precision, but usleep_range(min,max) with min==max results in giving the timer subsystem no room to optimize uncritical delays. Fix this by setting the range to 2000,3000 us. Fixes: commit f05259a6ffa4 ("clk: wm831x: Add initial WM831x clock driver") Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org> Acked-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09clk: imx: pllv3: support fractional multiplier on vf610 PLL1/PLL2Nikita Yushchenko3-2/+102
On vf610, PLL1 and PLL2 have registers to configure fractional part of frequency multiplier. This patch adds support for these registers. This fixes "fast system clock" issue on boards where bootloader sets fractional multiplier for PLL1. Suggested-by: Andrey Smirnov <andrew.smirnov@gmail.com> CC: Chris Healy <cphealy@gmail.com> Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09clk/axs10x: Clear init field in driver probeJose Abreu1-0/+1
Init field must be cleared in driver probe as this structure is not dinamically allocated. If not, wrong flags can be passed to core. Signed-off-by: Jose Abreu <joabreu@synopsys.com> Cc: Carlos Palminha <palminha@synopsys.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org Fixes: 923587aafc2c ("clk/axs10x: Add I2S PLL clock driver") Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/040cc9afdfa0e95ce7a01c406ff427ef7dc0c0fd.1481540717.git.joabreu@synopsys.com
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