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2017-01-09Merge branches 'clk-qcom-rpm8974', 'clk-stm32f4', 'clk-ipq4019' and 'clk-fixes' into clk-nextStephen Boyd4-40/+1136
* clk-qcom-rpm8974: clk: qcom: smd-rpmcc: Add msm8974 clocks * clk-stm32f4: clk: stm32f4: SDIO & 48Mhz clock management for STM32F469 board clk: stm32f4: Add SAI clocks clk: stm32f4: Add I2S clock clk: stm32f4: Add lcd-tft clock clk: stm32f4: Add post divisor for I2S & SAI PLLs clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards clk: stm32f4: Update DT bindings documentation * clk-ipq4019: clk: qcom: ipq4019: Add the cpu clock frequency change notifier clk: qcom: ipq4019: Add all the frequencies for apss cpu clk: qcom: ipq4019: correct sdcc frequency and parent name clk: qcom: ipq4019: Add the nodes for pcnoc clk: qcom: ipq4019: Add the apss cpu pll divider clock node clk: qcom: ipq4019: remove fixed clocks and add pll clocks * clk-fixes: clk: stm32f4: Use CLK_OF_DECLARE_DRIVER initialization method clk: renesas: mstp: Support 8-bit registers for r7s72100
2017-01-06Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linuxLinus Torvalds2-7/+24
Pull clk fixes from Stephen Boyd: "One fix for a broken driver on Renesas RZ/A1 SoCs with bootloaders that don't turn all the clks on and another fix for stm32f4 SoCs where we have multiple drivers attaching to the same DT node" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: stm32f4: Use CLK_OF_DECLARE_DRIVER initialization method clk: renesas: mstp: Support 8-bit registers for r7s72100
2017-01-06clk: rockchip: Remove useless init of "grf" to -EPROBE_DEFERDouglas Anderson1-1/+0
When we used to defer setting the "grf" member to rockchip_clk_get_grf() it was important to init the "grf" member to an error value in rockchip_clk_init(). With recent changes, we now set "grf" right in rockchip_clk_init() (two lines below the place where we initted it). That makes the old init useless. Get rid of it. Fixes: 6f339dc2719e ("clk: rockchip: lookup General Register Files in rockchip_clk_init") Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-05clk: rockchip: add clock controller for rk3328Elaine Zhang3-0/+914
Add the clock tree definition for the new rk3328 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-02clk: sunxi-ng: A31: Fix spdif clock registerMarcus Cooper1-2/+2
As the SPDIF was rarely documented on the earlier Allwinner SoCs it was assumed that it had a similar clock register to the one described in the H3 User Manual. However this is not the case and it looks to shares the same setup as the I2S clock registers. Signed-off-by: Marcus Cooper <codekipper@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-02clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33Icenowy Zheng1-1/+1
The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to be changeable by changing the rate of PLL_CPUX. Add CLK_SET_RATE_PARENT flag to this clock. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-02clk: sunxi-ng: fix PLL_CPUX adjusting on A33Icenowy Zheng1-0/+10
When adjusting PLL_CPUX on A33, the PLL is temporarily driven too high, and the system hangs. Add a notifier to avoid this situation by temporarily switching to a known stable 24 MHz oscillator. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-02clk: sunxi-ng: fix PLL_CPUX adjusting on H3Ondrej Jirman1-0/+10
When adjusting PLL_CPUX on H3, the PLL is temporarily driven too high, and the system becomes unstable (oopses or hangs). Add a notifier to avoid this situation by temporarily switching to a known stable 24 MHz oscillator. Signed-off-by: Ondrej Jirman <megous@megous.com> Tested-by: Lutz Sammer <johns98@gmx.net> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-02clk: rockchip: add new pll-type for rk3328Elaine Zhang2-3/+14
The rk3328's pll and clock are similar with rk3036's, it different with pll_mode_mask, the rk3328 soc pll mode only one bit(rk3036 soc have two bits) so these should be independent and separate from the series of rk3328s. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-02clk: rockchip: describe aclk_vcodec using the new muxgrf type on rk3288Heiko Stuebner1-6/+5
With the newly introduced clk type for muxes in the grf we now can describe some missing clocks, like the aclk_vcodec that selects between aclk_vdpu and aclk_vepu based on a bit set in the general register files. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-02clk: rockchip: add a clock-type for muxes based in the grfHeiko Stuebner4-0/+131
Rockchip socs often have some tiny number of muxes not controlled from the core clock controller but through bits set in the general register files. Add a clock-type that can control these as well, so that we don't need to work around them being absent. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-12-29clk: samsung: exynos-audss: Replace syscore PM with platform device PMMarek Szyprowski1-14/+10
Exynos AUDSS clock driver has been already converted to platform driver, so remove the dependency on the syscore ops - the last remaining non-platform driver feature. Platform device's system sleep PM provides all needed infrastructure for replacing syscore-based PM, so do it now. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-12-29clk: samsung: exynos5433: Set NoC (Network On Chip) clocks as criticalChanwoo Choi1-4/+4
The ACLK_BUS0/1/2 are used for NoC (Network on Chip). If NoC's clocks are disabled, the system halt happens. Following clocks must be always enabled: - CLK_ACLK_BUS0_400 : NoC's bus clock for PERIC/PERIS/FSYS/MSCL, - CLK_ACLK_BUS1_400 : NoC's bus clock for MFC/HEVC/G3D, - CLK_ACLK_BUS2_400 : NoC's bus clock for GSCL/DISP/G2D/CAM0/CAM1/ISP. This patch also adds the CLK_SET_RATE_PARENT flag to the CLK_SCLK_JPEG_MSCL because this clock should be used for bus frequency scaling. This clock need to be changed on the fly with CLK_SET_RATE_PARENT flag. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-12-29clk: samsung: Add CPU clk configuration data for Exynos4412 PrimeBartlomiej Zolnierkiewicz1-0/+4
Add cpu clock configuration data for Exynos4412 Prime SoC (it supports additional PLL rates & CPU frequencies). Based on Hardkernel's kernel for ODROID-X2/U2/U3 boards. Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-12-27clk: qcom: ipq4019: Add the cpu clock frequency change notifierAbhishek Sahu1-1/+39
The current driver code gives the crash or gets hang while switching the CPU frequency some time. The APSS CPU Clock divider is not glitch free so it the APPS clock need to be switched for stable clock during the change. This patch adds the frequency change notifier for APSS CPU clock. It changes the parent of this clock to stable PLL FEPLL500 for PRE_RATE_CHANGE event. This event will be generated before actual clock set operations. The clock set operation will again change its corresponding parent by getting the same from frequency table. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> [sboyd@codeaurora.org: Indent less in probe] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-27clk: renesas: r8a7796: Add MSIOF controller clocksHiromitsu Yamasaki1-0/+5
This patch adds MSIOF{0,1,2,3} clocks for R8A7796 SoC. Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-12-27clk: renesas: r8a7796: Add CAN FD peripheral clockChris Paterson1-0/+1
Based on a patch for r8a7795 by Ramesh Shanmugasundaram. Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-12-27clk: renesas: r8a7796: Add CANFD clockChris Paterson1-0/+1
Based on a patch for r8a7795 by Ramesh Shanmugasundaram. Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-12-27clk: renesas: r8a7796: Add CAN peripheral clockChris Paterson1-0/+2
Based on a patch for r8a7795 by Ramesh Shanmugasundaram. Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-12-21clk: stm32f4: Use CLK_OF_DECLARE_DRIVER initialization methodGabriel Fernandez1-2/+2
Clock and reset controller use same compatible strings (same IP). Since commit 989eafd0b609 ("clk: core: Avoid double initialization of clocks") the OF core flags clock controllers registered with the CLK_OF_DECLARE() macro as OF_POPULATED, so platform devices with the same compatible string will not be registered. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-21clk: renesas: mstp: Support 8-bit registers for r7s72100Chris Brandt1-5/+22
The RZ/A1 is different than the other Renesas SOCs because the MSTP registers are 8-bit instead of 32-bit and if you try writing values as 32-bit nothing happens...meaning this driver never worked for r7s72100. Fixes: b6face404f38 ("ARM: shmobile: r7s72100: add essential clock nodes to dtsi") Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-21clk: stm32f4: SDIO & 48Mhz clock management for STM32F469 boardGabriel Fernandez1-3/+46
In the stm32f469 soc, the 48Mhz clock could be derived from pll-q or from pll-sai-p. The SDIO clock could be also derived from 48Mhz or from sys clock. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-21clk: stm32f4: Add SAI clocksGabriel Fernandez1-0/+16
This patch introduces SAI clocks for stm32f4 socs. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-21clk: stm32f4: Add I2S clockGabriel Fernandez1-1/+13
This patch introduces I2S clock for stm32f4 soc. The I2S clock could be derived from an external clock or from pll-i2s Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-21clk: stm32f4: Add lcd-tft clockGabriel Fernandez1-0/+114
This patch introduces lcd-tft clock for stm32f4 soc. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-21clk: stm32f4: Add post divisor for I2S & SAI PLLsGabriel Fernandez1-0/+55
This patch adds post dividers of I2S & SAI PLLs. These dividers are managed by a dedicated register (RCC_DCKCFGR). The PLL should be off before a set rate. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-21clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boardsGabriel Fernandez1-17/+334
This patch introduces PLL_I2S and PLL_SAI. Vco clock of these PLLs can be modify by DT (only n multiplicator, m divider is still fixed by the boot-loader). Each PLL has 3 dividers. PLL should be off when we modify the rate. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Acked-by: Rob Herring <robh@kernel.org> [sboyd@codeaurora.org: Mark stm32f4_pll_div_ops static] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-21clk: qcom: smd-rpmcc: Add msm8974 clocksBjorn Andersson1-0/+71
This adds all RPM based clocks for msm8974, except cxo and gfx3d_clk_src. Tested-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-21clk: qcom: ipq4019: Add all the frequencies for apss cpuAbhishek Sahu1-2/+12
The APSS CPU clock does not contain all the frequencies in its frequency table so this patch adds the same. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-21clk: qcom: ipq4019: correct sdcc frequency and parent nameAbhishek Sahu1-2/+2
1. The parent for sdcc clock is sdccpll. 2. The frequency value was wrong so modified the same. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-21clk: qcom: ipq4019: Add the nodes for pcnocAbhishek Sahu1-0/+39
The current ipq4019 clock driver does not have the node for PCNOC so this patch adds and registers the PCNOC clock nodes. This PCNOC clock is critical and should not be turned off so setting CRITICAL flag also. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-21clk: qcom: ipq4019: Add the apss cpu pll divider clock nodeAbhishek Sahu1-0/+132
The current ipq4019 clock driver does not have support for all the frequency supported by APSS CPU. APSS CPU frequency is provided with APSS CPU PLL divider which divides down the VCO frequency. This divider is nonlinear and specific to IPQ4019 so the standard divider code cannot be used for this. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-21clk: qcom: ipq4019: remove fixed clocks and add pll clocksAbhishek Sahu1-11/+243
The current ipq4019 clock driver registered the PLL clocks and dividers as fixed clock. These fixed clock needs to be removed from driver probe function and same need to be registered with clock framework. These PLL clocks should be programmed only once and the same are being programmed already by the boot loader so the set rate operation is not required for these clocks. Only the rate can be calculated by clock operations in clock driver file so this patch adds the same. The PLL takes the reference clock from XO and generates the intermediate VCO frequency. This VCO frequency will be divided down by different PLL internal dividers. Some of the PLL internal dividers are fixed while other are programmable. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-15Merge branch 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-armLinus Torvalds1-0/+8
Pull ARM updates from Russell King: - an update for clkdev registration error detection to simplify users - add cpu capacity parsing from DT - support for larger cachelines found on UniPhier caches - documentation for udelay constants - properly tag assembly function declarations - remove unnecessary indirection of asm/mach-types.h - switch to syscall table based generation to simplify future additions of system calls, along with correpsonding commit for pkey syscalls - remove redundant sa1101 header file - RONX protect modules when they're in the vmalloc region * 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm: ARM: mm: allow set_memory_*() to be used on the vmalloc region ARM: mm: fix set_memory_*() bounds checks ARM: 8631/1: clkdev: Detect errors in clk_hw_register_clkdev() for mass registration ARM: 8629/1: vfp: properly tag assembly function declarations in C code ARM: 8622/3: add sysfs cpu_capacity attribute ARM: 8621/3: parse cpu capacity-dmips-mhz from DT ARM: 8623/1: mm: add ARM_L1_CACHE_SHIFT_7 for UniPhier outer cache ARM: Update mach-types ARM: sa1100: remove SA-1101 header file ARM: 8619/1: udelay: document the various constants ARM: wire up new pkey syscalls ARM: convert to generated system call tables ARM: remove indirection of asm/mach-types.h
2016-12-15Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds1-1/+1
Pull ARM SoC platform updates from Arnd Bergmann: "These are updates for platform specific code on 32-bit ARM machines, essentially anything that can not (yet) be expressed using DT files. Noteworthy changes include: - Added support for the TI DRA71x family of SoCs in mach-omap2, this is an new variant of the the DRA72x/DRA74x automotive infotainment chips we already supported for a while. - Added support for the ST STM32F746 SoC, the first Cortex-M7 based microcontroller we support, related to the smaller STM32F4 family. - Renesas adds support for r8a7743 and r8a7745 in mach-shmobile, see http://elinux.org/RZ-G - SMP is now supported on the OX820 platform - A lot of code in mach-omap2 gets removed as a follow-up to removing support for board files in the previous release - Davinci has some new work to improve USB support - For i.MX, the performance monitor now supports profiling the memory controller using 'perf'" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (95 commits) ARM: davinci: da830-evm: use gpio descriptor for mmc pins ARM: davinci: da850-evm: use gpio descriptor for mmc pins ARM: davinci: hawk: use gpio descriptor for mmc pins ARM: ARTPEC-6: add select MFD_SYSCON to MACH_ARTPEC6 ARM: davinci: da8xx: Fix ohci device name ARM: oxnas: Add OX820 config and makefile entry ARM: oxnas: Add OX820 SMP support ARM: davinci: PM: fix build when da850 not compiled in ARM: orion5x: remove legacy support of ls-chl ARM: integrator: drop EBI access use syscon ARM: BCM5301X: Add back handler ignoring external imprecise aborts ARM: davinci: PM: support da8xx DT platforms ARM: davinci: PM: cleanup: remove references to pdata ARM: davinci: PM: rework init, remove platform device ARM: Kconfig: Introduce MACH_STM32F746 flag ARM: mach-stm32: Add a new SOC - STM32F746 ARM: shmobile: document SK-RZG1E board ARM: shmobile: r8a7745: basic SoC support ARM: imx: mach-imx6ul: add imx6ull support ARM: zynq: Reserve correct amount of non-DMA RAM ...
2016-12-15Merge tag 'armsoc-fixes-nc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds1-26/+26
Pull ARM SoC non-urgent fixes from Arnd Bergmann: "As usual, we queue up a few fixes that don't seem urgent enough to go in through -rc, or that just came a little too late given their size. The zx fixes make the platform finally boot on real hardware, the davinci and imx31 get the DT support working better for some of the machines that are still normally used with classic board files. One tegra fix is important for new bootloader versions, but the bug has been around for a while without anyone noticing. The other changes are mostly cosmetic" * tag 'armsoc-fixes-nc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (22 commits) arm64: tegra: Add missing Smaug revision arm64: tegra: Add VDD_GPU regulator to Jetson TX1 arm64: dts: zte: clean up gic-v3 redistributor properties arm64: dts: zx: Fix gic GICR property bus: vexpress-config: fix device reference leak soc: ti: qmss: fix the case when !SMP ARM: lpc32xx: drop duplicate header device.h ARM: ixp4xx: drop duplicate header gpio.h ARM: socfpga: fix spelling mistake in error message ARM: dts: imx6q-cm-fx6: fix fec pinctrl ARM: dts: imx7d-pinfunc: fix UART pinmux defines ARM: dts: imx6qp: correct LDB clock inputs ARM: OMAP2+: pm-debug: Use seq_putc() in two functions ARM: OMAP2+: Remove the omapdss_early_init_of() function mfd: tps65217: Fix mismatched interrupt number ARM: zx: Fix error handling ARM: spear: Fix error handling ARM: davinci: da850: Fix pwm name matching ARM: clk: imx31: properly init clocks for machines with DT clk: imx31: fix rewritten input argument of mx31_clocks_init() ...
2016-12-12clk: bcm: Fix 'maybe-uninitialized' warning in bcm2835_clock_choose_div_and_prate()Boris Brezillon1-1/+1
best_rate is reported as potentially uninitialized by gcc. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Fixes: 155e8b3b0ee3 ("clk: bcm: Support rate change propagation on bcm2835 clocks") Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-08clk: add devm_get_clk_from_child() APIKuninori Morimoto1-0/+21
Some driver is using this type of DT bindings for clock (more detail, see ${LINUX}/Documentation/devicetree/bindings/sound/simple-card.txt). sound_soc { ... cpu { clocks = <&xxx>; ... }; codec { clocks = <&xxx>; ... }; }; Current driver in this case uses of_clk_get() for each node, but there is no devm_of_clk_get() today. OTOH, the problem of having devm_of_clk_get() is that it encourages the use of of_clk_get() when clk_get() is more desirable. Thus, this patch adds new devm_get_clk_from_chile() which explicitly reads as get a clock from a child node of this device. By this function, we can also use this type of DT bindings sound_soc { clocks = <&xxx>, <&xxx>; clock-names = "cpu", "codec"; clock-ranges; ... cpu { ... }; codec { ... }; }; Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> [sboyd@codeurora.org: Rename subject to clk + add API] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-08clk: st: clk-flexgen: Unmap region obtained by of_iomapArvind Yadav1-1/+4
Free memory mapping, if probe is not successful. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-08clk: keystone: pll: Unmap region obtained by of_iomapArvind Yadav1-2/+7
Free memory mapping, if of_pll_div_clk_init is not successful. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-08clk:mmp:clk-of-mmp2: Free memory and Unmap region obtained by kzalloc and of_iomapArvind Yadav1-3/+12
Free memory and memory mapping , if mmp2_clk_init is not successful. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> [sboyd@codeaurora.org: Put return at the right place] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-08clk:mmp:clk-of-pxa910: Free memory and Unmap region obtained by kzmalloc and of_iomapArvind Yadav1-4/+15
Free memory and memory mapping , if pxa910_clk_init is not successful. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-08clk: mmp: clk-of-pxa1928: Free memory obtained by kzallocArvind Yadav1-0/+3
Free memory, if init is not successful. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-08clk: cdce925: Fix limit checkChristophe JAILLET1-1/+1
It is likely that instead of '1>64', 'q>64' was expected. Moreover, according to datasheet, http://www.ti.com/lit/ds/symlink/cdce925.pdf SCAS847I - JULY 2007 - REVISED OCTOBER 2016 PLL settings limits are: 16 <= q <= 63 So change the upper limit check from 64 to 63. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-08clk: bcm: Make COMMON_CLK_IPROC into a libraryStephen Boyd1-11/+5
The broadcom clk driver Kconfig file selects and depends on the COMMON_CLK_IPROC config for different SoC specific drivers. Let's simplify this by always selecting the COMMON_CLK_IPROC config, turning it into a set of library code. We still want to retain the SoC specific options, so we leave those in place. Since we're here we also drop COMMON_CLK dependency because that's implicitly handled by including this file in drivers/clk/Kconfig in the right place and also make CLK_BCM_KONA default to y on the architecture it exists for instead of plain default y. Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Ray Jui <ray.jui@broadcom.com> Cc: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-08clk: qoriq: added ls1012a clock configurationTang Yuantian1-0/+19
Acked-by: Scott Wood <oss@buserror.net> Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> [sboyd@codeaurora.org: Sorted list] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-08clk: ti: dra7: fix "failed to lookup clock node gmac_gmii_ref_clk_div" boot messageGrygorii Strashko1-1/+0
Prevent creating clk alias for non existing gmac_gmii_ref_clk_div clock and, this way, eliminate excessive error message during boot: "ti_dt_clocks_register: failed to lookup clock node gmac_gmii_ref_clk_div" Fixes: c097338ebd3f ("ARM: dts: dra7: cpsw: fix clocks tree") Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-08clk: bcm: Allow rate change propagation to PLLH_AUX on VEC clockBoris Brezillon1-1/+6
The VEC clock requires needs to be set at exactly 108MHz. Allow rate change propagation on PLLH_AUX to match this requirement wihtout impacting other IPs (PLLH is currently only used by the HDMI encoder, which cannot be enabled when the VEC encoder is enabled). Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-08clk: bcm: Support rate change propagation on bcm2835 clocksBoris Brezillon1-4/+63
Some peripheral clocks, like the VEC (Video EnCoder) clock need to be set to a precise rate (in our case 108MHz). With the current implementation, where peripheral clocks are not allowed to forward rate change requests to their parents, it is impossible to match this requirement unless the bootloader has configured things correctly, or a specific rate has been assigned through the DT (with the assigned-clk-rates property). Add a new field to struct bcm2835_clock_data to specify which parent clocks accept rate change propagation, and support set rate propagation in bcm2835_clock_determine_rate(). Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-08clk: bcm2835: Avoid overwriting the div info when disabling a pll_div clkBoris Brezillon1-1/+3
bcm2835_pll_divider_off() is resetting the divider field in the A2W reg to zero when disabling the clock. Make sure we preserve this value by reading the previous a2w_reg value first and ORing the result with A2W_PLL_CHANNEL_DISABLE. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks") Cc: <stable@vger.kernel.org> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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