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2016-08-12clk: fixed-factor: Convert into a module platform driverRicardo Ribalda Delgado1-8/+65
Adds support for fixed-factor clock providers which have not been enabled via of_clk_init(). This is required by Device trees overlays that introduce clocks providers. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> [sboyd@codeaurora.org: Make new private function static, don't check clk for NULL when unregistering in driver remove] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-12clk: core: Avoid double initialization of clocksRicardo Ribalda Delgado1-0/+4
Some clock providers can be initialized via of_clk_init() and also via platform device probe. Avoid double initialization of them by setting the OF_POPULATED flag. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-12clk: sunxi: apb0: Use new macro CLK_OF_DECLARE_DRIVERRicardo Ribalda Delgado1-2/+2
This driver initializes a clock provider via sun8i_a23_apb0_setup and then continues the initialization on sun8i_a23_apb0_clk_probe. Use the new macro to notify the clk subsystem about this behaviour. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-12clk: sunxi: mod0: Use new macro CLK_OF_DECLARE_DRIVERRicardo Ribalda Delgado1-1/+2
This driver initializes a clock provider via sun4i_a10_mod0_setup and then continues the initialization on sun4i_a10_mod0_clk_probe. Use the new macro to notify the clk subsystem about this behaviour. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-12clk: nxp: Use new macro CLK_OF_DECLARE_DRIVERRicardo Ribalda Delgado1-1/+2
This driver initializes a clock provider via lpc18xx_creg_clk_init and then continues the initialization on lpc18xx_creg_clk_probe. Use the new macro to notify the clk subsystem about this behaviour. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> [sboyd@codeaurora.org: s/npx/nxp/ in subject] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-12clk: axis: Use new macro CLK_OF_DECLARE_DRIVERRicardo Ribalda Delgado1-2/+2
This driver initializes a clock provider via of_artpec6_clkctrl_setup and then continues the initialization on artpec6_clkctrl_probe. Use the new macro to notify the clk subsystem about this behaviour. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-12clk: divider: Fix clk_divider_round_rate() to use clk_readl()Geert Uytterhoeven1-1/+1
clk-divider uses clk_readl()/clk_writel() everywhere, except in clk_divider_round_rate(), where plain readl() is used. Change this to clk_readl(), as it makes a difference on powerpc. Fixes: e6d5e7d90be92cee ("clk-divider: Fix READ_ONLY when divider > 1") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-12clk: rockchip: fix incorrect GATE bits for {c, g}pll_aclk_perihp_src on rk3399Xing Zheng1-2/+2
Sorry to refer incorrect clock diagram, we double check it that the bits configuration of the Xpll_aclk_perihp_src need to be fixed: bit 1 - shows aclk_perihp_cpll_src_en bit 0 - shows aclk_perihp_gpll_src_en Through the testing that plug/unplug the USB ethernet cable on the RK3399 kevin board. 1. the hclk_host0 and hclk_host1 are endpoint clocks: cpll --> G5[1] --> aclk_perihp_cpll_src --\ |--> hclk_host0 | --> ... ---> | gpll --> G5[0] --> aclk_perihp_gpll_src --/ |--> hclk_host1 2. there is no clock below the cpll_aclk_perihp_src, and the hclk_hostX are below the gpll_aclk_perihp_src: pll_cpll 1 1 800000000 0 0 cpll 7 19 800000000 0 0 cpll_aclk_perihp_src 0 0 800000000 0 0 ... pll_gpll 1 1 594000000 0 0 gpll 10 10 594000000 0 0 gpll_aclk_perihp_src 2 2 594000000 0 0 hclk_perihp 5 5 74250000 0 0 hclk_host1_arb 2 2 74250000 0 0 hclk_host1 2 2 74250000 0 0 hclk_host0_arb 2 2 74250000 0 0 hclk_host0 2 2 74250000 0 0 3. by default, G5[0] and G5[1] are enabled: localhost ~ # mem r 0xff760314 0x000003e0 4. close the G5[1] (aclk_perihp_cpll_src), and plug/unplug USB ethernet cable, the DUT still works well: localhost ~ # mem w 0xff760314 0xffff03e2 localhost ~ # mem r 0xff760314 0x000003e2 plug/unplug, the work statue is ok 5. close the G5[0] (aclk_perihp_gpll_src), , and plug/unplug USB ethernet cable, the DUT will be crashed: localhost ~ # mem w 0xff760314 0xffff03e1 localhost ~ # mem r 0xff760314 0x000003e1 plug/unplug, the DUT is crashed Summary: bit 1 - shows aclk_perihp_cpll_src_en bit 0 - shows aclk_perihp_gpll_src_en Fixes: 3bd14ae9da91 ("clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src") Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> [here the clock-documentation in the manual was actually stating the wrong bits and thus only Xing's testing above revealed the issue] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-08-12clk: rockchip: fix incorrect aclk_emmc source gate bits on rk3399Xing Zheng1-2/+2
Dues to incorrect diagram, we need to fix incorrect bits for (c/g)pll_aclk_emmc_src: cpll_aclk_emmc_src --> G6[13] gpll_aclk_emmc_src --> G6[12] Fixes: 115510053e5e ("clk: rockchip: add clock controller for the RK3399") Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-08-11clk: imx7d: do not set the parent of IMX7D_ENET_AXI_ROOT_SRCFabio Estevam1-2/+0
Booting the kernel on a imx7s-warp leads to several warnings like these: [ 0.000000] ------------[ cut here ]------------ [ 0.000000] WARNING: CPU: 0 PID: 0 at kernel/locking/lockdep.c:3536 lock_release+0x2f8/0x330 [ 0.000000] releasing a pinned lock [ 0.000000] ------------[ cut here ]------------ [ 0.000000] WARNING: CPU: 0 PID: 0 at kernel/locking/lockdep.c:2722 trace_hardirqs_on_caller+0x1ac/0x1f4 [ 0.000000] DEBUG_LOCKS_WARN_ON(unlikely(early_boot_irqs_disabled)) [ 0.000000] ---[ end trace cb88537fdc8fa201 ]--- [ 0.000000] bad: scheduling from the idle thread! [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 4.7.0-rc7-next-20160715 #404 [ 0.000000] ------------[ cut here ]------------ [ 0.000000] WARNING: CPU: 0 PID: 0 at kernel/time/sched_clock.c:179 sched_clock_register+0x44/0x1f8 [ 0.000000] Modules linked in: [ 0.000591] ------------[ cut here ]------------ [ 0.000610] WARNING: CPU: 0 PID: 0 at kernel/time/sched_clock.c:179 sched_clock_register+0x44/0x1f8 [ 0.002084] ------------[ cut here ]------------ [ 0.002104] WARNING: CPU: 0 PID: 0 at init/main.c:576 start_kernel+0x258/0x3b0 [ 0.002114] Interrupts were enabled early This fix is along the same lines as 5e33ebff7edd ("clk: imx7d: do not set parent of ethernet time/ref clocks") and the explanation from that commit is: "The reason for the warning is that setting the parent enables the ENET PLL since we are using CLK_OPS_PARENT_ENABLE. Enabling the ENET PLL can cause clk_pllv3_wait_lock to sleep. See also: commit fc8726a2c021 ("clk: core: support clocks which requires parents enable (part 2)")." imx7s-warp does not even use the FEC interface, so we should not really configure the parent of IMX7D_ENET_AXI_ROOT_SRC in the common MX7 clock driver code. The dts file should use the assigned-clocks/assigned-clock-parents method, so simply remove the configuration of IMX7D_ENET_AXI_ROOT_SRC parent. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-11clk: migrate ref counts when orphans are reunitedMichael Turquette1-2/+10
It's always nice to see families reunited, and this is equally true when talking about parent clocks and their children. However, if the orphan clk had a positive prepare_count or enable_count, then we would not migrate those counts up the parent chain correctly. This has manifested with the recent critical clocks feature, which often enables clocks very early, before their parents have been registered. Fixed by replacing the call to clk_core_reparent with calls to __clk_set_parent_{before,after}. Cc: James Liao <jamesjj.liao@mediatek.com> Cc: Erin Lo <erin.lo@mediatek.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> [sboyd@codeaurora.org: Recalc accuracies and rates too] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-11clk: renesas: r8a7795: Fix SD clocksYoshihiro Shimoda1-4/+5
According to the datasheet, SDn clocks are from the SDSRC clock. And the SDSRC has a 1/2 divider. So, we should have ".sdsrc" as an internal core clock. Otherwise, since the sdhi driver will calculate clock for a sd card using the wrong parent clock rate, and then performance will be not good. Fixes: 90c073e53909da85 ("clk: shmobile: r8a7795: Add SD divider support") Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: stable@vger.kernel.org Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-12clk: rockchip: mark rk3399 hdcp_noc and vio_noc as criticalChris Zhong1-0/+4
The aclk_vio_noc should be put into critical list, as the interconnect is not handled right now, but is required by VOP. And the Type-C DP need these clocks: aclk_hdcp_noc, hclk_hdcp_noc, pclk_hdcp_noc. Mark them as critical to avoid someone close them. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Reviewed-by: Guenter Roeck <groeck@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-08-11clk: rockchip: fix rk3399 aclk_vio gate bitChris Zhong1-1/+1
Fix incorrect rk3399 aclk_vio gating bit, it should be 0, not 10. Fixes: 115510053e5e ("clk: rockchip: add clock controller for the RK3399") Signed-off-by: Chris Zhong <zyw@rock-chips.com> Reviewed-by: Xing Zheng <zhengxing@rock-chips.com> Reviewed-by: Guenter Roeck <groeck@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-08-10clk: sunxi-ng: Fix inverted test condition in ccu_helper_wait_for_lockChen-Yu Tsai1-1/+1
The condition passed to read*_poll_timeout() is the break condition, i.e. wait for this condition to happen and return success. The original code assumed the opposite, resulting in a warning when the PLL clock rate was changed but never lost it's lock as far as the readout indicated. This was verified by checking the read out register value. Fixes: 1d80c14248d6 ("clk: sunxi-ng: Add common infrastructure") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-09ARM: i.MX: Remove i.MX1 non-DT supportAlexander Shiyan1-41/+5
This patch removes registration helpers and support files, used for non-DT i.MX1 targets. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-08-09clk: renesas: r8a7796: Add watchdog module clockGeert Uytterhoeven1-0/+1
Add the module clock for the Watchdog Timer (WDT) controller on the Renesas R-Car M3-W (r8a7796) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-08-09clk: renesas: r8a7796: Add watchdog core clocksGeert Uytterhoeven1-0/+6
Add all core clocks related to the Watchdog Timer (WDT) controller on the Renesas R-Car M3-W (r8a7796) SoC: OSC, Internal RCLK, and RCLK. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-08-08clk: sunxi-ng: nkm: Add mux to support multiple parentsChen-Yu Tsai2-6/+57
The MIPI mode of the MIPI-PLL on A31 is an NKM-style PLL with 2 selectable parents. Add mux support to the NKM clock. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-08-08clk: sunxi-ng: mux: Increase fixed pre-divider div sizeChen-Yu Tsai2-2/+2
Some clocks have a predivider value that is larger than what u8 can store. One such example is the OUT clk found on A20/A31, which has a /750 pre-divider on one of the osc24M parents. Increase the size of the div field to u16. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-08-08clk: sunxi-ng: nk: Make ccu_nk_find_best staticChen-Yu Tsai1-3/+3
make C=2 reports: CHECK drivers/clk/sunxi-ng/ccu_nk.c drivers/clk/sunxi-ng/ccu_nk.c:17:6: warning: symbol 'ccu_nk_find_best' was not declared. Should it be static? ccu_nk_find_best is only used within ccu_nk.c. So make it static to get rid of this warning. Fixes: adbfb0056e03 ("clk: sunxi-ng: Add N-K-factor clock support") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-08-08clk: sunxi-ng: Fix inverted test condition in ccu_helper_wait_for_lockChen-Yu Tsai1-1/+1
The condition passed to read*_poll_timeout() is the break condition, i.e. wait for this condition to happen and return success. The original code assumed the opposite, resulting in a warning when the PLL clock rate was changed but never lost it's lock as far as the readout indicated. This was verified by checking the read out register value. Fixes: 1d80c14248d6 ("clk: sunxi-ng: Add common infrastructure") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-08-08clk: sunxi: Fix return value check in sun8i_a23_mbus_setup()Wei Yongjun1-1/+1
In case of error, the function of_io_request_and_map() returns ERR_PTR() and never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-08-08clk: sunxi: pll2: Fix return value check in sun4i_pll2_setup()Wei Yongjun1-2/+2
In case of error, the functions clk_register_composite() and clk_register_divider() returns ERR_PTR() and never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-08-08clk: rockchip: use general clock flag when registering pllHeiko Stübner3-4/+4
Add the general flags the pll list already contains to the clock init, so that needed clock flags can be used for plls. Signed-off-by: Heiko Stübner <heiko@sntech.de>
2016-08-08clk: rockchip: delete the CLK_IGNORE_UNUSED from aclk_pcie on rk3399Elaine Zhang1-2/+2
allow aclk_pcie and aclk_perf_pcie disabled when unused. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-08-08clk: rockchip: add 65MHz and 106.5MHz rates to rk3399 plls used for HDMIXing Zheng1-0/+2
We need to add more clocks for supporting more display resolution for HDMI. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-08-02treewide: replace obsolete _refok by __refFabian Frederick1-2/+2
There was only one use of __initdata_refok and __exit_refok __init_refok was used 46 times against 82 for __ref. Those definitions are obsolete since commit 312b1485fb50 ("Introduce new section reference annotations tags: __ref, __refdata, __refconst") This patch removes the following compatibility definitions and replaces them treewide. /* compatibility defines */ #define __init_refok __ref #define __initdata_refok __refdata #define __exit_refok __ref I can also provide separate patches if necessary. (One patch per tree and check in 1 month or 2 to remove old definitions) [akpm@linux-foundation.org: coding-style fixes] Link: http://lkml.kernel.org/r/1466796271-3043-1-git-send-email-fabf@skynet.be Signed-off-by: Fabian Frederick <fabf@skynet.be> Cc: Ingo Molnar <mingo@redhat.com> Cc: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2016-08-01Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds1-0/+1
Pull ARM DT updates from Olof Johansson: "Device tree contents continue to be the largest branches we submit. This time around, some of the contents worth pointing out is: New SoC platforms: - Freescale i.MX 7Solo - Broadcom BCM23550 - Cirrus Logic EP7209 and EP7211 (clps711x platforms)_ - Hisilicon HI3519 - Renesas R8A7792 Some of the other delta that is sticking out, line-count wise: - Exynos moves of IP blocks under an SoC bus, which causes a large delta due to indentation changes - a new Tegra K1 board: Apalis - a bunch of small updates to many Allwinner platforms; new hardware support, some cleanup, etc" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (426 commits) ARM: dts: sun8i: Add dts file for inet86dz board ARM: dts: sun8i: Add dts file for Polaroid MID2407PXE03 tablet ARM: dts: sun8i: Use sun8i-reference-design-tablet for ga10h dts ARM: dts: sun8i: Use sun8i-reference-design-tablet for polaroid mid2809pxe04 ARM: dts: sun8i: reference-design-tablet: Add drivevbus-supply ARM: dts: Copy sun8i-q8-common.dtsi sun8i-reference-design-tablet.dtsi ARM: dts: sun5i: Use sun5i-reference-design-tablet.dtsi for utoo p66 dts ARM: dts: sun5i: Use sun5i-reference-design-tablet.dtsi for dit4350 dts ARM: dts: sun5i: reference-design-tablet: Remove mention of q8 ARM: dts: sun5i: reference-design-tablet: Set lradc vref to avcc ARM: dts: sun5i: Rename sun5i-q8-common.dtsi sun5i-reference-design-tablet.dtsi ARM: dts: sun5i: Move q8 display bits to sun5i-a13-q8-tablet.dts ARM: dts: sunxi: Rename sunxi-q8-common.dtsi sunxi-reference-design-tablet.dtsi ARM: dts: at91: Don't build unnecessary dtbs ARM: dts: at91: sama5d3x: separate motherboard gmac and emac definitions ARM: dts: at91: at91sam9g25ek: fix isi endpoint node ARM: dts: at91: move isi definition to at91sam9g25ek ARM: dts: at91: fix i2c-gpio node name ARM: dts: at91: vinco: fix regulator name ARM: dts: at91: ariag25 : fix onewire node ...
2016-08-01Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds4-31/+7
Pull ARM SoC driver updates from Olof Johansson: "Driver updates for ARM SoCs. A slew of changes this release cycle. The reset driver tree, that we merge through arm-soc for historical reasons, is also sizable this time around. Among the changes: - clps711x: Treewide changes to compatible strings, merged here for simplicity. - Qualcomm: SCM firmware driver cleanups, move to platform driver - ux500: Major cleanups, removal of old mach-specific infrastructure. - Atmel external bus memory driver - Move of brcmstb platform to the rest of bcm - PMC driver updates for tegra, various fixes and improvements - Samsung platform driver updates to support 64-bit Exynos platforms - Reset controller cleanups moving to devm_reset_controller_register() APIs - Reset controller driver for Amlogic Meson - Reset controller driver for Hisilicon hi6220 - ARM SCPI power domain support" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (100 commits) ARM: ux500: consolidate base platform files ARM: ux500: move soc_id driver to drivers/soc ARM: ux500: call ux500_setup_id later ARM: ux500: consolidate soc_device code in id.c ARM: ux500: remove cpu_is_u* helpers ARM: ux500: use CLK_OF_DECLARE() ARM: ux500: move l2x0 init to .init_irq mfd: db8500 stop passing around platform data ASoC: ab8500-codec: remove platform data based probe ARM: ux500: move ab8500_regulator_plat_data into driver ARM: ux500: remove unused regulator data soc: raspberrypi-power: add CONFIG_OF dependency firmware: scpi: add CONFIG_OF dependency video: clps711x-fb: Changing the compatibility string to match with the smallest supported chip input: clps711x-keypad: Changing the compatibility string to match with the smallest supported chip pwm: clps711x: Changing the compatibility string to match with the smallest supported chip serial: clps711x: Changing the compatibility string to match with the smallest supported chip irqchip: clps711x: Changing the compatibility string to match with the smallest supported chip clocksource: clps711x: Changing the compatibility string to match with the smallest supported chip clk: clps711x: Changing the compatibility string to match with the smallest supported chip ...
2016-08-01Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds2-0/+9
Pull ARM SoC platform updates from Olof Johansson: "Improved and new platform support for various SoCs: New SoC support: - Broadcom BCM23550 - Freescale i.MX7Solo - Qualcomm MDM9615 - Renesas r8a7792 Improvements: - convert clps711x to multiplatform - debug uart improvements for Atmel platforms - Tango platform improvements: HOTPLUG_CPU, Suspend-to-ram - OMAP tweaks and improvements to hwmod - OMAP support for kexec on SMP" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (109 commits) ARM: davinci: fix build break because of undeclared dm365_evm_snd_data ARM: s3c64xx: smartq: Avoid sparse warnings ARM: sti: Implement dummy L2 cache's write_sec ARM: STi: Update machine _namestr to be more generic. arm: meson: explicitly select clk drivers ARM: tango: add Suspend-to-RAM support ARM: hisi: consolidate the hisilicon machine entries ARM: tango: fix CONFIG_HOTPLUG_CPU=n build MAINTAINERS: Update BCM281XX/BCM11XXX/BCM216XX entry MAINTAINERS: Update BCM63XX entry MAINTAINERS: Add NS2 entry MAINTAINERS: Fix nsp false-positives MAINTAINERS: Change L to M for Broadcom ARM/ARM64 SoC entries ARM: debug: Enable DEBUG_BCM_5301X for Northstar Plus SoCs ARM: clps711x: Switch to MULTIPLATFORM ARM: clps711x: Remove boards support ARM: clps711x: Add basic DT support ARM: clps711x: Reduce static map size ARM: SAMSUNG: Constify iomem address passed to s5p_init_cpu ARM: oxnas: Change OX810SE default driver config ...
2016-07-21Merge branch 'clk-fixes' into clk-nextMichael Turquette3-6/+5
2016-07-19clk: Makefile: re-sort and clean upMichael Turquette1-9/+11
Sorting is hard. Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-07-18clk: at91: fix clk_programmable_set_parent()Boris Brezillon1-1/+1
Since commit 1bdf02326b71e ("clk: at91: make use of syscon/regmap internally"), clk_programmable_set_parent() is always selecting the first parent (AKA slow_clk), no matter what's passed in the 'index' parameter. Fix that by initializing the pckr variable to the index value. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Reported-by: Hans Verkuil <hans.verkuil@cisco.com> Fixes: 1bdf02326b71e ("clk: at91: make use of syscon/regmap internally") Cc: <stable@vger.kernel.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1468828152-18389-1-git-send-email-boris.brezillon@free-electrons.com
2016-07-15Merge branch 'clk-s905' into clk-nextMichael Turquette1-1/+1
2016-07-15Revert "clk: gxbb: expose CLKID_MMC_PCLK"Michael Turquette1-1/+1
This reverts commit e16fb2e6355c1c1b41623af9e01ada196e2af098. Updated documentation from the chip vendor reveals that this clock is not required for correct operation of the MMC controller. As such, do not expose it to DT. Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-07-14Merge tag 'sti-late-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti into next/lateArnd Bergmann3-14/+27
Merge "STi late updates for v4.8" from Patrice Chotard: - Add STi DT critical clocks declaration - Remove SPI hack wich has dependecy with critical clocks These 2 STi DT patches and SPI hack MUST be applied after patches contained into Stephen Boyd's branch clk-next/clk-st-critical. This to ensure not to break SPI. * tag 'sti-late-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti: spi: st-ssc4: Remove 'no clocking' hack ARM: sti: stih410-clocks: Identify critical clocks ARM: sti: stih407-family: Supply defines for CLOCKGEN A0 clk: st: clkgen-pll: Detect critical clocks clk: st: clkgen-fsyn: Detect critical clocks clk: st: clk-flexgen: Detect critical clocks
2016-07-14Merge tag 'ux500-cleanup-bundle' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/driversArnd Bergmann3-30/+6
Merge "Ux500 cleanups from Arnd" from Linus Walleij: This is a set of cleanups for the Ux500 that reduce the number of machine-local files and boardfile-type data for regulators and ASoC. * tag 'ux500-cleanup-bundle' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: ARM: ux500: consolidate base platform files ARM: ux500: move soc_id driver to drivers/soc ARM: ux500: call ux500_setup_id later ARM: ux500: consolidate soc_device code in id.c ARM: ux500: remove cpu_is_u* helpers ARM: ux500: use CLK_OF_DECLARE() ARM: ux500: move l2x0 init to .init_irq mfd: db8500 stop passing around platform data ASoC: ab8500-codec: remove platform data based probe ARM: ux500: move ab8500_regulator_plat_data into driver ARM: ux500: remove unused regulator data
2016-07-13clk: samsung: Allow modular build of the Audio Subsystem CLKCON driverSylwester Nawrocki3-12/+11
Any clock dependencies can be properly handled with deferred probing so we can remove core_initcall and switch to a proper loadable platform driver module. This change has been tested on Exynos4412 Odroid U3 based board. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1467987300-31450-1-git-send-email-s.nawrocki@samsung.com
2016-07-13clk: samsung: make clk-s5pv210-audss explicitly non-modularPaul Gortmaker1-27/+2
The Kconfig currently controlling compilation of this code is: arch/arm/mach-s5pv210/Kconfig:config ARCH_S5PV210 arch/arm/mach-s5pv210/Kconfig: bool "Samsung S5PV210/S5PC110" if ARCH_MULTI_V7 ...meaning that it currently is not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the driver there is no doubt it is builtin-only. We explicitly disallow a driver unbind, since that doesn't have a sensible use case anyway, and it allows us to drop the ".remove" code for non-modular drivers. Since this code is already not using module_init, case, the init ordering remains unchanged with this commit. We also delete the MODULE_LICENSE tags etc. since all that information is already contained at the top of the file in the comments. Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-samsung-soc@vger.kernel.org Cc: linux-clk@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160704211220.5685-8-paul.gortmaker@windriver.com
2016-07-13clk: exynos5433: remove CLK_IGNORE_UNUSED flag from SPI clocksAndi Shyti1-3/+2
Because the Exynos5433 SPI driver supports the ioclk handling and the following patch: http://marc.info/?l=linux-kernel&m=146787645626318&w=2 fixes a synchronus abort issue, none of the SPI clocks require any critical handling: remove, then, the CLK_IGNORE_UNUSED flag for the SPI related clocks. Signed-off-by: Andi Shyti <andi.shyti@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1468317736-18841-8-git-send-email-andi.shyti@samsung.com
2016-07-12clk: oxnas: Add hardware dependenciesJean Delvare1-0/+1
The clk-oxnas driver is specific to its architecture, so do not propose it on other architectures, unless build-testing. Signed-off-by: Jean Delvare <jdelvare@suse.de> Cc: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160707091844.196a7930@endymion
2016-07-12clk: imx7d: do not set parent of ethernet time/ref clocksStefan Agner1-9/+0
All device trees currently in mainline specify the time clock parent using the assigned-clocks/assigned-clock-parents method, there is no need to statically assign the parent in the core clock driver. Also all current boards provide an Ethernet reference clock for the PHY externally, hence configuring the internal PHY reference clock. Furthermore, and the actual driver of this patch, specify ethernet related parents at that early point in boot leads to a warning: bad: scheduling from the idle thread! The reason for the warning is that setting the parent enables the ENET PLL since we are using CLK_OPS_PARENT_ENABLE. Enabling the ENET PLL can cause clk_pllv3_wait_lock to sleep. See also: commit fc8726a2c021 ("clk: core: support clocks which requires parents enable (part 2)"). Note that setting the ENET AXI root clock parent also requires ENET PLL to be enabled. However, U-Boot typically leaves the ENET PLL on, hence when the framework sets the parent of the first clock, it does not need to wait for the PLL to come up. But because there is currently no user of that clock, the PLL gets disabled after setting the parent. Therefore, subsequent reparenting calls of any clock which somehow rely on the ENET PLL, need to reenable the ENET PLL which leads to a sleep. Removing those subsequent reparenting calls works around this issue. Also remove comments. The code is really verbose enough. Signed-off-by: Stefan Agner <stefan@agner.ch> Tested-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160703174813.13970-1-stefan@agner.ch
2016-07-12ARM: ux500: use CLK_OF_DECLARE()Arnd Bergmann3-30/+6
The ux500 DT support predates the CLK_OF_DECLARE macro and calls directly into the clk driver from platform code. Converting this to CLK_OF_DECLARE makes the code much nicer and similar to how modern platforms do it today. It also removes the last user of cpu_is_u8500_family() etc. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-07-11Merge branch 'clk-sunxi-ng' into clk-nextMichael Turquette2-3/+3
2016-07-11clk: sunxi-ng: h3: Fix Kconfig symbol typoMaxime Ripard1-1/+1
The Kconfig symbol for the sun8i SoC family was mistyped. Fix that. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160711203448.18062-2-maxime.ripard@free-electrons.com
2016-07-11clk: sunxi-ng: h3: Fix audio clock divider offsetMaxime Ripard1-2/+2
The code had a typo and got the wrong offset for the hardcoded divider, fix that. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reported-by: Jean-Francois Moine <moinejf@free.fr> Reported-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160711203448.18062-1-maxime.ripard@free-electrons.com
2016-07-08Merge branch 'clk-sunxi-ng' into clk-nextMichael Turquette31-0/+3397
2016-07-08clk: sunxi-ng: Add H3 clocksMaxime Ripard4-0/+904
Add the list of clocks and resets found in the H3 CCU. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160629190535.11855-14-maxime.ripard@free-electrons.com
2016-07-08clk: sunxi-ng: Add N-K-M-P factor clockMaxime Ripard4-0/+244
Introduce support for clocks that use a combination of two linear multipliers (N and K factors), one linear divider (M) and one power of two divider (P). Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160629190535.11855-13-maxime.ripard@free-electrons.com
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