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2014-02-25clk: shmobile: div6: use proper description in kernel docWolfram Sang1-1/+1
These variable clocks have nothing to do with MSTP gating, probably a copy&paste leftover. Signed-off-by: Wolfram Sang <wsa@sang-engineering.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-24Merge branch 'clk-fixes' into clk-nextMike Turquette14-89/+107
2014-02-24clk: ti: am335x: remove unecessary cpu0 clk nodeNishanth Menon1-1/+0
cpu0 clock node has no functionality, since cpufreq-cpu0 is already capable of picking up the clock from dts. Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-24clk: Correct handling of NULL clk in __clk_{get, put}Sylwester Nawrocki1-6/+7
Ensure clk->kref is dereferenced only when clk is not NULL. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-24clk: return probe defer when DT clock not yet readyJean-Francois Moine2-1/+3
At probe time, a clock device may not be ready when some other device wants to use it. This patch lets the functions clk_get/devm_clk_get return a probe defer when the clock is defined in the DT but not yet available. Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-24clk: add pr_debug & kerneldoc around clk notifiersMike Turquette1-1/+4
Both the pr_err and the additional kerneldoc aim to help when debugging errors thrown from within a clock rate-change notifier callback. Reported-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-24Merge branch 'clk-tegra-more-fixes-3.14' of git://nv-tegra.nvidia.com/user/pdeschrijver/linux into clk-fixesMike Turquette7-31/+45
Fixes stray access to undefined registers, use of wrong clock parents & running clocks at wrong rates. All of these issues cause regressions in the form of boards that are unable to boot or crash and die horrible deaths.
2014-02-24clk: bcm281xx: don't disable unused peripheral clocksAlex Elder1-1/+1
Add the CLK_IGNORE_UNUSED flag when setting up a peripheral clock. This prevents unused clocks from getting disabled, and by doing this we can use the common clock code even before we've resolved all the spots that need to get a reference to their clock. Signed-off-by: Alex Elder <elder@linaro.org> Reviewed-by: Matt Porter <mporter@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Matt Porter <mporter@linaro.org>
2014-02-24clk: bcm281xx: add initial clock framework supportAlex Elder8-0/+2642
Add code for device tree support of clocks in the BCM281xx family of SoCs. Machines in this family use peripheral clocks implemented by "Kona" clock control units (CCUs). (Other Broadcom SoC families use Kona style CCUs as well, but support for them is not yet upstream.) A BCM281xx SoC has multiple CCUs, each of which manages a set of clocks on the SoC. A Kona peripheral clock is composite clock that may include a gate, a parent clock multiplexor, and zero, one or two dividers. There is a variety of gate types, and many gates implement hardware-managed gating (often called "auto-gating"). Most dividers divide their input clock signal by an integer value (one or more). There are also "fractional" dividers which allow division by non-integer values. To accomodate such dividers, clock rates and dividers are generally maintained by the code in "scaled" form, which allows integer and fractional dividers to be handled in a uniform way. If present, the gate for a Kona peripheral clock must be enabled when a change is made to its multiplexor or one of its dividers. Additionally, dividers and multiplexors have trigger registers which must be used whenever the divider value or selected parent clock is changed. The same trigger is often used for a divider and multiplexor, and a BCM281xx peripheral clock occasionally has two triggers. The gate, dividers, and parent clock selector are treated in this code as "components" of a peripheral clock. Their functionality is implemented directly--e.g. the common clock framework gate implementation is not used for a Kona peripheral clock gate. (This has being considered though, and the intention is to evolve this code to leverage common code as much as possible.) The source code is divided into three general portions: drivers/clk/bcm/clk-kona.h drivers/clk/bcm/clk-kona.c These implement the basic Kona clock functionality, including the clk_ops methods and various routines to manipulate registers and interpret their values. This includes some functions used to set clocks to a desired initial state (though this feature is only partially implemented here). drivers/clk/bcm/clk-kona-setup.c This contains generic run-time initialization code for data structures representing Kona CCUs and clocks. This encapsulates the clock structure initialization that can't be done statically. Note that there is a great deal of validity-checking code here, making explicit certain assumptions in the code. This is mostly useful for adding new clock definitions and could possibly be disabled for production use. drivers/clk/bcm/clk-bcm281xx.c This file defines the specific CCUs used by BCM281XX family SoCs, as well as the specific clocks implemented by each. It declares a device tree clock match entry for each CCU defined. include/dt-bindings/clock/bcm281xx.h This file defines the selector (index) values used to identify a particular clock provided by a CCU. It consists entirely of C preprocessor constants, to be used by both the C source and device tree source files. Signed-off-by: Alex Elder <elder@linaro.org> Reviewed-by: Tim Kryger <tim.kryger@linaro.org> Reviewed-by: Matt Porter <mporter@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Matt Porter <mporter@linaro.org>
2014-02-23Merge tag 'clk-mvebu-3xx-3.15' of git://git.infradead.org/linux-mvebu into clk-next-mvebuMike Turquette5-31/+461
clock: mvebu new SoC changes for v3.15 - mvebu (Armada 375/380/385) - extend corediv clock driver to support new SoCs - add core and gating clock drivers for new SoCs
2014-02-23clk: ux500: Staticize ux500_twocell_getSachin Kamat1-1/+2
ux500_twocell_get is a local symbol. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-23clk: tegra: Staticize tegra_clk_periph_no_gate_opsSachin Kamat1-1/+1
tegra_clk_periph_no_gate_ops is a local symbol. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-23clk: add clock-indices supportBen Dooks1-1/+19
Add a property called clock-indices to allow clock-output-names to be used where the index used to lookup a clock is not a 1:1 mapping to the array position in the clock-output-names Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-20clk: tegra124: remove gr2d and gr3d clocksPeter De Schrijver1-2/+0
Tegra124 does not have gr2d and gr3d clocks. They have been replaced by the vic03 and gpu clocks respectively. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2014-02-20clk: tegra: Fix vic03 mux indexPeter De Schrijver1-3/+1
The vic03 mux uses a linear mapping. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2014-02-18Merge branch 'for_3.14-rcx/clk-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into clk-fixesMike Turquette1-0/+1
2014-02-18Merge tag 'mvebu-clk-fixes-3.14' of git://git.infradead.org/linux-mvebu into clk-fixesMike Turquette4-50/+44
mvebu clock fixes for v3.14 - kirkwood, dove, armada-xp, armada-370 - force clock init order broken by sorting DT ocp nodes by address - fixes boot failures on affected platforms
2014-02-18clk: shmobile: rcar-gen2: Fix qspi divisorLaurent Pinchart1-1/+1
The qspi clock divisor is incorrectly set to twice the value it should have, possibly because it has been computed based on PLL1 as the clock parent instead of PLL1 / 2 (the datasheets specifies the qspi nominal frequencies, not the divisor values). Fix it. Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-18clk: shmobile: rcar-gen2: Fix clock parent all non-PLL clocksLaurent Pinchart1-1/+9
The lb, qspi, sdh, sd0 and sd1 clocks have the PLL1 (divided by 2) as their parent, not the main clock. Fix it. Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-18Merge tag 'socfpga-clk-for-3.15' of git://git.rocketboards.org/linux-socfpga-next into clk-nextMike Turquette6-314/+540
SOCFPGA clk updates for v3.15
2014-02-18clk: socfpga: Add a clk-phase property to the "altr,socfpga-gate-clk"Dinh Nguyen1-0/+68
The clk-phase property is used to represent the 2 clock phase values that is needed for the SD/MMC driver. Add a prepare function to the clk_ops, that will use the syscon driver to set sdmmc_clk's phase shift that is located in the system manager. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> --- v9: none v8: Use degrees in the clk-phase binding property v7: Add dts property to represent the clk phase of the sdmmc_clk. Add a prepare function to the gate clk that will toggle clock phase setting. Remove the "altr,socfpga-sdmmc-sdr-clk" clock type. v6: Add a new clock type "altr,socfpga-sdmmc-sdr-clk" that will be used to set the phase shift settings. v5: Use the "snps,dw-mshc" binding v4: Use the sdmmc_clk prepare function to set the phase shift settings v3: Not use the syscon driver because as of 3.13-rc1, the syscon driver is loaded after the clock driver. v2: Use the syscon driver
2014-02-18clk: socfpga: split clk codeSteffen Trumtrar6-306/+462
Move the different kinds of clocks into their own files. The reason is to aid readability of the code. This also goes along with the other SoC-specific clock drivers. The split introduces new structs for the three types of clocks and uses them. Other changes are not done to the code. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
2014-02-18clk: socfpga: fix define typoSteffen Trumtrar1-3/+3
It should be SOCFPGA instead of SOCFGPA. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
2014-02-18clk: socfpga: remove unused fieldSteffen Trumtrar1-1/+0
The clk_name field from the socfpga_clk struct is unused. Remove it. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
2014-02-18clk: socfpga: Remove socfpga_init_clocksDinh Nguyen1-10/+0
The only thing that socfpga_init_clocks was doing is setting up the smp_twd clk. Now that twd-timer's clock phandle is populated in the DTS, we can remove this function. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-02-18clk: socfpga: Look for the GPIO_DB_CLK by its offsetDinh Nguyen1-2/+3
After the patch: "clk: socfpga: Map the clk manager base address in the clock driver" The clk->name field in socfpga_clk_recalc_rate() was getting cleared. Replace looking for the GPIO_DB_CLK by its divider offset instead. Also rename the define SOCFPGA_DB_CLK_OFFSET -> SOCFPGA_GPIO_DB_CLK_OFFSET, as this represents the GPIO_DB_CLK. Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
2014-02-18clk: socfpga: Map the clk manager base address in the clock driverDinh Nguyen1-4/+16
The clk manager's base address was being mapped in SOCFPGA's arch code and being extern'ed out to the clock driver. This method is not correct, and the arch code was not really doing anything with that clk manager anyways. This patch moves the mapping of the clk manager's base address in the clock driver itself. Cleans up CLK_OF_DECLARE() into a single registration of all the clocks. Suggested-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Acked-by: Arnd Bergmann <arnd@arndb.de> --- v2: Use a static declaration for the clk_mgr_base_addr. Clean up the CLK_OF_DECLARE() as suggested by Arnd.
2014-02-18clk: Fix notifier documentationSoren Brinkmann1-12/+3
Contradicting to documenation, the notifier callbacks do receive the original clock rate in struct clk_notifier_data.old_rate and the new frequency struct clk_notifier_data.new_rate, independent of the notification reason. This behavior also seems to make more sense, since callbacks can use the same code to deterimine whether clocks are scaled up or down. Something which would not even possible in the post-rate-change case if the behavior was as documented. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-18clk: sunxi: Add new clock compatiblesMaxime Ripard1-15/+15
The Allwinner A10 compatibles were following a slightly different compatible patterns than the rest of the SoCs for historical reasons. Add compatibles matching the other pattern to the clock driver for consistency, and keep the older one for backward compatibility. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-02-18clk: sunxi: Add Allwinner A20/A31 GMAC clock unitChen-Yu Tsai1-0/+96
The Allwinner A20/A31 clock module controls the transmit clock source and interface type of the GMAC ethernet controller. Model this as a single clock for GMAC drivers to use. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-02-18clk: sunxi: Add support for PLL6 on the A31Maxime Ripard1-0/+45
The A31 has a slightly different PLL6 clock. Add support for this new clock in our driver. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-02-18clk: sunxi: Add USB clock register defintionsRoman Byshko1-0/+12
Add register definitions for the usb-clk register found on sun4i, sun5i and sun7i SoCs. Signed-off-by: Roman Byshko <rbyshko@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-02-18clk: sunxi: Add support for USB clock-register reset bitsHans de Goede1-0/+71
The usb-clk register is special in that it not only contains clk gate bits, but also has a few reset bits. This commit adds support for this by allowing gates type sunxi clks to also register a reset controller. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-02-17clk: tegra: use max divider if divider overflowsAndrew Bresticker1-1/+1
When requesting a rate less than the minimum clock rate for a divider, use the maximum divider value instead of bailing out with an error. This matches the behavior of the generic clock divider. Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17clk: tegra: cclk_lp has a pllx/2 dividerAndrew Bresticker1-1/+1
When pll_x is the parent of cclk_lp, PLLX_DIV2_BYPASS_LP determines whether cclk_lp output is divided by 2. Set TEGRA_DIVIDER_2 so that the clk_super driver is aware of this. Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17clk: tegra: fix sdmmc clks on Tegra1x4Andrew Bresticker4-8/+16
The sdmmc clocks on Tegra114 and Tegra124 are 3-bit wide muxes with 6 parents. Add support for tegra_clk_sdmmc*_8 and switch Tegra114 and Tegra124 to use these clocks instead. Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17clk: tegra: fix host1x clock on Tegra124Mark Zhang1-1/+1
The host1x clock on Tegra124 is a 3-bit wide mux with 6 parents. Change thte id to tegra_clk_host1x_8 so that the correct clock gets registered. Signed-off-by: Mark Zhang <markz@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17clk: tegra: PLLD2 fixes for hdmiDavid Ung1-8/+7
Set correct pll_d2_out0 divider and correct the p div values for pll_d2. Signed-off-by: David Ung <davidu@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17clk: tegra: Fix PLLD mnp tableRhyland Klein1-1/+10
PLLD was using the same mnp table as PLLP. Fix it to use its own table which is different from PLLP's. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17clk: tegra: Fix PLLP rate tableGabe Black1-5/+5
This table had settings for 216MHz, but PLLP is (and is supposed to be) configured at 408MHz. If that table is used and PLLP_BASE_OVRRIDE is not set, the kernel will panic in clk_pll_recalc_rate(). Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17clk: tegra: Correct clock number for UARTEThierry Reding1-1/+1
UARTE has clock number 66. Number 65 is the right one for UARTD. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-02-17clk: tegra: Add missing Tegra20 fuse clksPeter De Schrijver1-0/+2
Add clocks required for accessing fuses on Tegra20. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2014-02-17clk: mvebu: add clock support for Armada 380/385Gregory CLEMENT3-0/+172
Add the clock support for the new SoCs Armada 380 and Armada 385: core clocks and gating clocks. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-02-17clk: mvebu: add clock support for Armada 375Gregory CLEMENT3-0/+189
Add the clock support for the new SoC Armada 375: core clocks and gating clocks. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-02-17clk: mvebu: add Armada 375 support to the corediv clock driverThomas Petazzoni1-0/+19
This commit adds support for the Core Divider clocks of the Armada 375. Compared to Armada 370 and XP the Core Divider clocks of the 375 cannot be gated: only their ratio can be changed. This is reflected by the fact that the enable, disable and is_enabled clock operations are not defined, and that the enable_bit_offset field is also undefined. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-02-17clk: mvebu: refactor corediv driver to support more SoCThomas Petazzoni1-24/+57
This commit refactors the corediv clock driver so that it is capable of handling various SOCs that have slightly different corediv clock registers and capabilities. It introduces a clk_corediv_soc_desc structure that encapsulates all the SoC specific details. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-02-17clk: mvebu: add a little bit of documentation about data structuresThomas Petazzoni1-0/+17
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-02-17clk: mvebu: do not copy the contents of clk_corediv_descThomas Petazzoni1-8/+8
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-02-14clk: samsung: exynos4: Add remaining suspend/resume handlingTomasz Figa1-8/+68
As of now, part of Exynos4 clock suspend/resume handling is located in mach-exynos/pm.c, which is not where code accessing CMU registers should reside. This patch implements all the necessary suspend/resume handling code in Exynos4 clock driver to allow dropping that old code. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-02-14clk: samsung: Drop old suspend/resume codeTomasz Figa7-61/+7
Since all SoC drivers have been moved to local suspend/resume handling, the old code can be safely dropped. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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