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2013-12-30clk: samsung: exynos5250: Fix parents of gate clocks from GSCL domainTomasz Figa1-8/+17
This patch adds mout_aclk266_gscl_sub mux clock and adjusts definitions of GSCL domain gate clocks to use it as their parent, as specified in SoC documentation. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30clk: samsung: exynos5250: Make names of mux and div clocks consistentTomasz Figa1-117/+118
This patch renames all mux clocks to start with mout_ prefix and all div clocks to start with div_ prefix for consistency with other clocks already defined this way. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30clk: samsung: exynos5250: Sort definitions by registers and bitfieldTomasz Figa1-102/+188
This patch reorders clock definitions, so they are sorted by register addresses and bitfield shifts. When at it, blank lines are added to separate definitions of clocks from different registers. Overall this should make the driver more readable and reduce the number of potential conflicts when adding new entries. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30Merge branch 'samsung-fixes' into samsung-next-baseTomasz Figa3-11/+15
2013-12-30clk: exynos: File scope reg_save array should depend on PM_SLEEPKrzysztof Kozlowski1-5/+5
Move reg_save[] into CONFIG_PM_SLEEP dependency block as it is used only by suspend and resume functions. This fixes the warning on CONFIG_PM_SLEEP=n: drivers/clk/samsung/clk-exynos-audss.c:29:22: warning: ‘reg_save’ defined but not used [-Wunused-variable] Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clockAbhilash Kesavan1-1/+2
The sysreg (system register) generates control signals for various blocks like disp1blk, i2c, mipi, usb etc. However, it gets disabled as an unused clock at boot-up. This can lead to failures in operation of above blocks, because they can not be configured properly if this clock is disabled. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> [t.figa: Updated patch description.] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30clk: samsung: exynos5250: Add MDMA0 clocksAbhilash Kesavan1-1/+4
Adds gate clock for MDMA0 on Exynos5250 SoC. This is needed to ensure that the clock is enabled when MDMA0 is used on systems on which firmware gates the clockby default. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> [t.figa: Updated patch description.] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30clk: samsung: exynos5250: Fix ACP gate register offsetAbhilash Kesavan1-1/+1
The CLK_GATE_IP_ACP register offset is incorrectly listed making definition of g2d clock incorrect, which may lead to system failures when trying to use G2D on systems on which firmware gates this clock by default. Fix this and the register ordering as well. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> [t.figa: Updated patch description.] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30clk: exynos5250: fix sysmmu_mfc{l,r} gate clocksAndrew Bresticker1-2/+2
The gate clocks for the MFC sysmmus appear to be flipped, i.e. GATE_IP_MFC[2] gates sysmmu_mfcl and GATE_IP_MFC[1] gates sysmmu_mfcr. Fix this so that the MFC will start up. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2013-12-30clk: samsung: exynos4: Correct SRC_MFC registerSeung-Woo Kim1-1/+1
The SRC_MFC register offset was incorrect, which could cause have caused wrong calculation of rate of sclk_mfc clock, that could in turn lead to incorrect operation of MFC. This patch corrects it. Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> [t.figa: Updated patch description] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2013-12-29Merge tag 'sunxi-clk-3.14-for-mike' of https://bitbucket.org/emiliolopez/linux into clk-next-sunxiMike Turquette3-77/+437
Allwinner sunXi SoCs clock changes This contains the clk driver parts of the "[PATCH v3 00/13] clk: sunxi: add PLL5 and PLL6 support" series. It adds support for PLL4/5/6 and mod0 clocks on most sunxi platforms. Additionally, it contains "[PATCH 1/4] clk: sunxi: Allwinner A20 output clock support" (v2) from Chen-Yu Tsai, which adds support for output clocks present on A20.
2013-12-28clk: sunxi: Allwinner A20 output clock supportChen-Yu Tsai1-0/+57
This patch adds support for the external clock outputs on the Allwinner A20 SoC. The clock outputs are similar to "module 0" type clocks, with different offsets and widths for clock factors. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Emilio López <emilio@elopez.com.ar>
2013-12-28clk: sunxi: support better factor DT nodesEmilio López1-0/+9
The DT nodes should look like abc_clk: clk@deadbeef { ... clock-output-names = "abc"; } But our old DT nodes look like abc: abc@deadbeef { ... } So, let's support both formats, until we can transition everything to the new, correct one. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Mike Turquette <mturquette@linaro.org>
2013-12-28clk: sunxi: mod0 supportEmilio López1-0/+57
This commit implements support for the "module 0" type of clocks, as used by MMC, IR, NAND, SATA and other components. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Mike Turquette <mturquette@linaro.org>
2013-12-28clk: sunxi: add PLL5 and PLL6 supportEmilio López1-0/+230
This commit implements PLL5 and PLL6 support on the sunxi clock driver. These PLLs use a similar factor clock, but differ on their outputs. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Mike Turquette <mturquette@linaro.org>
2013-12-28clk: sunxi: make factors_clk_setup return the clock it registersEmilio López1-7/+8
We will be needing this to register a factor clock as parent with leaf divisors on a single call. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Mike Turquette <mturquette@linaro.org>
2013-12-28clk: sunxi: add gating support to PLL1Emilio López1-0/+2
This commit adds gating support to PLL1 on the clock driver. This makes the PLL1 implementation fully compatible with PLL4 as well. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org>
2013-12-28clk: sunxi: clean the magic number of mux parentsEmilio López1-2/+3
This was pointed out during the review of the factor patches. Let's indicate what does that magic 5 mean. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Mike Turquette <mturquette@linaro.org>
2013-12-28clk: sunxi: register factors clocks behind compositeEmilio López3-73/+76
This commit reworks factors clock registration to be done behind a composite clock. This allows us to additionally add a gate, mux or divisors, as it will be needed by some future PLLs. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org>
2013-12-27clk: remove CONFIG_COMMON_CLK_DEBUGMike Turquette2-11/+1
Populate ${DEBUGS_MOUNT_POINT}/clk if CONFIG_DEBUG_FS is set. This eliminates the extra (annoying) step of enabling the config option manually. Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-12-26clk: max77686: Remove redundant breakSachin Kamat1-2/+0
'break' after 'goto' is redundant. Remove it. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-12-26Merge branch 'tegra/dma-reset-rework' into next/dtOlof Johansson16-3070/+4715
Bringing in the tegra dma/reset framework cleanup as a base for the DT changes. * tegra/dma-reset-rework: (320 commits) spi: tegra: checking for ERR_PTR instead of NULL ASoC: tegra: update module reset list for Tegra124 clk: tegra: remove bogus PCIE_XCLK clk: tegra: remove legacy reset APIs ARM: tegra: remove legacy DMA entries from DT ARM: tegra: remove legacy clock entries from DT USB: EHCI: tegra: use reset framework Input: tegra-kbc - use reset framework serial: tegra: convert to standard DMA DT bindings serial: tegra: use reset framework spi: tegra: convert to standard DMA DT bindings spi: tegra: use reset framework staging: nvec: use reset framework i2c: tegra: use reset framework ASoC: tegra: convert to standard DMA DT bindings ASoC: tegra: allocate AHUB FIFO during probe() not startup() ASoC: tegra: call pm_runtime APIs around register accesses ASoC: tegra: use reset framework dma: tegra: register as an OF DMA controller dma: tegra: use reset framework ... Signed-off-by: Olof Johansson <olof@lixom.net>
2013-12-26Merge tag 'tegra-for-3.14-dmas-resets-rework' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/cleanupOlof Johansson8-82/+57
From Stephen Warren: ARM: tegra: implement common DMA and resets DT bindings This series converts the Tegra DTs and drivers to use the common/ standard DMA and reset bindings, rather than custom bindings. It also adds complete documentation for the Tegra clock bindings without actually changing any binding definitions. This conversion relies on a few sets of patches in branches from outside the Tegra tree: 1) A patch to add an DMA channel request API which allows deferred probe to be implemented. 2) A patch to implement a common part of the of_xlate function for DMA controllers. 3) Some ASoC patches (which in turn rely on (1) above), which support deferred probe during DMA channel allocation. 4) The Tegra clock driver changes for 3.14. Consequently, this branch is based on a merge of all of those external branches. In turn, this branch is or will be pulled into a few places that either rely on features introduced here, or would otherwise conflict with the patches: a) Tegra's own for-3.14/powergate and for-4.14/dt branches, to avoid conflicts. b) The DRM tree, which introduces new code that relies on the reset controller framework introduced in this branch, and to avoid conflicts. * tag 'tegra-for-3.14-dmas-resets-rework' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (30 commits) spi: tegra: checking for ERR_PTR instead of NULL ASoC: tegra: update module reset list for Tegra124 clk: tegra: remove bogus PCIE_XCLK clk: tegra: remove legacy reset APIs ARM: tegra: remove legacy DMA entries from DT ARM: tegra: remove legacy clock entries from DT USB: EHCI: tegra: use reset framework Input: tegra-kbc - use reset framework serial: tegra: convert to standard DMA DT bindings serial: tegra: use reset framework spi: tegra: convert to standard DMA DT bindings spi: tegra: use reset framework staging: nvec: use reset framework i2c: tegra: use reset framework ASoC: tegra: convert to standard DMA DT bindings ASoC: tegra: allocate AHUB FIFO during probe() not startup() ASoC: tegra: call pm_runtime APIs around register accesses ASoC: tegra: use reset framework dma: tegra: register as an OF DMA controller dma: tegra: use reset framework ... Signed-off-by: Olof Johansson <olof@lixom.net>
2013-12-26Merge branches 'depends/asoc-dma', 'depends/dma-of' and 'depends/tegra-clk' into next/cleanupOlof Johansson16-3003/+4673
Merging in external dependencies for the Tegra DMA and reset controller refactoring from external trees. Per Stephen Warren, the stability of these branches have been negotiated with the relevant parties (Vinod/Mark/Mike) * depends/asoc-dma: ASoC: dmaengine: fix deferred probe detection ASoC: dmaengine: support deferred probe for DMA channels dma: add channel request API that supports deferred probe ASoC: dmaengine: add custom DMA config to snd_dmaengine_pcm_config ASoC: don't leak on error in snd_dmaengine_pcm_register ASoC: restructure dmaengine_pcm_request_chan_of() ASoC: generic-dmaengine-pcm: Set BATCH flag when residue reporting is not supported ASoC: Add resource managed snd_dmaengine_pcm_register() * depends/dma-of: dma: add dma_get_any_slave_channel(), for use in of_xlate() * depends/tegra-clk: (42 commits) clk: tegra: fix __clk_lookup() return value checks clk: tegra: Do not print errors for clk_round_rate() clk: tegra: Initialize DSI low-power clocks clk: tegra: add FUSE clock device clk: tegra: Properly setup PWM clock on Tegra30 clk: tegra: Initialize secondary gr3d clock on Tegra30 clk: tegra114: Initialize clocks needed for HDMI clk: tegra124: add suspend/resume function for tegra_cpu_car_ops clk: tegra124: add wait_for_reset and disable_clock for tegra_cpu_car_ops clk: tegra124: Add support for Tegra124 clocks clk: tegra124: Add new peripheral clocks clk: tegra124: Add common clk IDs to clk-id.h clk: tegra: add TEGRA_PERIPH_NO_GATE clk: tegra: add locking to periph clks clk: tegra: Add periph regs bank X clk: tegra: Add support for PLLSS clk: tegra: move tegra20 to common infra clk: tegra: move tegra30 to common infra clk: tegra: introduce common gen4 super clock clk: tegra: move PMC, fixed clocks to common files ... Signed-off-by: Olof Johansson <olof@lixom.net>
2013-12-23Merge tag 'samsung-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dtOlof Johansson1-1/+2
From Kukjin Kim: Samsung DT 2nd updates for v3.14 - add DMA controller, SPI, and TMU DT nodes for exynos5420 - add PWM DT nodes for exynos5250 and exynos5420 - drop interrupt controller properties from MCT nodes because MCT is not an interrupt controller - move MCT nodes to exynos4x12 from board because it is a per-processor interrupt and same 4212 and 4412 - use one cell for MCT interrupt map for exynos4 SoCs - update Exynos MCT DT bindings accordingly - fix missing spaces after labels for exynos - fix mmc status property for exynos5250-snow - add MCLK for codec for exynos5250-smdk5250 - disable SPI and I2C by default for exynos5250 SoC and enable into requiring some boards - rename cros5250-common to exynos5250-cros-common * tag 'samsung-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (27 commits) ARM: dts: Rename Exynos5250 ChromeOS common file to have exynos prefix ARM: dts: Disable I2C controllers by default on Exynos5250 ARM: dts: Leave Exynos5250 SPI controller disabled by default ARM: dts: Add CODEC MCLK for SMDK5250 ARM: dts: Add device nodes for TMU blocks for exynos5420 ARM: dts: Fix status property of mmc nodes for snow board ARM: dts: Fix missing spaces after labels for exynos ARM: dts: Simplify MCT interrupt map for exynos4 SoCs ARM: dts: Move MCT node to exynos4x12.dtsi ARM: dts: Drop interrupt controller properties from MCT nodes for exynos4 SoCs Documentation: devicetree: Update Exynos MCT bindings description ARM: dts: add pwm DT nodes to Exynos5250 and Exynos5420 ARM: dts: Add SPI nodes to the exynos5420 device tree file ARM: dts: Add DMA controller node info on Exynos5420 ARM: dts: Use MSHC controller for eMMC memory for exynos4412-trats2 ARM: dts: Fix definition of MSHC device tree nodes for exynos4x12 ARM: dts: add clock provider for mshc node for Exynos4412 SOC clk: samsung: exynos4: Fix definition of div_mmc_pre4 divider ARM: dts: Fix exynos5250-snow's search key to be L_META ARM: dts: Add the missing "\" key in non-US keyboards for exynos5250-snow ... Signed-off-by: Olof Johansson <olof@lixom.net>
2013-12-22clk: add accuracy support for fixed clockBoris BREZILLON1-6/+37
This patch adds support for accuracy retrieval on fixed clocks. It also adds a new dt property called 'clock-accuracy' to define the clock accuracy. This can be usefull for oscillator (RC, crystal, ...) definitions which are always given an accuracy characteristic. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-12-22clk: add clk accuracy retrieval supportBoris BREZILLON1-7/+93
The clock accuracy is expressed in ppb (parts per billion) and represents the possible clock drift. Say you have a clock (e.g. an oscillator) which provides a fixed clock of 20MHz with an accuracy of +- 20Hz. This accuracy expressed in ppb is 20Hz/20MHz = 1000 ppb (or 1 ppm). Clock users may need the clock accuracy information in order to choose the best clock (the one with the best accuracy) across several available clocks. This patch adds clk accuracy retrieval support for common clk framework by means of a new function called clk_get_accuracy. This function returns the given clock accuracy expressed in ppb. In order to get the clock accuracy, this implementation adds one callback called recalc_accuracy to the clk_ops structure. This callback is given the parent clock accuracy (if the clock is not a root clock) and should recalculate the given clock accuracy. This callback is optional and may be implemented if the clock is not a perfect clock (accuracy != 0 ppb). Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-12-22clk: si570: Remove redundant of_match_ptr helperSachin Kamat1-1/+1
'clk_si570_of_match' is always compiled in. Hence the helper macro is not needed. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-12-22Merge tag 'renesas-clock-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into clk-next-shmobile2Mike Turquette2-1/+105
Renesas ARM based SoC Clock updates for v3.14 Add support for using emev2 SMU clocks with DT
2013-12-22Merge branch 'at91/dt' into next/driversOlof Johansson14-0/+3288
Merging at91/dt as a prereq for the at91/drivers code. * at91/dt: (43 commits) ARM: at91/at91rm9200ek.dts: rearrange nodes in address ascending order ARM: at91: dt: at91rm9200ek: add emac and nor flash support ARM: at91: add uart aliases to sama5d3 dtsi ARM: at91: add i2c2 pinctrl speficifation to sama5d3 DT ARM: at91: Animeo IP: fix mtd partition table ARM: at91: at91sam9g45: add i2c pinctrl ARM: at91: at91sam9g45: set default mmc pinctrl-names ARM: at91: sama5d3: enable qt1070 as a wakeup source ARM: at91: add support for Cosino board series by HCE Engineering ARM: at91/dt/sama5d3: add DMA information to SHA/AES/TDES nodes ARM: at91/dt/trivial: before sama5d3, Atmel MPU were using at91 prefix ARM: at91/dt/trivial: use macro for AES irq type ARM: at91: sam9263ek: add dt lcd support ARM: at91: at9sam9m10g45ek: add dt lcd support ARM: at91: sam9263: add fb dt support ARM: at91: sam9g45: add fb dt support ARM: at91/dt: binding: add missing compatibility string in SDRAM/DDR documentation ARM: at91/dt: binding: add precision to AIC documentation ARM: at91/dt: add atmel,pullup-gpio to at91rm9200ek usb1 definition ARM: at91/dt: add ethernet phy to at91rm9200ek board ...
2013-12-21clk: samsung: exynos4: Fix definition of div_mmc_pre4 dividerTomasz Figa1-1/+2
The clock was missing CLK_SET_RATE_PARENT flag, which caused rate setting failures due to inability of reconfiguration of second divider behind it. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-12-20Merge tag 'mvebu-clk-3.14' of git://git.infradead.org/linux-mvebu into clk-nextMike Turquette3-0/+229
mvebu clock changes for v3.14 - mvebu: add the core divider clock driver - sparse cleanup
2013-12-20clk/zynq/clkc: Add 'fclk-enable' featureSoren Brinkmann1-3/+15
In some use cases Zynq's FPGA clocks are used as static clock generators for IP in the FPGA part of the SOC for which no Linux driver exists and would control those clocks. To avoid automatic gating of these clocks in such cases a new property - fclk-enable - is added to the clock controller's DT description to accomodate such use cases. It's value is a bitmask, where a set bit results in enabling the corresponding FCLK through the clkc. FPGA clocks are handled following the rules below: If an FCLK is not enabled by bootloaders, that FCLK will be disabled in Linux. Drivers can enable and control it through the CCF as usual. If an FCLK is enabled by bootloaders AND the corresponding bit in the 'fclk-enable' DT property is set, that FCLK will be enabled by the clkc, resulting in an off by one reference count for that clock. Ensuring it will always be running. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-12-19clk: ux500: Remove extra semicolonSachin Kamat1-1/+1
Extra semicolon is redundant. Remove it. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-12-19clk: vt8500: Staticize vtwm_pll_opsSachin Kamat1-1/+1
'vtwm_pll_ops' is local to this file. Make it static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Cc: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-12-19clk: mvebu: Staticize of_cpu_clk_setupSachin Kamat1-1/+1
'of_cpu_clk_setup' is used only in this file. Make it static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-12-19clk: versatile: Staticize clk_sp810_timerclken_of_getSachin Kamat1-1/+1
clk_sp810_timerclken_of_get is used only in this file. Make it static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-12-19clk: socfpga: Use NULL instead of 0Sachin Kamat1-1/+1
'div_reg' is a pointer. Assign NULL instead of 0. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-12-19clk: tegra: Staticize tegra_clk_periph_nodiv_opsSachin Kamat1-1/+1
tegra_clk_periph_nodiv_ops is used only in this file. Make it static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-12-19clk: tegra: Staticize local variables in clk-pll.cSachin Kamat1-6/+6
Local variables used only in this file are made static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-12-19clk: SPEAr: Staticize clk_frac_opsSachin Kamat1-1/+1
clk_frac_ops is local to this file. Make it static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-12-19clk: at91: fix pmc_clk_ids data type attriubteBoris BREZILLON1-1/+1
Fix pmc_clk_ids data type attribute (__initdata -> __initconst). Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Reported-by: Fengguang Wu <fengguang.wu@intel.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2013-12-16mfd: s2mps11: Fix build after regmap field rename in sec-core.cKrzysztof Kozlowski1-3/+3
Fix building of s2mps11 regulator and clock drivers after renaming regmap field in struct sec_pmic_dev in commit: - "mfd/rtc: s5m: Fix register updating by adding regmap for RTC" Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Mark Brown <broonie@linaro.org>
2013-12-14clk: si570: Add a driver for SI570 oscillatorsSoren Brinkmann3-0/+542
Add a driver for SILabs 570, 571, 598, 599 programmable oscillators. The devices generate low-jitter clock signals and are reprogrammable via an I2C interface. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-12-14clk: Fix debugfs reparenting NULL pointer dereferenceStephen Boyd1-2/+1
Adding clocks from a kernel module can cause a NULL pointer dereference if the parent of a clock is added after the clock is added. This happens because __clk_init() iterates over the list of orphans and reparents the orphans to the clock being registered before creating the debugfs entry for the clock. Create the debugfs entry first before reparenting the orphans. Unable to handle kernel NULL pointer dereference at virtual address 00000028 pgd = ef3e4000 [00000028] *pgd=bf810831 Internal error: Oops: 17 [#1] PREEMPT SMP ARM Modules linked in: mmcc_8960(+) CPU: 0 PID: 52 Comm: modprobe Not tainted 3.12.0-rc2-00023-g1021a28-dirty #659 task: ef319200 ti: ef3a6000 task.ti: ef3a6000 PC is at lock_rename+0x24/0xc4 LR is at debugfs_rename+0x34/0x208 pc : [<c0317238>] lr : [<c047dfe4>] psr: 00000013 sp : ef3a7b88 ip : ef3a7ba8 fp : ef3a7ba4 r10: ef3d51cc r9 : ef3bc680 r8 : ef3d5210 r7 : ef3bc640 r6 : eee287e0 r5 : eee287e0 r4 : 00000000 r3 : ef3bc640 r2 : 00000000 r1 : eee287e0 r0 : 00000000 Flags: nzcv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user Control: 10c5787d Table: af3e406a DAC: 00000015 Process modprobe (pid: 52, stack limit = 0xef3a6240) Stack: (0xef3a7b88 to 0xef3a8000) 7b80: ef3bc640 ee4047e0 00000000 eee287e0 ef3a7bec ef3a7ba8 7ba0: c047dfe4 c0317220 ef3bc680 ef3d51cc ef3a7bdc ef3a7bc0 c06e29d0 c0268784 7bc0: c08946e8 ef3d5210 00000000 ef3bc700 ef3d5290 ef3d5210 ef3bc680 ef3d51cc 7be0: ef3a7c0c ef3a7bf0 c05b9e9c c047dfbc 00000000 00000000 ef3d5210 ef3d5290 7c00: ef3a7c24 ef3a7c10 c05baebc c05b9e30 00000001 00000001 ef3a7c64 ef3a7c28 7c20: c05bb124 c05bae9c bf000cd8 ef3bc7c0 000000d0 c0ff129c bf001774 00000002 7c40: ef3bc740 ef3d5290 ef0f9a10 bf001774 bf00042c 00000061 ef3a7c8c ef3a7c68 7c60: c05bb480 c05baed8 bf001774 ef3d5290 ef0f9a10 bf001774 ef38bc10 ef0f9a00 7c80: ef3a7cac ef3a7c90 c05bb5a8 c05bb3a0 bf001774 00000062 ef0f9a10 ef38bc18 7ca0: ef3a7cec ef3a7cb0 bf00010c c05bb56c 00000000 ef38ba00 00000000 ef3d60d0 7cc0: ef3a7cdc c0fefc24 ef0f9a10 c0a091c0 bf000d24 00000000 bf0029f0 bf006000 7ce0: ef3a7cfc ef3a7cf0 c05156c0 bf000040 ef3a7d2c ef3a7d00 c0513f5c c05156a8 7d00: ef3a7d2c ef0f9a10 ef0f9a10 bf000d24 ef0f9a44 c09ca588 00000000 bf006000 7d20: ef3a7d4c ef3a7d30 c05142b8 c0513ecc ef0fd25c 00000000 bf000d24 c0514214 7d40: ef3a7d74 ef3a7d50 c0512030 c0514220 ef0050a8 ef0fd250 ef0050f8 bf000d24 7d60: ef37c100 c09ed150 ef3a7d84 ef3a7d78 c05139c8 c0511fd8 ef3a7 7d80: c051344c c05139a8 bf000864 c09ca588 ef3a7db4 bf000d24 bf002 7da0: c09ca588 00000000 ef3a7dcc ef3a7db8 c05149dc c0513360 ef3a7 7dc0: ef3a7ddc ef3a7dd0 c0515914 c0514960 ef3a7dec ef3a7de0 bf006 7de0: ef3a7e74 ef3a7df0 c0208800 bf00600c ef3a7e1c ef3a7e00 c04c5 7e00: ffffffff c09d46c4 00000000 bf0029a8 ef3a7e34 ef3a7e20 c024c 7e20: ffffffff c09d46c4 ef3a7e5c ef3a7e38 c024e2fc c024ce40 00000 7e40: ef3a7f48 bf0029b4 bf0029a8 271aeb1c ef3a7f48 bf0029a8 00000001 ef383c00 7e60: bf0029f0 00000001 ef3a7f3c ef3a7e78 c028fac4 c0208718 bf0029b4 00007fff 7e80: c028cd58 000000d2 f0065000 00000000 ef3a7ebc 00000000 00000000 bf0029b4 7ea0: 00000000 bf0029ac bf0029b4 ef3a6000 ef3a7efc c08bf128 00000000 00000000 7ec0: 00000000 00000000 00000000 00000000 6e72656b 00006c65 00000000 00000000 7ee0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 7f00: 00000000 00000000 00000000 271aeb1c ef3a7f2c 00016376 b6f38008 001d3774 7f20: 00000080 c020f968 ef3a6000 00000000 ef3a7fa4 ef3a7f40 c02904dc c028e178 7f40: c020f898 010ccfa8 f0065000 00016376 f0073f60 f0073d7d f007a1e8 00002b24 7f60: 000039e4 00000000 00000000 00000000 0000002f 00000030 00000019 00000016 7f80: 00000012 00000000 00000000 010de1b2 b6f38008 010ccfa8 00000000 ef3a7fa8 7fa0: c020f6c0 c0290434 010de1b2 b6f38008 b6f38008 00016376 001d3774 00000000 7fc0: 010de1b2 b6f38008 010ccfa8 00000080 010de1b2 bedb6f90 010de1c9 0001d8dc 7fe0: 0000000c bedb674c 0001ce30 000094c4 60000010 b6f38008 00000008 0000001d [<c0317238>] (lock_rename+0x24/0xc4) from [<c047dfe4>] (debugfs_rename+0x34/0x208) [<c047dfe4>] (debugfs_rename+0x34/0x208) from [<c05b9e9c>] (clk_debug_reparent+0x78/0xc0) [<c05baebc>] (__clk_reparent+0x2c/0x3c) from [<c05bb124>] (__clk_init+0x258/0x4c8) [<c05bb124>] (__clk_init+0x258/0x4c8) from [<c05bb480>] (_clk_register+0xec/0x1cc) [<c05bb480>] (_clk_register+0xec/0x1cc) from [<c05bb5a8>] (devm_clk_register+0x48/0x7c) [<c05bb5a8>] (devm_clk_register+0x48/0x7c) from [<bf00010c>] (msm_mmcc_8960_probe+0xd8/0x190 [mmcc_8960]) [<bf00010c>] (msm_mmcc_8960_probe+0xd8/0x190 [mmcc_8960]) from [<c05156c0>] (platform_drv_probe+0x24/0x28) [<c05156c0>] (platform_drv_probe+0x24/0x28) from [<c0513f5c>] (driver_probe_device+0x9c/0x354) [<c0513f5c>] (driver_probe_device+0x9c/0x354) from [<c05142b8>] (__driver_attach+0xa4/0xa8) [<c05142b8>] (__driver_attach+0xa4/0xa8) from [<c0512030>] (bus_for_each_dev+0x64/0x98) [<c0512030>] (bus_for_each_dev+0x64/0x98) from [<c05139c8>] (driver_attach+0x2c/0x30) [<c05139c8>] (driver_attach+0x2c/0x30) from [<c051344c>] (bus_add_driver+0xf8/0x2a8) [<c051344c>] (bus_add_driver+0xf8/0x2a8) from [<c05149dc>] (driver_register+0x88/0x104) [<c05149dc>] (driver_register+0x88/0x104) from [<c0515914>] (__platform_driver_register+0x58/0x6c) [<c0515914>] (__platform_driver_register+0x58/0x6c) from [<bf006018>] (msm_mmcc_8960_driver_init+0x18/0x24 [mmcc_8960]) [<bf006018>] (msm_mmcc_8960_driver_init+0x18/0x24 [mmcc_8960]) from [<c0208800>] (do_one_initcall+0xf4/0x1b8) [<c0208800>] (do_one_initcall+0xf4/0x1b8) from [<c028fac4>] (load_module+0x1958/0x22bc) [<c028fac4>] (load_module+0x1958/0x22bc) from [<c02904dc>] (SyS_init_module+0xb4/0x120) [<c02904dc>] (SyS_init_module+0xb4/0x120) from [<c020f6c0>] (ret_fast_syscall+0x0/0x48) Code: e1500001 e1a04000 e1a05001 0a000021 (e5903028) Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-12-14clk: emev2: Add support for emev2 SMU clocks with DTTakashi Yoshii2-1/+105
Device tree clock binding document for EMMA Mobile EV2 SMU, And Common clock framework based implementation of it. Following nodes are defined to describe clock tree. - renesas,emev2-smu - renesas,emev2-smu-clkdiv - renesas,emev2-smu-gclk These bindings are designed manually based on 19UH0037EJ1000_SMU : System Management Unit User's Manual So far, reparent is not implemented, and is fixed to index #0. Clock tree description is not included, and should be provided by device-tree. Signed-off-by: Takashi Yoshii <takasi-y@ops.dti.ne.jp> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-12-12Merge tag 'clk-hisilicon' of git://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1/linux into clk-next-hisiliconMike Turquette6-0/+652
2013-12-12Merge branch 'clk-next-shmobile' into clk-nextMike Turquette5-0/+720
2013-12-12clk: shmobile: Add MSTP clock supportLaurent Pinchart2-0/+230
MSTP clocks are gate clocks controlled through a register that handles up to 32 clocks. The register is often sparsely populated. Those clocks are found on Renesas ARM SoCs. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-12-12clk: shmobile: Add DIV6 clock supportLaurent Pinchart2-0/+186
DIV6 clocks are divider gate clocks controlled through a single register. The divider is expressed on 6 bits, hence the name, and can take values from 1/1 to 1/64. Those clocks are found on Renesas ARM SoCs. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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