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2013-10-06clk: armada-370: fix tclk frequenciesSimon Guinot1-2/+2
This patch fixes the tclk frequency array for the Armada-370 SoC. This bug has been introduced by commit 6b72333d ("clk: mvebu: add Armada 370 SoC-centric clock init"). A wrong tclk frequency affects the following drivers: mvsdio, mvneta, i2c-mv64xxx and mvebu-devbus. This list may be incomplete. About the mvneta Ethernet driver, note that the tclk frequency is used to compute the Rx time coalescence. Then, this bug harms the coalescence configuration and also degrades the networking performances with the default values. Signed-off-by: Simon Guinot <simon.guinot@sequanux.org> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Cc: stable@vger.kernel.org Signed-off-by: Michael Turquette <mturquette@deferred.io>
2013-10-02clk: wm831x: get rid of the implementation of remove functionLaxman Dewangan1-6/+0
The remove function implemented for platform driver's remove callback just return 0 as part of its implementation. Remove this APIs and do not pass the valid .remove for platform driver. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Mark Brown <broonie@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-10-01clk: nomadik: set all timers to use 2.4 MHz TIMCLKLinus Walleij1-0/+21
This fixes a regression for the Nomadik on the main system timers. The Nomadik seemed a bit slow and its heartbeat wasn't looking healthy. And it was not strange, because it has been connected to the 32768 Hz clock at boot, while being told by the clock driver that it was 2.4MHz. Actually connect the TIMCLK to 2.4MHz by default as this is what we want for nice scheduling, clocksource and clock event. Cc: stable@vger.kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-10-01clk: Correct lookup logic in clk_fetch_parent_index()Tomasz Figa1-4/+7
This function is supposed to iterate over all parents of given child clock to find the index of given parent clock in its parent list, using parent cache if possible and falling back to string compare otherwise. However currently the logic falls back to string compare in every iteration in which clock cache entry does not match given parent, due to wrong check conditions. This patch corrects the logic to continue the loop if parent cache entry is present and does not match requested parent clock. In addition, redundant checks for parent cache array presence are removed, because it is always allocated in the beginning of the function. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-10-01clk: Use kcalloc() to allocate arraysTomasz Figa1-7/+7
Instead of calculating sizes of arrays manually, kcalloc() can be used to allocate arrays of elements with defined size. This is just a cleanup patch without any functional changes. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-10-01clk: Add error handling to clk_fetch_parent_index()Tomasz Figa1-11/+14
There are at least two different error cases that can happen in clk_fetch_parent_index() function: - allocation failure, - parent clock lookup failure, however it returns only an u8, which is supposed to contain parent clock index. This patch modified the function to return full int instead allowing positive clock indices and negative error codes to be returned. All users of this function are adjusted as well to handle the return value correctly. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-09-30Merge tag 'ux500-dt-for-v3.13-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/dtOlof Johansson3-1/+561
From Linus Walleij: This is a huge device tree and ATAG removal series for ux500: - Move all the clock definitions over to the device tree - Remove all now-redundant AUXDATA and make the ux500 device tree only * tag 'ux500-dt-for-v3.13-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: (92 commits) ARM: ux500: delete devices-common remnants clk: ux500: Provide a look-up for the ARMSS clock ARM: ux500: Enable CPUFreq on Snowball ARM: ux500: Provide a Device Tree node for CPUFreq in the DBx500 ARM: ux500: Provide a clock lookup for the Hash driver ARM: ux500: Provide a clock lookup for the Crypto driver ARM: ux500: Fix trivial white-space error in the DBX500 DTSI file ARM: ux500: Remove ATAG booting support for Snowball ARM: ux500: Remove ATAG booting support for HREF ARM: ux500: Remove ATAG booting support for U8520 ARM: ux500: Remove ATAG booting support for MOP500 ARM: ux500: Purge UIB framework when booting with ATAGs ARM: ux500: Take out STUIB support when not booting with Device Tree ARM: ux500: Remove BU21013 ROHM TS support when booting with only ATAGs ARM: ux500: Don't register the STMPE/SKE when booting with ATAG support ARM: ux500: Delete U8500 UIB support when booting with ATAGs ARM: ux500: Don't register Synaptics RMI4 TS when booting with ATAGs ARM: ux500: Purge DB8500 PRCMU registration when not booting with DT ARM: ux500: Stop requesting the SoC device to play 'parent' role ARM: ux500: Remove UART support when booting without Device Tree ... Signed-off-by: Olof Johansson <olof@lixom.net>
2013-09-29ARM: mxs: remove custom .init_time hookSebastian Hesselbarth2-15/+16
This patch converts clk-imx2[38] clocksource_of_init compatible init associated with fsl,imx2[38]-clkctrl. With arch/arm calling of_clk_init(NULL) from time_init(), we can now also remove custom .init_time hooks. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Shawn Guo <shawn.guo@linaro.org>
2013-09-29ARM: highbank: remove custom .init_time hookSebastian Hesselbarth1-3/+7
With arch/arm calling of_clk_init(NULL) from time_init(), we can now remove custom .init_time hooks. Highbank clock provider need a reference to system registers, as a workaround current clk driver maps those independent of arch code now. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Mike Turquette <mturquette@linaro.org>
2013-09-29ARM: bcm2835: remove custom .init_time hookSebastian Hesselbarth1-8/+0
With arch/arm calling of_clk_init(NULL) from time_init(), we can now remove custom .init_time hooks. Also remove call to of_clk_init from clk-bcm2835 with core fixed_clock match, as this has already been registered now. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Mike Turquette <mturquette@linaro.org>
2013-09-29ARM: vt8500: prepare for arch-wide .init_time callbackSebastian Hesselbarth1-10/+0
Current vt8500 board init calls of_clk_init() from vtwm_clk_init. To allow consolidation of DT driven .time_init, move of_clock_init() to a temporary .time_init callback that will be removed when arch-wide callback is available. With previous pmc_base parsing helper for vt8500 clock providers, we can also safely remove the call to vtwm_clk_init() and get rid of some includes. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Tony Prisk <linux@prisktech.co.nz> Acked-by: Mike Turquette <mturquette@linaro.org>
2013-09-29clk: vt8500: parse pmc_base from clock driverSebastian Hesselbarth1-0/+24
Currently, clock providers for vt8500 depend on machine_init providing pmc_base address before calling of_clk_init. With upcoming arch-wide .time_init calling of_clk_init, we should make clock providers independent of mach code. This adds a pmc_base parsing helper to current clock provider that gets called if there is no pmc_base set, yet. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Tony Prisk <linux@prisktech.co.nz> Acked-by: Mike Turquette <mturquette@linaro.org>
2013-09-29clk: sunxi: declare OF clock providerSebastian Hesselbarth1-5/+6
Common clock framework allows to register clock providers to get called on of_clk_init() by using CLK_OF_DECLARE. This converts sunxi clock providers to make use of it and get rid of the mach specific clk init call. As sunxi has a bunch of independent clk provider nodes, we hook current clock init to board compatible to make it called once. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org>
2013-09-29clk: prima2: declare OF clock providerSebastian Hesselbarth1-23/+6
Common clock framework allows to register clock providers to get called on of_clk_init() by using CLK_OF_DECLARE. This converts prima2 clock provider to make use of it and get rid of the mach specific clk init call. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Barry Song <baohua.song@csr.com> Acked-by: Mike Turquette <mturquette@linaro.org>
2013-09-29clk: nomadik: declare OF clock providerSebastian Hesselbarth1-30/+15
Common clock framework allows to register clock providers to get called on of_clk_init() by using CLK_OF_DECLARE. This converts nomadik clock provider to make use of it and get rid of the mach specific clk init call. As clocks require system reset controller base address to be initialized each clock driver checks src_base and calls new nomadik_src_init if required. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org>
2013-09-29clk: nomadik: move src init out of nomadik_clk_initSebastian Hesselbarth1-70/+74
nomadik_clk_init currently also maps system reset controller base address used by clocks and registers a reboot notifier. To allow further cleanup of nomadik clk setup, this moves system reset controller setup from nomadik_clk_init to its own function. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org>
2013-09-26clk: ux500: Provide a look-up for the ARMSS clockLee Jones1-0/+1
The ARMSS clock is used by the newly DT enabled CPUFreq driver. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-26clk: ux500: Add Device Tree support for the TWD clockLee Jones1-2/+5
This patch enables the TWD fixed factor clock to be specified from Device Tree via phandles to the "smp-twd-clock" node. Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-26clk: ux500: Add Device Tree support for the RTC clockLee Jones1-2/+5
This patch enables the RTC fixed frequency clock to be specified from Device Tree via phandles to the "rtc32k-clock" node. Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-26clk: ux500: Add Device Tree support for the PRCC Kernel clockLee Jones1-0/+32
This patch enables clocks to be specified from Device Tree via phandles to the "prcc-kernel-clock" node. Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-26clk: ux500: Add Device Tree support for the PRCC Peripheral clockLee Jones1-0/+52
This patch enables clocks to be specified from Device Tree via phandles to the "prcc-periph-clock" node. Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-26clk: ux500: Add Device Tree support for the PRCMU clockLee Jones1-2/+48
This patch enables clocks to be specified from Device Tree via phandles to the "prcmu-clock" node. Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-26clk: ux500: Add a 2-cell Device Tree parser for obtaining PRCC clocksLee Jones1-0/+22
PRCC (peripheral and kernel) clocks are specified using a property tuple <&phandle base bit>, where 'base' is the peripheral (1, 2, 3, 5 or 6), and bit is read-in value into that peripheral stipulated by the hardware specification. Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-26clk: ux500: Provide u8500_clk with skeleton Device Tree supportLee Jones1-0/+19
The functional components will be added on a per-clock basis. Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-26clk: ux500: Copy u8500_clk_init() ready for DT enablementLee Jones2-0/+382
Here we're using the old clock initialisation function as a template. It's necessary to remove all of the clk_register_clkdev() calls as they don't make sense when booting with Device Tree. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-26clk: ux500: Remove BML8580 clockLee Jones1-1/+1
There is no mention of the PRCMU_BML8580CLK in any of the Design Specifications for the chips supported in Mainline. In fact, where it is incorrectly used in the u8540 clock definition driver it would have the side effect of using the incorrect clock management address ([PRCM_BML8580CLK_MGT] 0x108 instead of the correct value 0x04C). Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-22clk: nomadik: set all timers to use 2.4 MHz TIMCLKLinus Walleij1-0/+21
This fixes a regression for the Nomadik on the main system timers. The Nomadik seemed a bit slow and its heartbeat wasn't looking healthy. And it was not strange, because it has been connected to the 32768 Hz clock at boot, while being told by the clock driver that it was 2.4MHz. Actually connect the TIMCLK to 2.4MHz by default as this is what we want for nice scheduling, clocksource and clock event. Cc: stable@vger.kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-17ARM: S3C64XX: Migrate clock handling to Common Clock FrameworkTomasz Figa1-2/+0
This patch migrates the s3c64xx platform to use the new clock driver using Common Clock Framework. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-09-09Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linuxLinus Torvalds47-1062/+2946
Pull clock framework changes from Michael Turquette: "The common clk framework changes for 3.12 are dominated by clock driver patches, both new drivers and fixes to existing. A high percentage of these are for Samsung platforms like Exynos. Core framework fixes and some new features like automagical clock re-parenting round out the patches" * tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux: (102 commits) clk: only call get_parent if there is one clk: samsung: exynos5250: Simplify registration of PLL rate tables clk: samsung: exynos4: Register PLL rate tables for Exynos4x12 clk: samsung: exynos4: Register PLL rate tables for Exynos4210 clk: samsung: exynos4: Reorder registration of mout_vpllsrc clk: samsung: pll: Add support for rate configuration of PLL46xx clk: samsung: pll: Use new registration method for PLL46xx clk: samsung: pll: Add support for rate configuration of PLL45xx clk: samsung: pll: Use new registration method for PLL45xx clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls clk: samsung: exynos4: Remove checks for DT node clk: samsung: exynos4: Remove unused static clkdev aliases clk: samsung: Modify _get_rate() helper to use __clk_lookup() clk: samsung: exynos4: Use separate aliases for cpufreq related clocks clocksource: samsung_pwm_timer: Get clock from device tree ARM: dts: exynos4: Specify PWM clocks in PWM node pwm: samsung: Update DT bindings documentation to cover clocks clk: Move symbol export to proper location clk: fix new_parent dereference before null check clk: wm831x: Initialise wm831x pointer on init ...
2013-09-09clk: only call get_parent if there is oneAlex Elder1-1/+1
In __clk_init(), after a clock is mostly initialized, a scan is done of the orphan clocks to see if the clock being registered is the parent of any of them. This code assumes that any clock that provides a get_parent method actually has at least one parent, and that's not a valid assumption. As a result, an orphan clock with no parent can return *something* as the parent index, and that value is blindly used to dereference the orphan's parent_names[] array (which will be ZERO_SIZE_PTR or NULL). Fix this by ensuring get_parent is only called for orphans with at least one parent. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-09-06clk: samsung: exynos5250: Simplify registration of PLL rate tablesTomasz Figa1-10/+2
Since the _get_rate() helper has been modified to use __clk_lookup() internally, checking of PLL input rates can be done using it and so the registration code can be simplified. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-09-06clk: samsung: exynos4: Register PLL rate tables for Exynos4x12Tomasz Figa1-0/+49
This patch adds rate tables for PLLs that can be reconfigured at runtime for Exynos4x12 SoCs. Provided tables contain PLL coefficients for input clock of 24 MHz and so are registered only in this case. MPLL does not need runtime reconfiguration and so table for it is not provided. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-09-06clk: samsung: exynos4: Register PLL rate tables for Exynos4210Tomasz Figa1-0/+45
This patch adds rate tables for PLLs that can be reconfigured at runtime for Exynos4210 SoCs. Provided tables contain PLL coefficients for input clock of 24 MHz and so are registered only in this case. MPLL does not need runtime reconfiguration and so table for it is not provided. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-09-06clk: samsung: exynos4: Reorder registration of mout_vpllsrcTomasz Figa1-1/+7
Since PLL input frequency must be known before PLL registration, mout_vpllsrc clock which is a reference clock of VPLL must be registered before VPLL. This patch reorders clock registration to register mout_vpllsrc before VPLL. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-09-06clk: samsung: pll: Add support for rate configuration of PLL46xxTomasz Figa2-1/+135
This patch implements round_rate and set_rate callbacks of PLL46xx driver to allow reconfiguration of PLL at runtime. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-09-06clk: samsung: pll: Use new registration method for PLL46xxTomasz Figa3-65/+14
This patch modifies PLL46xx support code and its users to use the recently introduced common PLL registration helper. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-09-06clk: samsung: pll: Add support for rate configuration of PLL45xxTomasz Figa2-1/+119
This patch implements round_rate and set_rate callbacks of PLL45xx driver to allow reconfiguration of PLL at runtime. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-09-06clk: samsung: pll: Use new registration method for PLL45xxTomasz Figa3-62/+20
This patch modifies PLL45xx support code and its users to use the recently introduced common PLL registration helper. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-09-06clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_pllsTomasz Figa1-3/+3
This array defines PLLs specific to Exynos 4x12 SoCs and not for all Exynos 4 SoCs, so the name should represent that. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-09-06clk: samsung: exynos4: Remove checks for DT nodeTomasz Figa1-7/+4
Exynos 4 supports only DT based bootup, so non-DT cases does not need to be handled anymore. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-09-06clk: samsung: exynos4: Remove unused static clkdev aliasesTomasz Figa1-184/+172
Since Exynos does not support legacy non-DT boot anymore, most of clock lookups happen using device tree, so most of static clkdev aliases are no longer necessary. This patch removes them. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-09-06clk: samsung: Modify _get_rate() helper to use __clk_lookup()Tomasz Figa3-9/+7
There is no need to use clkdev inside the clock driver to retrieve the clocks for internal use. Instead __clk_lookup() helper can be used to look up clocks by their platform name. This patch modifies the behavior of _get_rate() helper to look up clocks by platform name and adjusts all users of it to pass platform names instead of clkdev aliases. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-09-06clk: samsung: exynos4: Use separate aliases for cpufreq related clocksTomasz Figa1-8/+27
Exynos cpufreq driver is the only remaining piece of code that needs static clkdev aliases for operation, because it can not do device tree based clock lookups yet. This patch moves clock alias definitions for those clocks to separate arrays that can be used with samsung_clk_register_alias() helper. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-09-06Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds1-0/+38
Pull ARM SoC platform changes from Olof Johansson: "This branch contains mostly additions and changes to platform enablement and SoC-level drivers. Since there's sometimes a dependency on device-tree changes, there's also a fair amount of those in this branch. Pieces worth mentioning are: - Mbus driver for Marvell platforms, allowing kernel configuration and resource allocation of on-chip peripherals. - Enablement of the mbus infrastructure from Marvell PCI-e drivers. - Preparation of MSI support for Marvell platforms. - Addition of new PCI-e host controller driver for Tegra platforms - Some churn caused by sharing of macro names between i.MX 6Q and 6DL platforms in the device tree sources and header files. - Various suspend/PM updates for Tegra, including LP1 support. - Versatile Express support for MCPM, part of big little support. - Allwinner platform support for A20 and A31 SoCs (dual and quad Cortex-A7) - OMAP2+ support for DRA7, a new Cortex-A15-based SoC. The code that touches other architectures are patches moving MSI arch-specific functions over to weak symbols and removal of ARCH_SUPPORTS_MSI, acked by PCI maintainers" * tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (266 commits) tegra-cpuidle: provide stub when !CONFIG_CPU_IDLE PCI: tegra: replace devm_request_and_ioremap by devm_ioremap_resource ARM: tegra: Drop ARCH_SUPPORTS_MSI and sort list ARM: dts: vf610-twr: enable i2c0 device ARM: dts: i.MX51: Add one more I2C2 pinmux entry ARM: dts: i.MX51: Move pins configuration under "iomuxc" label ARM: dtsi: imx6qdl-sabresd: Add USB OTG vbus pin to pinctrl_hog ARM: dtsi: imx6qdl-sabresd: Add USB host 1 VBUS regulator ARM: dts: imx27-phytec-phycore-som: Enable AUDMUX ARM: dts: i.MX27: Disable AUDMUX in the template ARM: dts: wandboard: Add support for SDIO bcm4329 ARM: i.MX5 clocks: Remove optional clock setup (CKIH1) from i.MX51 template ARM: dts: imx53-qsb: Make USBH1 functional ARM i.MX6Q: dts: Enable I2C1 with EEPROM and PMIC on Phytec phyFLEX-i.MX6 Ouad module ARM i.MX6Q: dts: Enable SPI NOR flash on Phytec phyFLEX-i.MX6 Ouad module ARM: dts: imx6qdl-sabresd: Add touchscreen support ARM: imx: add ocram clock for imx53 ARM: dts: imx: ocram size is different between imx6q and imx6dl ARM: dts: imx27-phytec-phycore-som: Fix regulator settings ARM: dts: i.MX27: Remove clock name from CPU node ...
2013-09-03clk: Move symbol export to proper locationThierry Reding1-1/+1
The __clk_get_flags() symbol is exported immediately following the clk_unprepare_unused_subtree() function. This is unusual, since a symbol export typically follows body of the function that it exports. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-30clk: fix new_parent dereference before null checkJames Hogan1-6/+7
Commit 71472c0 (clk: add support for clock reparent on set_rate) added a dereference of the new_parent pointer in clk_reparent(), but as detected by smatch clk_reparent() later checks whether new_parent is NULL. The dereference was in order to clear the new parent's new_child pointer to avoid duplicate POST_RATE_CHANGE notifications, so clearly isn't necessary if the new parent is NULL, so move it inside the "if (new_parent)" block. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-30clk: wm831x: Initialise wm831x pointer on initMark Brown1-0/+2
Otherwise any attempt to interact with the hardware will crash. This is what happens when drivers get written blind. Signed-off-by: Mark Brown <broonie@linaro.org> Cc: stable@vger.kernel.org Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-29clk/exynos5420: assign dout_pixel id to pixel clock dividerRahul Sharma1-1/+4
dout_pixel is a new ID allocated for pixel clock divider. It is queried in the driver to pass as the parent to hdmi clock while switching between parents. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-29clk/exynos5420: add hdmi mux to change parents in hdmi driverRahul Sharma1-1/+4
hdmi driver needs to change the parent of hdmi clock to pixel clock or hdmiphy clock, based on the stability of hdmiphy. This patch is exposing the mux for changing the parent. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-29clk/exynos5420: fix the order of parents of hdmi muxRahul Sharma1-1/+1
Listing sclk_hdmiphy at 0th position in the list of parents is causing wrong configuration in reg SRC_DISP10. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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