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2021-11-23clk: sunxi-ng: Add support for the D1 SoC clocksSamuel Holland6-0/+1576
The D1 SoC contains a CCU and a R_CCU (PRCM CCU). Add support for them. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20211119043545.4010-7-samuel@sholland.org
2021-11-23clk: sunxi-ng: gate: Add macros for gates with fixed dividersSamuel Holland1-1/+31
It is possible to declare a gate with a fixed divider, by using the CCU_FEATURE_ALL_PREDIV flag. Since this is not obvious, add a macro for declaring this type of clock. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20211119043545.4010-6-samuel@sholland.org
2021-11-23clk: sunxi-ng: mux: Add macros using clk_parent_data and clk_hwSamuel Holland1-0/+33
Referencing parents with clk_hw pointers is more efficient and removes the dependency on global clock names. clk_parent_data is needed when some parent clocks are provided from another driver. Add macros for declaring muxes that take advantage of these. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20211119043545.4010-5-samuel@sholland.org
2021-11-23clk: sunxi-ng: mp: Add macros using clk_parent_data and clk_hwSamuel Holland1-0/+49
Referencing parents with clk_hw pointers is more efficient and removes the dependency on global clock names. clk_parent_data is needed when some parent clocks are provided from another driver. Add macros for declaring dividers that take advantage of these. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20211119043545.4010-4-samuel@sholland.org
2021-11-23clk: sunxi-ng: div: Add macros using clk_parent_data and clk_hwSamuel Holland1-0/+78
Referencing parents with clk_hw pointers is more efficient and removes the dependency on global clock names. clk_parent_data is needed when some parent clocks are provided from another driver. Add macros for declaring dividers that take advantage of these. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20211119043545.4010-3-samuel@sholland.org
2021-11-23clk: sunxi-ng: Allow the CCU core to be built as a moduleSamuel Holland4-17/+24
Like the individual CCU drivers, it can be beneficial for memory consumption of cross-platform configurations to only load the CCU core on the relevant platform. For example, a generic arm64 kernel sees the following improvement when building the CCU core and drivers as modules: before: text data bss dec hex filename 13882360 5251670 360800 19494830 12977ae vmlinux after: text data bss dec hex filename 13734787 5086442 360800 19182029 124b1cd vmlinux So the result is a 390KB total reduction in kernel image size. The one early clock provider (sun5i) requires the core to be built in. Now that loading the MMC driver will trigger loading the CCU core, the MMC timing mode functions do not need a compile-time fallback. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20211119033338.25486-5-samuel@sholland.org
2021-11-23clk: sunxi-ng: Convert early providers to platform driversSamuel Holland11-173/+333
The PRCM CCU drivers depend on clocks provided by other CCU drivers. For example, the sun8i-r-ccu driver uses the "pll-periph" clock provided by the SoC's main CCU. However, sun8i-r-ccu is an early OF clock provider, and many of the main CCUs (e.g. sun50i-a64-ccu) use platform drivers. This means that the consumer clocks will be orphaned until the supplier driver is bound. This can be avoided by converting the remaining CCUs to use platform drivers. Then fw_devlink will ensure the drivers are bound in the optimal order. The sun5i CCU is the only one which actually needs to be an early clock provider, because it provides the clock for the system timer. That one is left alone. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20211119033338.25486-4-samuel@sholland.org
2021-11-22clk: samsung: exynos850: Register clocks earlySam Protsenko1-21/+49
Some clocks must be registered before init calls. For example MCT clock (from CMU_PERI) is needed for MCT timer driver, which is registered with TIMER_OF_DECLARE(). By the time we get to core_initcall() used for clk-exynos850 platform driver init, it's already too late. Inability to get "mct" clock in MCT driver leads to kernel panic, as functions registered with *_OF_DECLARE() can't do deferred calls. MCT timer driver can't be fixed either, as it's acting as a clock source and it's essential to register it in start_kernel() -> time_init(). Let's register CMU_PERI clocks early, using CLK_OF_DECLARE(). CMU_TOP generates clocks needed for CMU_PERI, but it's already registered early. While at it, let's cleanup the code a bit, by extracting everything related to CMU initialization and registration to the separate function. Similar issue was discussed at [1] and addressed in commit 1f7db7bbf031 ("clk: renesas: cpg-mssr: Add early clock support"), as well as in drivers/clk/mediatek/clk-mt2712.c. [1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20180829132954.64862-2-chris.brandt@renesas.com/ Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20211122144206.23134-1-semen.protsenko@linaro.org
2021-11-22clk: imx8mp: Fix the parent clk of the audio_root_clkHui Wang1-1/+1
Having the parent of the audio_root_clk set to ipg_root in the clk-imx8mp.c, there is a hang happening when the audiomix IP regs are accessed. Switch parent to audio_ahb. And we could also refer to the section "5.1.4 System Clocks" of the IMX8MPRM.pdf, the parent clk of CCGR101 (Audiomix) is the AUDIO_AHB_CLK_ROOT. Signed-off-by: Hui Wang <hui.wang@canonical.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20211109125657.63485-2-hui.wang@canonical.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-11-22clk: imx8mn: Fix imx8mn_clko1_selsAdam Ford1-3/+3
When attempting to use sys_pll1_80m as the parent for clko1, the system hangs. This is due to the fact that the source select for sys_pll1_80m was incorrectly pointing to m7_alt_pll_clk, which doesn't yet exist. According to Rev 3 of the TRM, The imx8mn_clko1_sels also incorrectly references an osc_27m which does not exist, nor does an entry for source select bits 010b. Fix both by inserting a dummy clock into the missing space in the table and renaming the incorrectly name clock with dummy. Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver") Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/20211117133202.775633-1-aford173@gmail.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-11-22clk: imx: Use div64_ul instead of do_divChangcheng Deng1-3/+3
do_div() does a 64-by-32 division. Here the divisor is an unsigned long which on some platforms is 64 bit wide. So use div64_ul instead of do_div to avoid a possible truncation. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: Changcheng Deng <deng.changcheng@zte.com.cn> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20211118080634.165275-1-deng.changcheng@zte.com.cn Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-11-22clk: imx: imx8ulp: set suppress_bind_attrs to truePeng Fan1-0/+1
The clock driver is registered as platform devices and it is possible to reloading the driver at runtime. But actually the clocks should never be removed to make system work, attempting to bind again would result in a crash, because almost all devices depends on clock to function well. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20211022131513.17381-1-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-11-22clk: samsung: exynos850: Keep some crucial clocks runningSam Protsenko1-6/+13
Some clocks shouldn't be automatically disabled in clk_disable_unused(), otherwise kernel hangs. Mark those clocks with: - CLK_IS_CRITICAL flag, when there won't be any consumers for that clock, but system can't function when it's gated - CLK_IGNORE_UNUSED flag, when consumer driver will be probably added later That makes it possible to run the kernel without passing the "clk_ignore_unused" param. Next clocks were modified: - "gout_dpu_cmu_dpu_pclk": CLK_IGNORE_UNUSED Will be enabled later in DSIM driver (Display Serial Interface Master). - "gout_gpio_peri_pclk": CLK_IGNORE_UNUSED "gout_gpio_cmgp_pclk": CLK_IGNORE_UNUSED "gout_gpio_hsi_pclk": CLK_IGNORE_UNUSED Should be probably enabled in corresponding GPIO driver later, or made CLK_IS_CRITICAL. "gout_gpio_peri_clk" is actually used by LEDs on Exynos850-based dev board, so kernel hangs if this clock is not running. Other clocks were marked as "ignore unused" to prevent similar issues for other use cases or boards that might be added later. - "gout_cci_aclk": CLK_IS_CRITICAL CCI (Cache Coherent Interconnect): obviously is critical. - "gout_gic_clk": CLK_IS_CRITICAL GIC (Generic Interrupt Controller): obviously is critical. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20211121232741.6967-7-semen.protsenko@linaro.org
2021-11-22clk: samsung: exynos850: Implement CMU_CMGP domainSam Protsenko1-0/+100
CMU_CMGP clock domain provides clocks for CMGP IP-core (Common GPIO). CMGP module encapsulates next blocks: - 8 GPIO lines - 1 GPADC - 2 USI blocks, each can be configured to provide one of UART/SPI/HSI2C serial interfaces Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20211121232741.6967-5-semen.protsenko@linaro.org
2021-11-22clk: samsung: exynos850: Implement CMU_APM domainSam Protsenko1-1/+141
CMU_APM clock domain provides clocks for APM IP-core (Active Power Management). According to Exynos850 TRM, CMU_APM generates I3C, Mailbox, Speedy, Timer, WDT, RTC and PMU clocks for BLK_ALIVE. This patch adds next clocks: - bus clocks in CMU_TOP needed for CMU_APM - all internal CMU_APM clocks - leaf clocks for I3C, Speedy and RTC IP-cores - bus clocks for CMU_CMGP and CMU_CHUB CMU_APM doesn't belong to Power Domains, but platform driver is used for its registration to keep its bus clock always running. Otherwise rtc-s3c driver disables that clock and system freezes. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20211121232741.6967-3-semen.protsenko@linaro.org
2021-11-22clk: sunxi-ng: Allow drivers to be built as modulesSamuel Holland12-47/+98
While it is useful to build all of the CCU drivers at once, only 1-3 of them will be loaded at a time, or possibly none of them if the kernel is booted on a non-sunxi platform. These CCU drivers are relatively large; 32-bit drivers have 30-50k of data each, while the 64-bit ones are 50-75k due to the increased pointer overhead. About half of that data comes from relocations. Let's allow the user to build these drivers as modules so only the necessary data is loaded. As a first step, convert the CCUs that are already platform drivers. When the drivers are built as modules, normally the file name becomes the module name. However, the current file names are inconsistent with the <platform>-<peripheral> name used everywhere else: the devicetree bindings, the platform driver names, and the Kconfig symbols. Use Makfile logic to rename the modules so they follow the usual pattern. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20211119033338.25486-3-samuel@sholland.org
2021-11-22clk: sunxi-ng: Export symbols used by CCU driversSamuel Holland14-0/+35
For the individual CCU drivers to be built as modules, the ops structs, helper functions, and callback registration functions must be exported. These symbols are intended for use only by the adjacent CCU drivers, so export them into the SUNXI_CCU namespace. of_sunxi_ccu_probe is not exported because it is only used by built-in OF clock providers. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20211119033338.25486-2-samuel@sholland.org
2021-11-20clk: samsung: Update CPU clk registrationWill McVicker6-57/+67
Convert the remaining exynos clock drivers to use samsung_clk_register_cpu() or if possible use samsung_cmu_register_one(). With this we can now make exynos_register_cpu_clock() a static function so that future CPU clock registration changes will use the samsung common clock driver. The main benefit of this change is that it standardizes the CPU clock registration for the samsung clock drivers. Link: https://lore.kernel.org/r/20211015190515.3760577-1-willmcvicker@google.com Signed-off-by: Will McVicker <willmcvicker@google.com> Tested-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> [snawrocki@kernel.org: Fixed build break in clk-exynos4.c, clk-exynos5250.c] Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2021-11-19clk: samsung: Remove meaningless __init and extern from header filesSylwester Nawrocki2-18/+18
Remove useless __init atrribute and unneeded extern qualifier in function declarations in header files. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20211015151425.29743-1-s.nawrocki@samsung.com
2021-11-19clk: samsung: remove __clk_lookup() usageMarek Szyprowski8-36/+32
__clk_lookup() interface is obsolete, so remove it from the Samsung clock drivers. This has been achieved by getting rid of custom _get_rate() helper and replacing it with clk_hw_get_rate(). Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20211018125456.8292-2-m.szyprowski@samsung.com Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2021-11-19clk: renesas: cpg-mssr: propagate return value of_genpd_add_provider_simple()Lad Prabhakar1-2/+1
of_genpd_add_provider_simple() might fail, this patch makes sure we check the return value of of_genpd_add_provider_simple() by propagating the return value to the caller of cpg_mssr_add_clk_domain(). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211117115101.28281-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-19clk: renesas: cpg-mssr: Check return value of pm_genpd_init()Lad Prabhakar1-1/+14
Make sure we check the return value of pm_genpd_init() which might fail. Also add a devres action to remove the power-domain in-case the probe callback fails further down in the code flow. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211117115101.28281-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-19clk: renesas: rzg2l: propagate return value of_genpd_add_provider_simple()Lad Prabhakar1-2/+1
of_genpd_add_provider_simple() might fail, this patch makes sure we check the return value of of_genpd_add_provider_simple() by propagating the return value to the caller of rzg2l_cpg_add_clk_domain(). Fixes: ef3c613ccd68a ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC") Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211117115101.28281-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-19clk: renesas: rzg2l: Check return value of pm_genpd_init()Lad Prabhakar1-1/+13
Make sure we check the return value of pm_genpd_init() which might fail. Also add a devres action to remove the power-domain in-case the probe callback fails further down in the code flow. Fixes: ef3c613ccd68a ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC") Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211117115101.28281-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-19clk: renesas: r9a07g044: Add RSPI clock and reset entriesLad Prabhakar1-0/+9
Add RSPI{0,1,2} clock and reset entries to CPG driver. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20211117002601.17971-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-19clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIVBiju Das1-1/+10
Core clock "I" is sourced from CPG_PL1_DDIV divider as per HW manual Rev.1.00. This patch adds clock divider table "dtable_1_8" and switches to DEF_DIV for "I" clock. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211112081003.15453-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-19clk: renesas: rzg2l: Add CPG_PL1_DDIV macroBiju Das1-0/+2
Core clock "I" is sourced from CPG_PL1_DDIV which controls CPU frequency. Define CPG_PL1_DDIV, so that we can register it as a clock divider in later patch. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211112081003.15453-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-19clk: renesas: rcar-gen3: Remove outdated SD_SKIP_FIRSTWolfram Sang1-12/+3
We handle it differently meanwhile. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20211110191610.5664-7-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-19clk: renesas: rcar-gen3: Switch to new SD clock handlingWolfram Sang4-202/+32
The old SD handling code was huge and could not handle all the details which showed up on R-Car Gen3 SoCs meanwhile. It is time to switch to another design. Have SDnH a separate clock, use the existing divider clocks and move the errata handling from the clock driver to the SDHI driver where it belongs. This patch removes the old SD handling code and switch to the new one. This updates the SDHI driver at the same time. Because the SDHI driver can only communicate with the clock driver via clk_set_rate(), I don't see an alternative to this flag-day-approach, so we cross subsystems here. The patch sadly looks messy for the CPG lib, but it is basically a huge chunk of code removed and smaller chunks added. It looks much better when you just view the resulting source file. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # For MMC Link: https://lore.kernel.org/r/20211110191610.5664-6-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-19clk: renesas: r8a779a0: Add SDnH clock to V3UWolfram Sang1-1/+10
Currently a pass-through clock but we will make it a real divider clock in the next patches. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20211110191610.5664-4-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-19clk: renesas: rcar-gen3: Add SDnH clockWolfram Sang10-32/+64
Currently a pass-through clock but we will make it a real divider clock in the next patches. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20211110191610.5664-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-19clk: renesas: rcar-gen3: Add dummy SDnH clockWolfram Sang4-0/+21
Currently, SDnH is handled together with SDn. This caused lots of problems, so we want SDnH as a separate clock. Introduce a dummy SDnH type here which creates a fixed-factor clock with factor 1. That allows us to convert the per-SoC CPG drivers while keeping the old behaviour for now. A later patch then will add the proper functionality. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20211110191610.5664-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-18Merge drm/drm-next into drm-misc-nextThomas Zimmermann182-2412/+14697
Backmerging from drm/drm-next for v5.16-rc1. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
2021-11-15clk: renesas: r9a07g044: Add OSTM clock and reset entriesBiju Das1-0/+9
Add OSTM{0,1,2} clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211110082019.28554-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-15clk: renesas: r9a07g044: Rename CLK_PLL2_DIV16 and CLK_PLL2_DIV20 macrosBiju Das1-6/+6
Rename the macros CLK_PLL2_DIV16->CLK_PLL2_DIV2_8 and CLK_PLL2_DIV20->CLK_PLL2_DIV2_10 to match the clock tree mentioned in the hardware manual(Rev.1.00 Sep, 2021). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211110082019.28554-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-15clk: renesas: r9a07g044: Add WDT clock and reset entriesBiju Das1-0/+15
Add WDT{0,1,2} clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20211104160858.15550-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-15clk: renesas: r9a07g044: Add clock and reset entry for SCI1Lad Prabhakar1-0/+3
Add clock and reset entry for SCI1 interface. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20211103160537.32253-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-15clk: renesas: rzg2l: Add missing kerneldoc for resetsGeert Uytterhoeven2-0/+4
make W=1: drivers/clk/renesas/rzg2l-cpg.c:95: warning: Function parameter or member 'num_resets' not described in 'rzg2l_cpg_priv' Add the missing kerneldoc for fields in struct rzg2l_cpg_priv and struct rzg2l_cpg_info related to Module Resets. Fixes: c3e67ad6f5a2c698 ("dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/39c2c5fd4232b6620a4a56dba4e2b0d61476ee36.1634646869.git.geert+renesas@glider.be
2021-11-14Merge tag 'devicetree-fixes-for-5.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linuxLinus Torvalds8-9/+11
Pull devicetree fixes from Rob Herring: - Two fixes due to DT node name changes on Arm, Ltd. boards - Treewide rename of Ingenic CGU headers - Update ST email addresses - Remove Netlogic DT bindings - Dropping few more cases of redundant 'maxItems' in schemas - Convert toshiba,tc358767 bridge binding to schema * tag 'devicetree-fixes-for-5.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: dt-bindings: watchdog: sunxi: fix error in schema bindings: media: venus: Drop redundant maxItems for power-domain-names dt-bindings: Remove Netlogic bindings clk: versatile: clk-icst: Ensure clock names are unique of: Support using 'mask' in making device bus id dt-bindings: treewide: Update @st.com email address to @foss.st.com dt-bindings: media: Update maintainers for st,stm32-hwspinlock.yaml dt-bindings: media: Update maintainers for st,stm32-cec.yaml dt-bindings: mfd: timers: Update maintainers for st,stm32-timers dt-bindings: timer: Update maintainers for st,stm32-timer dt-bindings: i2c: imx: hardware do not restrict clock-frequency to only 100 and 400 kHz dt-bindings: display: bridge: Convert toshiba,tc358767.txt to yaml dt-bindings: Rename Ingenic CGU headers to ingenic,*.h
2021-11-13Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linuxLinus Torvalds16-47/+94
Pull more clk updates from Stephen Boyd: "This is the second batch of clk driver updates that needed a little more time to soak in linux-next. - Use modern i2c probe in vc5 - Cleanup some includes - Update links to datasheets - Add UniPhier NX1 SoC clk support - Fix DT bindings for SiFive FU740 - Revert the module platform driver support for Rockchip because it wasn't actually tested - Fix the composite clk code again as the previous fix had a one line bug that broke rate changes for clks that want to use the same parent still - Use the right table for a divider in ast2600 driver - Get rid of gcc_aggre1_pnoc_ahb_clk in qcom clk driver again because its critical but unused" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: qcom: gcc-msm8996: Drop (again) gcc_aggre1_pnoc_ahb_clk clk: imx8m: Do not set IMX_COMPOSITE_CORE for non-regular composites clk/ast2600: Fix soc revision for AHB clk: composite: Fix 'switching' to same clock clk: rockchip: drop module parts from rk3399 and rk3568 drivers Revert "clk: rockchip: use module_platform_driver_probe" clk:mediatek: remove duplicate include in clk-mt8195-imp_iic_wrap.c dt-bindings: clock: fu740-prci: add reset-cells clk: uniphier: Add SoC-glue clock source selector support for Pro4 dt-bindings: clock: uniphier: Add clock binding for SoC-glue clk: uniphier: Add NX1 clock support dt-bindings: clock: uniphier: Add NX1 clock binding clk: uniphier: Add audio system and video input clock control for PXs3 clk: si5351: Update datasheet references clk: vc5: Use i2c .probe_new clk/actions/owl-factor.c: remove superfluous headers clk: ingenic: Fix bugs with divided dividers
2021-11-11clk: versatile: clk-icst: Ensure clock names are uniqueRob Herring1-2/+4
Commit 2d3de197a818 ("ARM: dts: arm: Update ICST clock nodes 'reg' and node names") moved to using generic node names. That results in trying to register multiple clocks with the same name. Fix this by including the unit-address in the clock name. Fixes: 2d3de197a818 ("ARM: dts: arm: Update ICST clock nodes 'reg' and node names") Cc: stable@vger.kernel.org Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-clk@vger.kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20211109164650.2233507-3-robh@kernel.org
2021-11-11dt-bindings: Rename Ingenic CGU headers to ingenic,*.hPaul Cercueil7-7/+7
Tidy up a bit the tree, by prefixing all include/dt-bindings/clock/ files related to Ingenic SoCs with 'ingenic,'. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211016133322.40771-1-paul@crapouillou.net
2021-11-08Merge tag 'mfd-next-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfdLinus Torvalds1-0/+1
Pull MFD updates from Lee Jones: "Removed Drivers: - Remove support for TI TPS80031/TPS80032 PMICs New Device Support: - Add support for Magnetic Reader to TI AM335x - Add support for DA9063_EA to Dialog DA9063 - Add support for SC2730 PMIC to Spreadtrum SC27xx - Add support for MacBookPro16,2 ICL-N UART Intel LPSS PCI - Add support for lots of new PMICS in QCom SPMI PMIC - Add support for ADC to Diolan DLN2 New Functionality: - Add support for Power Off to Rockchip RK817 Fix-ups: - Simplify Regmap passing to child devices in hi6421-spmi-pmic - SPDX licensing updates in ti_am335x_tscadc - Improve error handling in ti_am335x_tscadc - Expedite clock search in ti_am335x_tscadc - Generic simplifications in ti_am335x_tscadc - Use generic macros/defines in ti_am335x_tscadc - Remove unused code in ti_am335x_tscadc, cros_ec_dev - Convert to GPIOD in wcd934x - Add namespacing in ti_am335x_tscadc - Restrict compilation to relevant arches in intel_pmt - Provide better description/documentation in exynos_lpass - Add SPI device ID table in altera-a10sr, motorola-cpcap, sprd-sc27xx-spi - Change IRQ handling in qcom-pm8xxx - Split out I2C and SPI code in arizona - Explicitly include used headers in altera-a10sr - Convert sysfs show() function to in sysfs_emit - Standardise *_exit() and *_remove() return values in mc13xxx, stmpe, tps65912 - Trivial (style/spelling/whitespace) fixups in ti_am335x_tscadc, qcom-spmi-pmic, max77686-private - Device Tree fix-ups in ti,am3359-tscadc, samsung,s2mps11, samsung,s2mpa01, samsung,s5m8767, brcm,misc, brcm,cru, syscon, qcom,tcsr, xylon,logicvc, max77686, x-powers,ac100, x-powers,axp152, x-powers,axp209-gpio, syscon, qcom,spmi-pmic Bug Fixes: - Balance refcounting (get/put) in ti_am335x_tscadc, mfd-core - Fix IRQ trigger type in sec-irq, max77693, max14577 - Repair off-by-one in altera-sysmgr - Add explicit 'select MFD_CORE' to MFD_SIMPLE_MFD_I2C" * tag 'mfd-next-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (95 commits) mfd: simple-mfd-i2c: Select MFD_CORE to fix build error mfd: tps80031: Remove driver mfd: max77686: Correct tab-based alignment of register addresses mfd: wcd934x: Replace legacy gpio interface for gpiod dt-bindings: mfd: qcom: pm8xxx: Add pm8018 compatible mfd: dln2: Add cell for initializing DLN2 ADC mfd: qcom-spmi-pmic: Add missing PMICs supported by socinfo mfd: qcom-spmi-pmic: Document ten more PMICs in the binding mfd: qcom-spmi-pmic: Sort compatibles in the driver mfd: qcom-spmi-pmic: Sort the compatibles in the binding mfd: janz-cmoio: Replace snprintf in show functions with sysfs_emit mfd: altera-a10sr: Include linux/module.h mfd: tps65912: Make tps65912_device_exit() return void mfd: stmpe: Make stmpe_remove() return void mfd: mc13xxx: Make mc13xxx_common_exit() return void dt-bindings: mfd: syscon: Add samsung,exynosautov9-sysreg compatible mfd: altera-sysmgr: Fix a mistake caused by resource_size conversion dt-bindings: gpio: Convert X-Powers AXP209 GPIO binding to a schema dt-bindings: mfd: syscon: Add rk3368 QoS register compatible mfd: arizona: Split of_match table into I2C and SPI versions ...
2021-11-05clk: qcom: gcc-msm8996: Drop (again) gcc_aggre1_pnoc_ahb_clkDmitry Baryshkov1-15/+0
The gcc_aggre1_pnoc_ahb_clk is crucial for the proper MSM8996/APQ8096 functioning. If it gets disabled, several subsytems will stop working (including eMMC/SDCC and USB). There are no in-kernel users of this clock, so it is much simpler to remove from the kernel. The clock was first removed in the commit 9e60de1cf270 ("clk: qcom: Remove gcc_aggre1_pnoc_ahb_clk from msm8996") by Stephen Boyd, but got added back in the commit b567752144e3 ("clk: qcom: Add some missing gcc clks for msm8996") by Rajendra Nayak. Let's remove it again in hope that nobody adds it back. Reported-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Cc: Rajendra Nayak <rnayak@codeaurora.org> Cc: Konrad Dybcio <konrad.dybcio@somainline.org> Fixes: b567752144e3 ("clk: qcom: Add some missing gcc clks for msm8996") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20211104011155.2209654-1-dmitry.baryshkov@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-11-05clk: imx8m: Do not set IMX_COMPOSITE_CORE for non-regular compositesAlexander Stein1-2/+2
Only imx8m_clk_hw_composite_core needs to set this flag. Fixes: a60fe746df94 ("clk: imx: Rework all imx_clk_hw_composite wrappers") Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Link: https://lore.kernel.org/r/20211103123947.3222443-1-alexander.stein@ew.tq-group.com Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Tested-by: Adam Ford <aford173@gmail.com> #imx8mm-beacon Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-11-03Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linuxLinus Torvalds161-2349/+14590
Pull clk updates from Stephen Boyd: "The usual collection of clk driver updates and new driver additions. In terms of lines it's mainly Qualcomm and Mediatek code, supporting various SoCs and their multitude of clk controllers. New Drivers: - GCC and RPMcc support for Qualcomm QCM2290 SoCs - GCC support for Qualcomm MSM8994/MSM8992 SoCs - LPASSCC and CAMCC support for Qualcomm SC7280 SoCs - Support for Mediatek MT8195 SoCs - Initial clock driver for the Exynos850 SoC - Add i.MX8ULP clock driver and related bindings Updates: - Clock power management for new SAMA7G5 SoC - Updates to the master clock driver and sam9x60-pll to be able to use cpufreq-dt driver and avoid overclocking of CPU and MCK0 domains while changing the frequency via DVFS - Use ARRAY_SIZE in qcom clk drivers - Remove some impractical fallback parent names in qcom clk drivers - Make Mediatek clk drivers tristate - Refactoring of the CPU clock code and conversion of Samsung Exynos5433 CPU clock driver to the platform driver - A few conversions to devm_platform_ioremap_resource() - Updates of the Samsung Kconfig help text - Update video path realted clocks for Amlogic meson8 - Add SPI Multi I/O Bus and SDHI clocks and resets on Renesas RZ/G2L - Add SPI Multi I/O Bus (RPC) clocks on Renesas R-Car V3U - Add MediaLB clocks on Renesas R-Car H3, M3-W/W+, and M3-N - Remove unused helpers from i.MX specific clock header - Rework all i.MX clk based helpers to use clk_hw based ones - Rework i.MX gate/mux/divider wrappers - Rework imx_clk_hw_composite and imx_clk_hw_pll14xx wrappers - Update i.MX pllv4 and composite clocks to support i.MX8ULP - Disable i.MX7ULP composite clock during initialization - Add CLK_SET_RATE_NO_REPARENT flag to the i.MX7ULP composite - Disable the i.MX pfd when set pfdv2 clock rate - Add support for i.MX8ULP in pfdv2 - Add the pcc reset controller support on i.MX8ULP - Fix the build break when clk-imx8ulp is built as module - Move csi_sel mux to correct base register in i.MX6UL clock drivr - Fix csi clk gate register in i.MX6UL clock driver - Fix build bug making CLK_IMX8ULP select MXC_CLK - Add TPU (PWM), and Z (Cortex-A76) clocks on Renesas R-Car V3U - Add Ethernet clocks on Renesas RZ/G2L - Move Rockchip to use module_platform_probe - Enable usage of Coresight related clocks on Rockchip rk3399" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (170 commits) clk: use clk_core_get_rate_recalc() in clk_rate_get() clk: at91: sama7g5: set low limit for mck0 at 32KHz clk: at91: sama7g5: remove prescaler part of master clock clk: at91: clk-master: add notifier for divider clk: at91: clk-sam9x60-pll: add notifier for div part of PLL clk: at91: clk-master: fix prescaler logic clk: at91: clk-master: mask mckr against layout->mask clk: at91: clk-master: check if div or pres is zero clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULL clk: at91: pmc: add sama7g5 to the list of available pmcs clk: at91: clk-master: improve readability by using local variables clk: at91: clk-master: add register definition for sama7g5's master clock clk: at91: sama7g5: add securam's peripheral clock clk: at91: pmc: execute suspend/resume only for backup mode clk: at91: re-factor clocks suspend/resume clk: ux500: Add driver for the reset portions of PRCC dt-bindings: clock: u8500: Rewrite in YAML and extend clk: composite: Use rate_ops.determine_rate when also a mux is available clk: samsung: describe drivers in Kconfig clk: samsung: exynos5433: update apollo and atlas clock probing ...
2021-11-03clk/ast2600: Fix soc revision for AHBJoel Stanley1-5/+7
Move the soc revision parsing to the initial probe, saving the driver from parsing the register multiple times. Use this variable to select the correct divisor table for the AHB clock. Before this fix the A2 would have used the A0 table. Fixes: 2d491066ccd4 ("clk: ast2600: Fix AHB clock divider for A1") Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210922235449.213631-1-joel@jms.id.au Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-11-03clk: composite: Fix 'switching' to same clockAlexander Stein1-0/+1
During commit 6594988fd625 ("clk: composite: Use rate_ops.determine_rate when also a mux is available") setting req->best_parent_hw got lost, so best_parent_hw stays NULL during switch to the same parent. This results in the (debug) message: clk_calc_new_rates: lcdif_pixel not gated but wants to reparent and the following rate change is dropped. Fixes: 6594988fd625 ("clk: composite: Use rate_ops.determine_rate when also a mux is available") Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Link: https://lore.kernel.org/r/20211103122441.3208576-1-alexander.stein@ew.tq-group.com Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-11-02clk: rockchip: drop module parts from rk3399 and rk3568 driversHeiko Stuebner3-10/+2
Both of these drivers were converted to real drivers and got a tristate build option. But them being builtin_platform_drivers, they only ever should be build-in - as the name suggests. So adapt the Kconfig symbol and drop the MODULE_* parts from the drivers. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20211027132616.1039814-3-heiko@sntech.de Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-11-02Revert "clk: rockchip: use module_platform_driver_probe"Heiko Stuebner2-2/+2
This reverts commit 1da80da028fe5accb866c0d6899a292ed86bef45. Reading recent discussions [0] [1], I realized this change introduces a number of problems: - only converting to module_platform_driver creates the issue with the existing __init and __initdata attributes. When the driver would've been built as a module, all the missing clock-definitions (all are initdata) should've turned up as error in testing suggesting that the change wasn't at all - a clock driver is a very core component of soc bringup and making this able to be built as a module solely for enabling the soc vendor to add out of tree changes for Android implementations is not in our interest and also everything except a ramdisk won't probe without a clock controller. This is especially true when the changes aren't really tested and are merely added to move the mainline driver "out of the way". [0] https://lwn.net/Articles/872209/ [1] https://lore.kernel.org/all/163529604399.15791.378104318036812951@swboyd.mtv.corp.google.com/ Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20211027132616.1039814-2-heiko@sntech.de Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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