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2019-04-16clocksource/drivers/timer-ti-dm: Remove omap_dm_timer_set_load_startNathan Chancellor1-28/+0
Commit 008258d995a6 ("clocksource/drivers/timer-ti-dm: Make omap_dm_timer_set_load_start() static") made omap_dm_time_set_load_start static because its prototype was not defined in a header. Unfortunately, this causes a build warning on multi_v7_defconfig because this function is not used anywhere in this translation unit: drivers/clocksource/timer-ti-dm.c:589:12: error: unused function 'omap_dm_timer_set_load_start' [-Werror,-Wunused-function] In fact, omap_dm_timer_set_load_start hasn't been used anywhere since commit f190be7f39a5 ("staging: tidspbridge: remove driver") and the prototype was removed in commit 592ea6bd1fad ("clocksource: timer-ti-dm: Make unexported functions static"), which is probably where this should have happened. Fixes: 592ea6bd1fad ("clocksource: timer-ti-dm: Make unexported functions static") Fixes: 008258d995a6 ("clocksource/drivers/timer-ti-dm: Make omap_dm_timer_set_load_start() static") Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2019-04-11clocksource/drivers/oxnas: Fix OX820 compatibleNeil Armstrong1-1/+1
The OX820 compatible is wrong is the driver, fix it. Fixes: 2ea3401e2a84 ("clocksource/drivers/oxnas: Add OX820 compatible") Reported-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2019-04-11clocksource/drivers/arm_arch_timer: Remove unneeded pr_fmt macroYangtao Li1-4/+1
After this commit ded24019b6b6f(clocksource: arm_arch_timer: clean up printk usage), the previous macro is redundant, so delete it. And move the new macro to the previous position. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2019-04-11clocksource/drivers/npcm: select TIMER_OFArnd Bergmann1-0/+1
When this is disabled, we get a link failure: drivers/clocksource/timer-npcm7xx.o: In function `npcm7xx_timer_init': timer-npcm7xx.c:(.init.text+0xf): undefined reference to `timer_of_init' Fixes: 1c00289ecd12 ("clocksource/drivers/npcm: Add NPCM7xx timer driver") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2019-03-24clocksource/drivers/clps711x: Remove board supportAlexander Shiyan1-32/+13
Since board support for the CLPS711X platform was removed, remove the board support from the clps711x-timer driver. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Arnd Bergmann <arnd@arndb.de> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lkml.kernel.org/r/20181220111626.17140-1-shc_work@mail.ru
2019-03-23clocksource/drivers/riscv: Fix clocksource maskAtish Patra1-3/+2
For all riscv architectures (RV32, RV64 and RV128), the clocksource is a 64 bit incrementing counter. Fix the clock source mask accordingly. Tested on both 64bit and 32 bit virt machine in QEMU. Fixes: 62b019436814 ("clocksource: new RISC-V SBI timer driver") Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Anup Patel <anup@brainfault.org> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: linux-riscv@lists.infradead.org Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Anup Patel <Anup.Patel@wdc.com> Cc: Damien Le Moal <Damien.LeMoal@wdc.com> Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20190322215411.19362-1-atish.patra@wdc.com
2019-03-22clocksource/drivers/mips-gic-timer: Make gic_compare_irqaction staticYueHaibing1-1/+1
Fix sparse warning: drivers/clocksource/mips-gic-timer.c:70:18: warning: symbol 'gic_compare_irqaction' was not declared. Should it be static? Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: <daniel.lezcano@linaro.org> Link: https://lkml.kernel.org/r/20190322144359.19516-1-yuehaibing@huawei.com
2019-03-22clocksource/drivers/timer-ti-dm: Make omap_dm_timer_set_load_start() staticYueHaibing1-2/+2
Fix sparse warning: drivers/clocksource/timer-ti-dm.c:589:5: warning: symbol 'omap_dm_timer_set_load_start' was not declared. Should it be static? Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: <daniel.lezcano@linaro.org> Link: https://lkml.kernel.org/r/20190322144302.6704-1-yuehaibing@huawei.com
2019-03-22clocksource/drivers/tcb_clksrc: Make tc_clksrc_suspend/resume() staticYueHaibing1-2/+2
Fix sparse warnings: drivers/clocksource/tcb_clksrc.c:74:6: warning: symbol 'tc_clksrc_suspend' was not declared. Should it be static? drivers/clocksource/tcb_clksrc.c:89:6: warning: symbol 'tc_clksrc_resume' was not declared. Should it be static? Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: <nicolas.ferre@microchip.com> Cc: <daniel.lezcano@linaro.org> Cc: <linux-arm-kernel@lists.infradead.org> Link: https://lkml.kernel.org/r/20190322143940.12396-1-yuehaibing@huawei.com
2019-03-22clocksource/drivers/clps711x: Make clps711x_clksrc_init() staticYueHaibing1-2/+3
Fix sparse warning: drivers/clocksource/clps711x-timer.c:96:13: warning: symbol 'clps711x_clksrc_init' was not declared. Should it be static? Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: <daniel.lezcano@linaro.org> Cc: <shc_work@mail.ru> Cc: <linux-arm-kernel@lists.infradead.org> Link: https://lkml.kernel.org/r/20190322143708.12716-1-yuehaibing@huawei.com
2019-03-15Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds1-2/+9
Pull KVM updates from Paolo Bonzini: "ARM: - some cleanups - direct physical timer assignment - cache sanitization for 32-bit guests s390: - interrupt cleanup - introduction of the Guest Information Block - preparation for processor subfunctions in cpu models PPC: - bug fixes and improvements, especially related to machine checks and protection keys x86: - many, many cleanups, including removing a bunch of MMU code for unnecessary optimizations - AVIC fixes Generic: - memcg accounting" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (147 commits) kvm: vmx: fix formatting of a comment KVM: doc: Document the life cycle of a VM and its resources MAINTAINERS: Add KVM selftests to existing KVM entry Revert "KVM/MMU: Flush tlb directly in the kvm_zap_gfn_range()" KVM: PPC: Book3S: Add count cache flush parameters to kvmppc_get_cpu_char() KVM: PPC: Fix compilation when KVM is not enabled KVM: Minor cleanups for kvm_main.c KVM: s390: add debug logging for cpu model subfunctions KVM: s390: implement subfunction processor calls arm64: KVM: Fix architecturally invalid reset value for FPEXC32_EL2 KVM: arm/arm64: Remove unused timer variable KVM: PPC: Book3S: Improve KVM reference counting KVM: PPC: Book3S HV: Fix build failure without IOMMU support Revert "KVM: Eliminate extra function calls in kvm_get_dirty_log_protect()" x86: kvmguest: use TSC clocksource if invariant TSC is exposed KVM: Never start grow vCPU halt_poll_ns from value below halt_poll_ns_grow_start KVM: Expose the initial start value in grow_halt_poll_ns() as a module parameter KVM: grow_halt_poll_ns() should never shrink vCPU halt_poll_ns KVM: x86/mmu: Consolidate kvm_mmu_zap_all() and kvm_mmu_zap_mmio_sptes() KVM: x86/mmu: WARN if zapping a MMIO spte results in zapping children ...
2019-03-06Merge tag 'armsoc-newsoc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds3-0/+171
Pull ARM new SoC family support from Arnd Bergmann: "Two new SoC families are added this time. Sugaya Taichi submitted support for the Milbeaut SoC family from Socionext and explains: "SC2000 is a SoC of the Milbeaut series. equipped with a DSP optimized for computer vision. It also features advanced functionalities such as 360-degree, real-time spherical stitching with multi cameras, image stabilization for without mechanical gimbals, and rolling shutter correction. More detail is below: https://www.socionext.com/en/products/assp/milbeaut/SC2000.html" Interestingly, this one has a history dating back to older chips made by Socionext and previously Matsushita/Panasonic based on their own mn10300 CPU architecture that was removed from the kernel last year. Manivannan Sadhasivam adds support for another SoC family, this is the Bitmain BM1880 chip used in the Sophon Edge TPU developer board. The chip is intended for Deep Learning applications, and comes with dual-core Arm Cortex-A53 to run Linux as well as a RISC-V microcontroller core to control the tensor unit. For the moment, the TPU is not accessible in mainline Linux, so we treat it as a generic Arm SoC. More information is available at https://www.sophon.ai/" * tag 'armsoc-newsoc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: ARM: multi_v7_defconfig: add ARCH_MILBEAUT and ARCH_MILBEAUT_M10V ARM: configs: Add Milbeaut M10V defconfig ARM: dts: milbeaut: Add device tree set for the Milbeaut M10V board clocksource/drivers/timer-milbeaut: Introduce timer for Milbeaut SoCs dt-bindings: timer: Add Milbeaut M10V timer description ARM: milbeaut: Add basic support for Milbeaut m10v SoC dt-bindings: Add documentation for Milbeaut SoCs dt-bindings: arm: Add SMP enable-method for Milbeaut dt-bindings: sram: milbeaut: Add binding for Milbeaut smp-sram MAINTAINERS: Add entry for Bitmain SoC platform arm64: dts: bitmain: Add Sophon Egde board support arm64: dts: bitmain: Add BM1880 SoC support arm64: Add ARCH_BITMAIN platform dt-bindings: arm: Document Bitmain BM1880 SoC
2019-03-05Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds10-139/+386
Pull timer and clockevent updates from Thomas Gleixner: "The time(r) core and clockevent updates are mostly boring this time: - A new driver for the Tegra210 timer - Small fixes and improvements alll over the place - Documentation updates and cleanups" * 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (22 commits) soc/tegra: default select TEGRA_TIMER for Tegra210 clocksource/drivers/tegra: Add Tegra210 timer support dt-bindings: timer: add Tegra210 timer clocksource/drivers/timer-cs5535: Rename the file for consistency clocksource/drivers/timer-pxa: Rename the file for consistency clocksource/drivers/tango-xtal: Rename the file for consistency dt-bindings: timer: gpt: update binding doc clocksource/drivers/exynos_mct: Remove unused header includes dt-bindings: timer: mediatek: update bindings for MT7629 SoC clocksource/drivers/exynos_mct: Fix error path in timer resources initialization clocksource/drivers/exynos_mct: Remove dead code clocksource/drivers/riscv: Add required checks during clock source init dt-bindings: timer: renesas: tmu: Document r8a774c0 bindings dt-bindings: timer: renesas, cmt: Document r8a774c0 CMT support clocksource/drivers/exynos_mct: Clear timer interrupt when shutdown clocksource/drivers/exynos_mct: Move one-shot check from tick clear to ISR clocksource/drivers/arch_timer: Workaround for Allwinner A64 timer instability clocksource/drivers/sun5i: Fail gracefully when clock rate is unavailable timers: Mark expected switch fall-throughs timekeeping/debug: No need to check return value of debugfs_create functions ...
2019-03-01clocksource/drivers/timer-milbeaut: Introduce timer for Milbeaut SoCsSugaya Taichi3-0/+171
Add timer driver for Milbeaut SoCs series. The timer has two 32-bit width down counters, one of which is configured as a clockevent device and the other is configured as a clock source. Signed-off-by: Sugaya Taichi <sugaya.taichi@socionext.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-23clocksource/drivers/tegra: Add Tegra210 timer supportJoseph Lo2-112/+261
Add support for the Tegra210 timer that runs at oscillator clock (TMR10-TMR13). We need these timers to work as clock event device and to replace the ARMv8 architected timer due to it can't survive across the power cycle of the CPU core or CPUPORESET signal. So it can't be a wake-up source when CPU suspends in power down state. Also convert the original driver to use timer-of API. Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-kernel@vger.kernel.org Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2019-02-23clocksource/drivers/timer-cs5535: Rename the file for consistencyDaniel Lezcano2-1/+1
For the sake of consistency, let's rename the file to a name similar to other file names in this directory. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2019-02-23clocksource/drivers/timer-pxa: Rename the file for consistencyDaniel Lezcano2-1/+1
For the sake of consistency, let's rename the file to a name similar to other file names in this directory. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2019-02-23clocksource/drivers/tango-xtal: Rename the file for consistencyDaniel Lezcano2-1/+1
For the sake of consistency, let's rename the file to a name similar to other file names in this directory. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2019-02-23clocksource/drivers/exynos_mct: Remove unused header includesKrzysztof Kozlowski1-2/+0
The driver does not use sched.h and platform_device.h. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2019-02-23clocksource/drivers/exynos_mct: Fix error path in timer resources initializationMarek Szyprowski1-1/+13
While freeing interrupt handlers in error path, don't assume that all requested interrupts are per-processor interrupts and properly release standard interrupts too. Reported-by: Krzysztof Kozlowski <krzk@kernel.org> Fixes: 56a94f13919c ("clocksource: exynos_mct: Avoid blocking calls in the cpu hotplug notifier") Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2019-02-23clocksource/drivers/exynos_mct: Remove dead codeMarek Szyprowski1-7/+2
Exynos Multi-Core Timer driver is used only on device-tree based systems, so remove non-dt related code. In case of !CONFIG_OF the code is anyway equal because of_irq_count() has a stub returning 0. Device node pointer is always provided when driver has been probed from device tree. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2019-02-23clocksource/drivers/riscv: Add required checks during clock source initAtish Patra1-3/+20
Currently, clocksource registration happens for an invalid cpu for non-smp kernels. This lead to kernel panic as cpu hotplug registration will fail for those cpus. Moreover, riscv_hartid_to_cpuid can return errors now. Do not proceed if hartid or cpuid is invalid. Take this opportunity to print appropriate error strings for different failure cases. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2019-02-23clocksource/drivers/exynos_mct: Clear timer interrupt when shutdownStuart Menefy1-0/+1
When shutting down the timer, ensure that after we have stopped the timer any pending interrupts are cleared. This fixes a problem when suspending, as interrupts are disabled before the timer is stopped, so the timer interrupt may still be asserted, preventing the system entering a low power state when the wfi is executed. Signed-off-by: Stuart Menefy <stuart.menefy@mathembedded.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Cc: <stable@vger.kernel.org> # v4.3+ Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2019-02-23clocksource/drivers/exynos_mct: Move one-shot check from tick clear to ISRStuart Menefy1-11/+11
When a timer tick occurs and the clock is in one-shot mode, the timer needs to be stopped to prevent it triggering subsequent interrupts. Currently this code is in exynos4_mct_tick_clear(), but as it is only needed when an ISR occurs move it into exynos4_mct_tick_isr(), leaving exynos4_mct_tick_clear() just doing what its name suggests it should. Signed-off-by: Stuart Menefy <stuart.menefy@mathembedded.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Cc: stable@vger.kernel.org # v4.3+ Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2019-02-23clocksource/drivers/arch_timer: Workaround for Allwinner A64 timer instabilitySamuel Holland2-0/+65
The Allwinner A64 SoC is known[1] to have an unstable architectural timer, which manifests itself most obviously in the time jumping forward a multiple of 95 years[2][3]. This coincides with 2^56 cycles at a timer frequency of 24 MHz, implying that the time went slightly backward (and this was interpreted by the kernel as it jumping forward and wrapping around past the epoch). Investigation revealed instability in the low bits of CNTVCT at the point a high bit rolls over. This leads to power-of-two cycle forward and backward jumps. (Testing shows that forward jumps are about twice as likely as backward jumps.) Since the counter value returns to normal after an indeterminate read, each "jump" really consists of both a forward and backward jump from the software perspective. Unless the kernel is trapping CNTVCT reads, a userspace program is able to read the register in a loop faster than it changes. A test program running on all 4 CPU cores that reported jumps larger than 100 ms was run for 13.6 hours and reported the following: Count | Event -------+--------------------------- 9940 | jumped backward 699ms 268 | jumped backward 1398ms 1 | jumped backward 2097ms 16020 | jumped forward 175ms 6443 | jumped forward 699ms 2976 | jumped forward 1398ms 9 | jumped forward 356516ms 9 | jumped forward 357215ms 4 | jumped forward 714430ms 1 | jumped forward 3578440ms This works out to a jump larger than 100 ms about every 5.5 seconds on each CPU core. The largest jump (almost an hour!) was the following sequence of reads: 0x0000007fffffffff → 0x00000093feffffff → 0x0000008000000000 Note that the middle bits don't necessarily all read as all zeroes or all ones during the anomalous behavior; however the low 10 bits checked by the function in this patch have never been observed with any other value. Also note that smaller jumps are much more common, with backward jumps of 2048 (2^11) cycles observed over 400 times per second on each core. (Of course, this is partially explained by lower bits rolling over more frequently.) Any one of these could have caused the 95 year time skip. Similar anomalies were observed while reading CNTPCT (after patching the kernel to allow reads from userspace). However, the CNTPCT jumps are much less frequent, and only small jumps were observed. The same program as before (except now reading CNTPCT) observed after 72 hours: Count | Event -------+--------------------------- 17 | jumped backward 699ms 52 | jumped forward 175ms 2831 | jumped forward 699ms 5 | jumped forward 1398ms Further investigation showed that the instability in CNTPCT/CNTVCT also affected the respective timer's TVAL register. The following values were observed immediately after writing CNVT_TVAL to 0x10000000: CNTVCT | CNTV_TVAL | CNTV_CVAL | CNTV_TVAL Error --------------------+------------+--------------------+----------------- 0x000000d4a2d8bfff | 0x10003fff | 0x000000d4b2d8bfff | +0x00004000 0x000000d4a2d94000 | 0x0fffffff | 0x000000d4b2d97fff | -0x00004000 0x000000d4a2d97fff | 0x10003fff | 0x000000d4b2d97fff | +0x00004000 0x000000d4a2d9c000 | 0x0fffffff | 0x000000d4b2d9ffff | -0x00004000 The pattern of errors in CNTV_TVAL seemed to depend on exactly which value was written to it. For example, after writing 0x10101010: CNTVCT | CNTV_TVAL | CNTV_CVAL | CNTV_TVAL Error --------------------+------------+--------------------+----------------- 0x000001ac3effffff | 0x1110100f | 0x000001ac4f10100f | +0x1000000 0x000001ac40000000 | 0x1010100f | 0x000001ac5110100f | -0x1000000 0x000001ac58ffffff | 0x1110100f | 0x000001ac6910100f | +0x1000000 0x000001ac66000000 | 0x1010100f | 0x000001ac7710100f | -0x1000000 0x000001ac6affffff | 0x1110100f | 0x000001ac7b10100f | +0x1000000 0x000001ac6e000000 | 0x1010100f | 0x000001ac7f10100f | -0x1000000 I was also twice able to reproduce the issue covered by Allwinner's workaround[4], that writing to TVAL sometimes fails, and both CVAL and TVAL are left with entirely bogus values. One was the following values: CNTVCT | CNTV_TVAL | CNTV_CVAL --------------------+------------+-------------------------------------- 0x000000d4a2d6014c | 0x8fbd5721 | 0x000000d132935fff (615s in the past) Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> ======================================================================== Because the CPU can read the CNTPCT/CNTVCT registers faster than they change, performing two reads of the register and comparing the high bits (like other workarounds) is not a workable solution. And because the timer can jump both forward and backward, no pair of reads can distinguish a good value from a bad one. The only way to guarantee a good value from consecutive reads would be to read _three_ times, and take the middle value only if the three values are 1) each unique and 2) increasing. This takes at minimum 3 counter cycles (125 ns), or more if an anomaly is detected. However, since there is a distinct pattern to the bad values, we can optimize the common case (1022/1024 of the time) to a single read by simply ignoring values that match the error pattern. This still takes no more than 3 cycles in the worst case, and requires much less code. As an additional safety check, we still limit the loop iteration to the number of max-frequency (1.2 GHz) CPU cycles in three 24 MHz counter periods. For the TVAL registers, the simple solution is to not use them. Instead, read or write the CVAL and calculate the TVAL value in software. Although the manufacturer is aware of at least part of the erratum[4], there is no official name for it. For now, use the kernel-internal name "UNKNOWN1". [1]: https://github.com/armbian/build/commit/a08cd6fe7ae9 [2]: https://forum.armbian.com/topic/3458-a64-datetime-clock-issue/ [3]: https://irclog.whitequark.org/linux-sunxi/2018-01-26 [4]: https://github.com/Allwinner-Homlet/H6-BSP4.9-linux/blob/master/drivers/clocksource/arm_arch_timer.c#L272 Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Tested-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Cc: stable@vger.kernel.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2019-02-23clocksource/drivers/sun5i: Fail gracefully when clock rate is unavailableChen-Yu Tsai1-0/+10
If the clock tree is not fully populated when the timer-sun5i init code is called, attempts to get the clock rate for the timer would fail and return 0. Make the init code for both clock events and clocksource check the returned clock rate and fail gracefully if the result is 0, instead of causing a divide by 0 exception later on. Fixes: 4a59058f0b09 ("clocksource/drivers/sun5i: Refactor the current code") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2019-02-19clocksource/arm_arch_timer: Store physical timer IRQ number for KVM on VHEAndre Przywara1-2/+9
A host running in VHE mode gets the EL2 physical timer as its time source (accessed using the EL1 sysreg accessors, which get re-directed to the EL2 sysregs by VHE). The EL1 physical timer remains unused by the host kernel, allowing us to pass that on directly to a KVM guest and saves us from emulating this timer for the guest on VHE systems. Store the EL1 Physical Timer's IRQ number in struct arch_timer_kvm_info on VHE systems to allow KVM to use it. Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@arm.com>
2019-01-29Merge branch 'pwm-dmtimer-fixes' into omap-for-v5.0/fixes-v2Tony Lindgren1-1/+4
2019-01-29bus: ti-sysc: Fix timer handling with drop pm_runtime_irq_safe()Tony Lindgren1-1/+0
Commit 84badc5ec5fc ("ARM: dts: omap4: Move l4 child devices to probe them with ti-sysc") started producing a warning for pwm-omap-dmtimer: WARNING: CPU: 0 PID: 77 at drivers/bus/omap_l3_noc.c:147 l3_interrupt_handler+0x2f8/0x388 44000000.ocp:L3 Custom Error: MASTER MPU TARGET L4PER2 (Idle): Data Access in Supervisor mode during Functional access ... __pm_runtime_idle omap_dm_timer_disable pwm_omap_dmtimer_start pwm_omap_dmtimer_enable pwm_apply_state pwm_vibrator_start pwm_vibrator_play_work This is because the timer that pwm-omap-dmtimer is using is now being probed with ti-sysc interconnect target module instead of omap_device and the ti-sysc quirk for SYSC_QUIRK_LEGACY_IDLE is not fully compatible with what omap_device has been doing. We could fix this by reverting the timer changes and have the timer probe again with omap_device. Or we could add more quirk handling to ti-sysc driver. But as these options don't work nicely as longer term solutions, let's just make timers probe with ti-sysc without any quirks. To do this, all we need to do is remove quirks for timers for ti-sysc, and drop the bogus pm_runtime_irq_safe() flag for timer-ti-dm. We should not use pm_runtime_irq_safe() anyways for drivers as it will take a permanent use count on the parent device blocking the parent devices from idling and has been forcing ti-sysc driver to use a quirk flag. Note that we will move the timer data to DEBUG section later on in clean-up patches. Fixes: 84badc5ec5fc ("ARM: dts: omap4: Move l4 child devices to probe them with ti-sysc") Cc: Andy Shevchenko <andy.shevchenko@gmail.com> Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: H. Nikolaus Schaller <hns@goldelico.com> Cc: Keerthy <j-keerthy@ti.com> Cc: Ladislav Michl <ladis@linux-mips.org> Cc: Pavel Machek <pavel@ucw.cz> Cc: Sebastian Reichel <sre@kernel.org> Cc: Tero Kristo <t-kristo@ti.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Thomas Gleixner <tglx@linutronix.de> Reported-by: H. Nikolaus Schaller <hns@goldelico.com> Tested-By: Andreas Kemnade <andreas@kemnade.info> Tested-By: H. Nikolaus Schaller <hns@goldelico.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-01-22clocksource: timer-ti-dm: Fix pwm dmtimer usage of fck reparentingTony Lindgren1-0/+4
Commit 84badc5ec5fc ("ARM: dts: omap4: Move l4 child devices to probe them with ti-sysc") moved some omap4 timers to probe with ti-sysc interconnect target module. Turns out this broke pwm-omap-dmtimer where we now try to reparent the clock to itself with the following: omap_dm_timer_of_set_source: failed to set parent With ti-sysc, we can now configure the clock sources in the dts with assigned-clocks and assigned-clock-parents. So we should be able to remove omap_dm_timer_of_set_source with clean-up patches later on. But for now, let's just fix it first by checking if parent and fck are the same and bail out of so. Fixes: 84badc5ec5fc ("ARM: dts: omap4: Move l4 child devices to probe them with ti-sysc") Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: H. Nikolaus Schaller <hns@goldelico.com> Cc: Keerthy <j-keerthy@ti.com> Cc: Ladislav Michl <ladis@linux-mips.org> Cc: Pavel Machek <pavel@ucw.cz> Cc: Sebastian Reichel <sre@kernel.org> Cc: Tero Kristo <t-kristo@ti.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Thomas Gleixner <tglx@linutronix.de> Reported-by: H. Nikolaus Schaller <hns@goldelico.com> Tested-By: Andreas Kemnade <andreas@kemnade.info> Tested-By: H. Nikolaus Schaller <hns@goldelico.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-01-05Merge tag 'csky-for-linus-4.21' of git://github.com/c-sky/csky-linuxLinus Torvalds1-3/+3
Pull arch/csky updates from Guo Ren: "Here are three main features (cpu_hotplug, basic ftrace, basic perf) and some bugfixes: Features: - Add CPU-hotplug support for SMP - Add ftrace with function trace and function graph trace - Add Perf support - Add EM_CSKY_OLD 39 - optimize kernel panic print. - remove syscall_exit_work Bugfixes: - fix abiv2 mmap(... O_SYNC) failure - fix gdb coredump error - remove vdsp implement for kernel - fix qemu failure to bootup sometimes - fix ftrace call-graph panic - fix device tree node reference leak - remove meaningless header-y - fix save hi,lo,dspcr regs in switch_stack - remove unused members in processor.h" * tag 'csky-for-linus-4.21' of git://github.com/c-sky/csky-linux: csky: Add perf support for C-SKY csky: Add EM_CSKY_OLD 39 clocksource/drivers/c-sky: fixup ftrace call-graph panic csky: ftrace call graph supported. csky: basic ftrace supported csky: remove unused members in processor.h csky: optimize kernel panic print. csky: stacktrace supported. csky: CPU-hotplug supported for SMP clocksource/drivers/c-sky: fixup qemu fail to bootup sometimes. csky: fixup save hi,lo,dspcr regs in switch_stack. csky: remove syscall_exit_work csky: fixup remove vdsp implement for kernel. csky: bugfix gdb coredump error. csky: fixup abiv2 mmap(... O_SYNC) failed. csky: define syscall_get_arch() elf-em.h: add EM_CSKY csky: remove meaningless header-y csky: Don't leak device tree node reference
2018-12-31clocksource/drivers/c-sky: fixup ftrace call-graph panicGuo Ren1-1/+1
We must add notrace on sched_clock_read, because it's called by ftrace_graph_caller. Signed-off-by: Guo Ren <ren_guo@c-sky.com>
2018-12-31clocksource/drivers/c-sky: fixup qemu fail to bootup sometimes.Guo Ren1-2/+2
Timer startup must after timer_irq_enable. For qemu, timer tick irq hanppens but irq not enable, so it will cause qemu boot failed. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Tested-by: Liu Zhiwei <zhiwei_liu@c-sky.com>
2018-12-25Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds19-377/+587
Pull timer updates from Thomas Gleixner: "The timer department delivers the following christmas presents: Core code: - Use proper seqcount initializer to make lockdep happy - SPDX annotations and cleanup of license boilerplates - Use DEFINE_SHOW_ATTRIBUTE() instead of open coding it - Minor cleanups Driver code: - Add the sched_clock for the arc timer (Alexey Brodkin) - Change the file timer names for riscv, rockchip, tegra20, sun4i and meson6 (Daniel Lezcano) - Add the DT bindings for r8a7796, r8a77470 and r8a774a1 (Biju Das) - Remove the early platform driver registration for timer-ti-dm (Bartosz Golaszewski) - Provide the sched_clock for the riscv timer (Anup Patel) - Add support for ARM64 for the imx-gpt and convert the imx-tpm to the timer-of API (Anson Huang) - Remove useless irq protection for the imx-gpt (Clément Péron) - Remove a duplicate function name for the vt8500 (Dan Carpenter) - Remove obsolete inclusion of <asm/smp_twd.h> for the tegra20 (Geert Uytterhoeven) - Demote the prcmu and the custom sched_clock for the dbx500 and the ux500 (Linus Walleij) - Add a new timer clock for the RDA8810PL (Manivannan Sadhasivam) - Rename the macro to stick to the register name and add the delay timer (Martin Blumenstingl) - Switch the bcm2835 to the SPDX identifier (Stefan Wahren) - Fix the interrupt register access on the fttmr010 (Tao Ren) - Add missing of_node_put in the initialization path on the integrator-ap (Yangtao Li)" * 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (39 commits) dt-bindings: timer: Document RDA8810PL SoC timer clocksource/drivers/rda: Add clock driver for RDA8810PL SoC clocksource/drivers/meson6: Change name meson6_timer timer-meson6 clocksource/drivers/sun4i: Change name sun4i_timer to timer-sun4i clocksource/drivers/tegra20: Change name tegra20_timer to timer-tegra20 clocksource/drivers/rockchip: Change name rockchip_timer to timer-rockchip clocksource/drivers/riscv: Change name riscv_timer to timer-riscv clocksource/drivers/riscv_timer: Provide the sched_clock clocksource/drivers/timer-imx-tpm: Specify clock name for timer-of clocksource/drivers/fttmr010: Fix invalid interrupt register access clocksource/drivers/integrator-ap: Add missing of_node_put() clocksource/drivers/bcm2835: Switch to SPDX identifier dt-bindings: timer: renesas, cmt: Document r8a774a1 CMT support clocksource/drivers/timer-imx-tpm: Convert the driver to timer-of clocksource/drivers/arc_timer: Utilize generic sched_clock dt-bindings: timer: renesas, cmt: Document r8a77470 CMT support dt-bindings: timer: renesas, cmt: Document r8a7796 CMT support clocksource/drivers/imx-gpt: Remove unnecessary irq protection clocksource/drivers/imx-gpt: Add support for ARM64 clocksource/drivers/meson6_timer: Implement the ARM delay timer ...
2018-12-18clocksource/drivers/rda: Add clock driver for RDA8810PL SoCManivannan Sadhasivam3-0/+204
Add clock driver for RDA Micro RDA8810PL SoC supporting OSTIMER and HWTIMER. RDA8810PL has two independent timers: OSTIMER (56 bit) and HWTIMER (64 bit). Each timer provides optional interrupt support. In this driver, OSTIMER is used for clockevents and HWTIMER is used for clocksource. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2018-12-18clocksource/drivers/meson6: Change name meson6_timer timer-meson6Daniel Lezcano2-1/+1
In order to unify the names in this directory, let's rename the driver to be prefixed with timer-* Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2018-12-18clocksource/drivers/sun4i: Change name sun4i_timer to timer-sun4iDaniel Lezcano2-1/+1
In order to unify the names in this directory, let's rename the driver to be prefixed with timer-* Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2018-12-18clocksource/drivers/tegra20: Change name tegra20_timer to timer-tegra20Daniel Lezcano2-1/+1
In order to unify the names in this directory, let's rename the driver to be prefixed with timer-* Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2018-12-18clocksource/drivers/rockchip: Change name rockchip_timer to timer-rockchipDaniel Lezcano2-1/+1
In order to unify the names in this directory, let's rename the driver to be prefixed with timer-* Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2018-12-18clocksource/drivers/riscv: Change name riscv_timer to timer-riscvDaniel Lezcano2-1/+1
In order to unify the names in this directory, let's rename the driver to be prefixed with timer-* Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2018-12-18clocksource/drivers/riscv_timer: Provide the sched_clockAnup Patel2-1/+10
Currently, we don't have a sched_clock registered for RISC-V systems. This means Linux time keeping will use jiffies (running at HZ) as the default sched_clock. To avoid this, we explicity provide sched_clock using RISC-V rdtime instruction (similar to riscv_timer clocksource). Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2018-12-18clocksource/drivers/timer-imx-tpm: Specify clock name for timer-ofAnson Huang1-0/+3
i.MX TPM needs "ipg" clock for register access and "per" clock for timer function, the driver gets "ipg" clock by searching the clock name, but timer-of initialization will get first clock in device tree TPM node since no clock name specified in of_clk, that means the "per" clock MUST be the first clock entry in device tree TPM node, this patch specifies clock name for of_clk to avoid this restriction, it makes TPM driver work properly with different sequence of clock entries in device tree TPM node. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2018-12-18clocksource/drivers/fttmr010: Fix invalid interrupt register accessTao Ren1-31/+42
TIMER_INTR_MASK register (Base Address of Timer + 0x38) is not designed for masking interrupts on ast2500 chips, and it's not even listed in ast2400 datasheet, so it's not safe to access TIMER_INTR_MASK on aspeed chips. Similarly, TIMER_INTR_STATE register (Base Address of Timer + 0x34) is not interrupt status register on ast2400 and ast2500 chips. Although there is no side effect to reset the register in fttmr010_common_init(), it's just misleading to do so. Besides, "count_down" is renamed to "is_aspeed" in "fttmr010" structure, and more comments are added so the code is more readble. Signed-off-by: Tao Ren <taoren@fb.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2018-12-18clocksource/drivers/integrator-ap: Add missing of_node_put()Yangtao Li1-9/+16
The function of_find_node_by_path() acquires a reference to the node returned by it and that reference needs to be dropped by its caller. integrator_ap_timer_init_of() doesn't do that. The pri_node and the sec_node are used as an identifier to compare against the current node, so we can directly drop the refcount after getting the node from the path as it is not used as pointer. By dropping the refcount right after getting it, a single variable is needed instead of two. Fix this by use a single variable and drop the refcount right after of_find_node_by_path(). Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2018-12-18clocksource/drivers/bcm2835: Switch to SPDX identifierStefan Wahren1-14/+1
Adopt the SPDX license identifier headers to ease license compliance management. Also drop the FSF address. Cc: Simon Arlott <simon@arlott.org> Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2018-12-18clocksource/drivers/timer-imx-tpm: Convert the driver to timer-ofAnson Huang1-81/+55
Convert the driver to use the timer_of helpers. This allows to handle timer base, clock and irq using common timer_of driver and it simplifies the code. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2018-12-18clocksource/drivers/arc_timer: Utilize generic sched_clockAlexey Brodkin2-0/+23
It turned out we used to use default implementation of sched_clock() from kernel/sched/clock.c which was as precise as 1/HZ, i.e. by default we had 10 msec granularity of time measurement. Now given ARC built-in timers are clocked with the same frequency as CPU cores we may get much higher precision of time tracking. Thus we switch to generic sched_clock which really reads ARC hardware counters. This is especially helpful for measuring short events. That's what we used to have: ------------------------------>8------------------------ $ perf stat /bin/sh -c /root/lmbench-master/bin/arc/hello > /dev/null Performance counter stats for '/bin/sh -c /root/lmbench-master/bin/arc/hello': 10.000000 task-clock (msec) # 2.832 CPUs utilized 1 context-switches # 0.100 K/sec 1 cpu-migrations # 0.100 K/sec 63 page-faults # 0.006 M/sec 3049480 cycles # 0.305 GHz 1091259 instructions # 0.36 insn per cycle 256828 branches # 25.683 M/sec 27026 branch-misses # 10.52% of all branches 0.003530687 seconds time elapsed 0.000000000 seconds user 0.010000000 seconds sys ------------------------------>8------------------------ And now we'll see: ------------------------------>8------------------------ $ perf stat /bin/sh -c /root/lmbench-master/bin/arc/hello > /dev/null Performance counter stats for '/bin/sh -c /root/lmbench-master/bin/arc/hello': 3.004322 task-clock (msec) # 0.865 CPUs utilized 1 context-switches # 0.333 K/sec 1 cpu-migrations # 0.333 K/sec 63 page-faults # 0.021 M/sec 2986734 cycles # 0.994 GHz 1087466 instructions # 0.36 insn per cycle 255209 branches # 84.947 M/sec 26002 branch-misses # 10.19% of all branches 0.003474829 seconds time elapsed 0.003519000 seconds user 0.000000000 seconds sys ------------------------------>8------------------------ Note how much more meaningful is the second output - time spent for execution pretty much matches number of cycles spent (we're runnign @ 1GHz here). Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: stable@vger.kernel.org Acked-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2018-12-18clocksource/drivers/imx-gpt: Remove unnecessary irq protectionClément Péron1-17/+0
shutdown and oneshot are already protected against irq interruptions Signed-off-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2018-12-18clocksource/drivers/imx-gpt: Add support for ARM64Anson Huang2-1/+5
This patch allows building and compile-testing the i.MX GPT driver also for ARM64. The delay_timer is only supported on ARMv7. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2018-12-18clocksource/drivers/meson6_timer: Implement the ARM delay timerMartin Blumenstingl1-0/+22
Implement an ARM delay timer to be used for udelay(). This allows us to skip the delay loop calibration at boot. With this patch udelay() is now independent of CPU frequency changes. This is a good thing on Meson8, Meson8b and Meson8m2 because changing the CPU frequency requires running the CPU clock off the XTAL while changing the PLL or it's dividers. After changing the CPU clocks we need to wait a few usecs for the clock to become stable. So having an udelay() implementation that doesn't depend on the CPU frequency is beneficial. Suggested-by: Jianxin Pan <jianxin.pan@amlogic.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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