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2016-05-19Merge tag 'dmaengine-4.7-rc1' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds1-1/+10
Pull dmaengine updates from Vinod Koul: "This time round the update brings in following changes: - new tegra driver for ADMA device - support for Xilinx AXI Direct Memory Access Engine and Xilinx AXI Central Direct Memory Access Engine and few updates to this driver - new cyclic capability to sun6i and few updates - slave-sg support in bcm2835 - updates to many drivers like designware, hsu, mv_xor, pxa, edma, qcom_hidma & bam" * tag 'dmaengine-4.7-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (84 commits) dmaengine: ioatdma: disable relaxed ordering for ioatdma dmaengine: of_dma: approximate an average distribution dmaengine: core: Use IS_ENABLED() instead of checking for built-in or module dmaengine: edma: Re-evaluate errors when ccerr is triggered w/o error event dmaengine: qcom_hidma: add support for object hierarchy dmaengine: qcom_hidma: add debugfs hooks dmaengine: qcom_hidma: implement lower level hardware interface dmaengine: vdma: Add clock support Documentation: DT: vdma: Add clock support for dmas dmaengine: vdma: Add config structure to differentiate dmas MAINTAINERS: Update Tegra DMA maintainers dmaengine: tegra-adma: Add support for Tegra210 ADMA Documentation: DT: Add binding documentation for NVIDIA ADMA dmaengine: vdma: Add Support for Xilinx AXI Central Direct Memory Access Engine Documentation: DT: vdma: update binding doc for AXI CDMA dmaengine: vdma: Add Support for Xilinx AXI Direct Memory Access Engine Documentation: DT: vdma: update binding doc for AXI DMA dmaengine: vdma: Rename xilinx_vdma_ prefix to xilinx_dma dmaengine: slave means at least one of DMA_SLAVE, DMA_CYCLIC dmaengine: mv_xor: Allow selecting mv_xor for mvebu only compatible SoC ...
2016-05-14dmaengine: edma: Re-evaluate errors when ccerr is triggered w/o error eventPeter Ujfalusi1-1/+10
When the ccerr handler is called but the error registers indicate no error events we need to command eDMA to re-evaluate the errors. Otherwise we can receive flood of error interrupts. Reported-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-04-06dmaengine: edma: special case slot limit workaroundJohn Ogness1-3/+22
Currently drivers are limited to 19 slots for cyclic transfers. However, if the DMA burst size is the same as the period size, the period size can be changed to the full buffer size and intermediate interrupts activated. Since intermediate interrupts will trigger for each burst and the burst size is the same as the period size, the driver will get interrupts each period as expected. This has the benefit of allowing the functionality of many more slots, but only uses 2 slots. This workaround is only active if more than 19 slots are needed and the burst size matches the period size. Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: John Ogness <john.ogness@linutronix.de> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-04-06dmaengine: edma: Remove dynamic TPTC power management featurePeter Ujfalusi1-35/+3
The dynamic or on demand pm_runtime does not work correctly on am335x and am437x due to interference with hwmod. Fall back using the pm_runtime usage as it was in the old driver stack, meaning that at probe time call pm_runtime_enable() and pm_runtime_get_sync() for the TPTCs as well. Fixes: 1be5336bc7ba ("dmaengine: edma: New device tree binding") Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Reported-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-03-17Merge tag 'dmaengine-4.6-rc1' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds1-27/+36
Pull dmaengine updates from Vinod Koul: "This is smallish update with minor changes to core and new driver and usual updates. Nothing super exciting here.. - We have made slave address as physical to enable driver to do the mapping. - We now expose the maxburst for slave dma as new capability so clients can know this and program accordingly - addition of device synchronize callbacks on omap and edma. - pl330 updates to support DMAFLUSHP for Rockchip platforms. - Updates and improved sg handling in Xilinx VDMA driver. - New hidma qualcomm dma driver, though some bits are still in progress" * tag 'dmaengine-4.6-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (40 commits) dmaengine: IOATDMA: revise channel reset workaround on CB3.3 platforms dmaengine: add Qualcomm Technologies HIDMA channel driver dmaengine: add Qualcomm Technologies HIDMA management driver dmaengine: hidma: Add Device Tree binding dmaengine: qcom_bam_dma: move to qcom directory dmaengine: tegra: Move of_device_id table near to its user dmaengine: xilinx_vdma: Remove unnecessary variable initializations dmaengine: sirf: use __maybe_unused to hide pm functions dmaengine: rcar-dmac: clear pertinence number of channels dmaengine: sh: shdmac: don't open code of_device_get_match_data() dmaengine: tegra: don't open code of_device_get_match_data() dmaengine: qcom_bam_dma: Make driver work for BE dmaengine: sun4i: support module autoloading dma/mic_x100_dma: IS_ERR() vs PTR_ERR() typo dmaengine: xilinx_vdma: Use readl_poll_timeout instead of do while loop's dmaengine: xilinx_vdma: Simplify spin lock handling dmaengine: xilinx_vdma: Fix issues with non-parking mode dmaengine: xilinx_vdma: Improve SG engine handling dmaengine: pl330: fix to support the burst mode dmaengine: make slave address physical ...
2016-02-22dmaengine: edma: Fetch echan->edesc while holding lock in edma_comletion_handlerPeter Ujfalusi1-27/+27
In order to avoid possible race condition when client drivers are using dmaengine_terminate_sync() call to disable the channel. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Suggested-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-02-22dmaengine: edma: Implement device_synchronize callbackPeter Ujfalusi1-0/+9
We need the callback to support the dmaengine_terminate_sync(). Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-02-08dmaengine: edma: fix residue race for cyclicJohn Ogness1-1/+40
When retrieving the residue value, the SRC/DST fields of the active PaRAM are read to determine the current position of the DMA engine. However, the AM335x Technical Reference Manual states: 11.3.3.6 Parameter Set Updates After the TR is read from the PaRAM (and is in the process of being submitted to the EDMA3TC), the following fields are updated as needed: ... SRC DST This means SRC/DST is incremented even though the DMA transfer may not have started yet or is in progress. Thus if the reader of the residue accesses the DMA buffer too quickly, the CPU is misinformed about the data that has been successfully processed. The CCSTAT.ACTV register is a boolean that is set if any TR is being processed by either the EMDA3CC or EDMA3TC. By polling this register it is possible to ensure that the residue value returned is valid for immediate processing. However, since the DMA engine may be active, polling may never hit a moment where no TR is being processed. To handle this, the SRC/DST is also polled to see if it changes. And as a last resort, a max loop count for the busy waiting exists to avoid an infinite loop. Signed-off-by: John Ogness <john.ogness@linutronix.de> Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-01-20Merge tag 'dmaengine-fix-4.5-rc1' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds1-1/+1
Pull dmaengine fixes from Vinod Koul: "Here is my second pull request for this window: A few driver fixes have piled up and one missed rcar bindings patch which got somehow lost in for-linus branch so cherry-picked that one. Fixes are for dw, at_hdmac, edma" * tag 'dmaengine-fix-4.5-rc1' of git://git.infradead.org/users/vkoul/slave-dma: dmaengine: rcar-dmac: Document SoC specific bindings dmaengine: at_xdmac: fix resume for cyclic transfers dmaengine: dw: fix cyclic transfer callbacks dmaengine: dw: fix cyclic transfer setup dmaengine: edma: Fix paRAM slot allocation for entry channel 0
2016-01-13Merge tag 'dmaengine-4.5-rc1' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds1-0/+10
Pull dmaengine updates from Vinod Koul: "This round we have few new features, new driver and updates to few drivers. The new features to dmaengine core are: - Synchronized transfer termination API to terminate the dmaengine transfers in synchronized and async fashion as required by users. We have its user now in ALSA dmaengine lib, img, at_xdma, axi_dmac drivers. - Universal API for channel request and start consolidation of request flows. It's user is ompa-dma driver. - Introduce reuse of descriptors and use in pxa_dma driver Add/Remove: - New STM32 DMA driver - Removal of unused R-Car HPB-DMAC driver Updates: - ti-dma-crossbar updates for supporting eDMA - tegra-apb pm updates - idma64 - mv_xor updates - ste_dma updates" * tag 'dmaengine-4.5-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (54 commits) dmaengine: mv_xor: add suspend/resume support dmaengine: mv_xor: de-duplicate mv_chan_set_mode*() dmaengine: mv_xor: remove mv_xor_chan->current_type field dmaengine: omap-dma: Add support for DMA filter mapping to slave devices dmaengine: edma: Add support for DMA filter mapping to slave devices dmaengine: core: Introduce new, universal API to request a channel dmaengine: core: Move and merge the code paths using private_candidate dmaengine: core: Skip mask matching when it is not provided to private_candidate dmaengine: mdc: Correct terminate_all handling dmaengine: edma: Add probe callback to edma_tptc_driver dmaengine: dw: fix potential memory leak in dw_dma_parse_dt() dmaengine: stm32-dma: Fix unchecked deference of chan->desc dmaengine: sh: Remove unused R-Car HPB-DMAC driver dmaengine: usb-dmac: Document SoC specific compatibility strings ste_dma40: Delete an unnecessary variable initialisation in d40_probe() ste_dma40: Delete another unnecessary check in d40_probe() ste_dma40: Delete an unnecessary check before the function call "kmem_cache_destroy" dmaengine: tegra-apb: Free interrupts before killing tasklets dmaengine: tegra-apb: Update driver to use GFP_NOWAIT dmaengine: tegra-apb: Only save channel state for those in use ...
2016-01-13dmaengine: edma: Fix paRAM slot allocation for entry channel 0Peter Ujfalusi1-1/+1
edma_alloc_slot was not checking the channel mapping support existence when slot 0 has been requested (used as entry slot for channel/event 0). Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-01-06Merge branch 'topic/univ_api' into for-linusVinod Koul1-0/+4
2015-12-18dmaengine: edma: Add support for DMA filter mapping to slave devicesPeter Ujfalusi1-0/+4
Add support for providing device to filter_fn mapping so client drivers can switch to use the dma_request_chan() API. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-12-18dmaengine: edma: Add probe callback to edma_tptc_driverPeter Ujfalusi1-0/+6
Due to changes in device and platform code drivers w/o probe will fail to load. This means that the devices for eDMA TPTCs are goign to be without driver and omap hwmod code will turn them off after the kernel finished loading: [ 3.015900] platform 49800000.tptc: omap_device_late_idle: enabled but no driver. Idling [ 3.024671] platform 49a00000.tptc: omap_device_late_idle: enabled but no driver. Idling This will prevent eDMA to work since the TPTCs are not enabled. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Fixes: 34635b1accb9 ("dmaengine: edma: Add dummy driver skeleton for edma3-tptc") Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-12-10Merge branch 'fix/edma' into fixesVinod Koul1-18/+35
2015-12-10dmaengine: edma: DT: Change reserved slot array from 16bit to 32bit typePeter Ujfalusi1-6/+25
This change makes the DT file to be easier to read since the reserved slots array does not need the '/bits/ 16' to be specified, which might confuse some people. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-12-10dmaengine: edma: DT: Change memcpy channel array from 16bit to 32bit typePeter Ujfalusi1-12/+10
This change makes the DT file to be easier to read since the memcpy channels array does not need the '/bits/ 16' to be specified, which might confuse some people. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-11-16dmaengine: edma: predecence bug in GET_NUM_QDMACH()Dan Carpenter1-1/+1
The current code uses bits 0-2 instead of 4-6 as the comment says. Fixes: 633e42b8c546 ('dmaengine: edma: Get qDMA channel information from HW also') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-11-16dmaengine: edma: fix build without CONFIG_OFArnd Bergmann1-1/+1
During the edma rework, a build error was introduced for the case that CONFIG_OF is disabled: drivers/built-in.o: In function `edma_tc_set_pm_state': :(.text+0x43bf0): undefined reference to `of_find_device_by_node' As the edma_tc_set_pm_state() function does nothing in case we are running without OF, this adds an IS_ENABLED() check that turns the function into an empty stub then and avoids the link error. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Fixes: ca304fa9bb76 ("ARM/dmaengine: edma: Public API to use private struct pointer") Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-11-04dmaengine: edma: Add dummy driver skeleton for edma3-tptcPeter Ujfalusi1-0/+19
The eDMA3 TPTC does not need any software configuration, but it is a separate IP block in the SoC. In order the omap hwmod core to be able to handle the TPTC resources correctly in regards of PM we need to have a driver loaded for it. This patch will add a dummy driver skeleton without probe or remove callbacks provided. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Reported-by: Olof Johansson <olof@lixom.net> Tested-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-27dmaengine: edma: New device tree bindingPeter Ujfalusi1-146/+340
With the old binding and driver architecture we had many issues: No way to assign eDMA channels to event queues, thus not able to tune the system by moving specific DMA channels to low/high priority servicing. We moved the cyclic channels to high priority within the code, but that was just a workaround to this issue. Memcopy was fundamentally broken: even if the driver scanned the DT/devices in the booted system for direct DMA users (which is not effective when the events are going through a crossbar) and created a map of 'used' channels, this information was not really usable. Since via dmaengien API the eDMA driver will be called with _some_ channel number, we would try to request this channel when any channel is requested for memcpy. By luck we got channel which is not used by any device most of the time so things worked, but if a device would have been using the given channel, but not requested it, the memcpy channel would have been waiting for HW event. The old code had the am33xx/am43xx DMA event router handling embedded. This should have been done in a separate driver since it is not part of the actual eDMA IP. There were no way to 'lock' PaRAM slots to be used by the DSP for example when booting with DT. In DT boot the edma node used more than one hwmod which is not a good practice and the kernel prints warning because of this. With the new bindings and the changes in the driver we can: - No regression with Legacy binding and non DT boot - DMA channels can be assigned to any TC (to set priority) - PaRAM slots can be reserved for other cores to use - Dynamic power management for CC and TCs, if only TC0 is used all other TC can be powered down for example Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-27dmaengine: edma: Merge the of parsing functionsPeter Ujfalusi1-16/+8
Instead of nesting functions just merge them since the resulting function is still small and readable. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-27dmaengine: edma: Do not allocate memory for edma_rsv_info in case of DT bootPeter Ujfalusi1-6/+0
The channel/slot reservation is not supported when booted with DT so there is not need to allocate memory. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-27dmaengine: edma: Refactor the dma device and channel struct initializationPeter Ujfalusi1-42/+37
Move all code under one function to do the dma device and eDMA channel related setup so they are not scattered around the driver. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-27dmaengine: edma: Get qDMA channel information from HW alsoPeter Ujfalusi1-0/+6
Query the number of qDMA channels from CCCFG register. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-27dmaengine: edma: Merge map_dmach_to_queue into assign_channel_eventqPeter Ujfalusi1-34/+22
edma_assign_channel_eventq() is a wrapper around edma_map_dmach_to_queue() We can merge the content of the later so we will have only one function to be used for mapping channels to given eventq Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-27dmaengine: edma: Correct PaRAM access function names (_parm_ to _param_)Peter Ujfalusi1-12/+12
These inline functions are designed to modify parts of the PaRAM in eDMA. Change the names accordingly. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-27dmaengine: edma: Simplify function parameter list for channel operationsPeter Ujfalusi1-273/+123
Instead of passing a pointer to struct edma_cc and the channel number, pass only the pointer to the edma_chan structure for the given channel. This struct contains all the information needed by the functions and the use of this makes it obvious that most of the sanity checks can be removed from the driver. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-27dmaengine: edma: Optimize memcpy operationPeter Ujfalusi1-21/+75
If the transfer is shorted then 64K we can complete it with one ACNT burst by configuring ACNT to the length of the copy, this require one paRAM slot. Otherwise we use two paRAM slots for the copy: slot1: will copy (length / 32767) number of 32767 byte long blocks slot2: will be configured to copy the remaining data. According to tests this patch increases the throughput of memcpy from ~3MB/s to 15MB/s Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-27dmaengine: edma: Remove alignment constraint for memcpyPeter Ujfalusi1-7/+6
Despite the claim by the original commit adding the memcpy support, eDMA does not have constraint on the alignment of src, dst or length in increment mode. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-14dmaengine: edma: Dynamic paRAM slot handling if HW supports itPeter Ujfalusi1-49/+52
If the eDMA3 has support for channel paRAM slot mapping we can utilize it to allocate slots on demand and save precious slots for real transfers. On am335x the eDMA has 64 channels which means we can unlock 64 paRAM slots out from the available 256. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-14dmaengine: edma: Rename bitfields for slot and channel usage trackingPeter Ujfalusi1-25/+26
The names chosen for the bitfields were quite confusing and given no real information on what they are used for... edma_inuse -> slot_inuse: tracks the slot usage/availability edma_unused -> channel_unused: tracks the channel usage/availability Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-14dmaengine: edma: Read channel mapping support only once from HWPeter Ujfalusi1-2/+6
Instead of directly reading it from CCCFG register take the information out once when we set up the configuration from the HW. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-14dmaengine: edma: Simplify and optimize ccerr interrupt handlerPeter Ujfalusi1-47/+35
No need to run through the bits in QEMR and CCERR events since they will not trigger any action, so just clearing the errors there is fine. In case of the missed event the loop can be optimized so we spend less time to handle the event. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-14dmaengine: edma: Move the pending error check into helper functionPeter Ujfalusi1-8/+12
In the ccerr interrupt handler the code checks for pending errors in the error status registers in two different places. Move the check out to a helper function. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-14dmaengine: edma: Simplify the interrupt handlingPeter Ujfalusi1-245/+205
With the merger of the arch/arm/common/edma.c code into the dmaengine driver, there is no longer need to have per channel callback/data storage for interrupt events. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-14dmaengine: edma: Consolidate the comments for functionsPeter Ujfalusi1-75/+11
Remove or rewrite the comments for the internal functions. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-14dmaengine: edma: Print warning when linking slots from different eDMAPeter Ujfalusi1-0/+3
Warning message in case of linking between paRAM slots in different eDMA controllers. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-14dmaengine: edma: Use the edma_write_slot instead open coded memcpy_toioPeter Ujfalusi1-2/+1
edma_write_slot() is for writing an entire paRAM slot. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-14dmaengine: edma: Use dev_dbg instead pr_debugPeter Ujfalusi1-12/+12
We have access to dev, so it is better to use the dev_dbg for debug prints. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-14dmaengine: edma: Cleanup regarding the use of dev around the codePeter Ujfalusi1-31/+30
Be consistent and do not mix the use of dev, &pdev->dev, etc in the functions. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-14dmaengine: edma: Use devm_kcalloc when possiblePeter Ujfalusi1-2/+2
When allocating a memory for number of items it is better (looks better) to use devm_kcalloc. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-14dmaengine: edma: Allocate memory dynamically for bitmaps and structuresPeter Ujfalusi1-28/+34
Instead of using defines to specify the size of different arrays and bitmaps, allocate the memory for them based on the information we get from the HW itself. Since these defines are set based on the worst case, there are devices where they are not valid. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-14ARM/dmaengine: edma: Merge the two drivers under drivers/dma/Peter Ujfalusi1-75/+1431
Move the code out from arch/arm/common and merge it inside of the dmaengine driver. This change is done with as minimal (if eny) functional change to the code as possible to avoid introducing regression. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-14ARM/dmaengine: edma: Remove limitation on the number of eDMA controllersPeter Ujfalusi1-9/+8
Since the driver stack no longer depends on lookup with id number in a global array of pointers, the limitation for the number of eDMAs are no longer needed. We can handle as many eDMAs in legacy and DT boot as we have memory for them to allocate the needed structures. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-14ARM/dmaengine: edma: Public API to use private struct pointerPeter Ujfalusi1-36/+43
Instead of relying on indexes pointing to edma private date in the global pointer array, pass the private data pointer via the public API. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-14ARM/dmaengine: edma: Move of_dma_controller_register to the dmaengine driverPeter Ujfalusi1-0/+16
If the of_dma_controller is registered in the non dmaengine driver we could have race condition: the of_dma_controller has been registered, but the dmaengine driver is not yet probed. Drivers requesting DMA channels during this window will fail since we do not yet have dmaengine drivers registered. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-14dmaengine: edma: Simplify and optimize the edma_execute pathPeter Ujfalusi1-47/+29
The code path in edma_execute() and edma_callback() can be simplified and make it more optimal. There is not need to call in to edma_execute() when the transfer has been finished for example. Also the handling of missed/first or next batch of paRAMs can be done in a more optimal way. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-05dmaengine: Add an enum for the dmaengine alignment constraintsMaxime Ripard1-1/+1
Most drivers need to set constraints on the buffer alignment for async tx operations. However, even though it is documented, some drivers either use a defined constant that is not matching what the alignment variable expects (like DMA_BUSWIDTH_* constants) or fill the alignment in bytes instead of power of two. Add a new enum for these alignments that matches what the framework expects, and convert the drivers to it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-05-06dmaenegine: edma: allow pause/resume for non-cyclic modeJohn Ogness1-6/+1
The 8250_omap serial driver relies on dmaengine_pause() actually pausing the DMA transfer. Before this patch dmaengine_pause() is a NOP for non-cylic DMA transfers. This allowed the 8250_omap driver to read DMA buffers while the DMA was still active, resulting in lost serial data. Signed-off-by: John Ogness <john.ogness@linutronix.de> Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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