aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/dma/xilinx (follow)
AgeCommit message (Collapse)AuthorFilesLines
2019-03-14Merge tag 'dmaengine-5.1-rc1' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds1-70/+100
Pull dmaengine updates from Vinod Koul: - dmatest updates for modularizing common struct and code - remove SG support for VDMA xilinx IP and updates to driver - Update to dw driver to support Intel iDMA controllers multi-block support - tegra updates for proper reporting of residue - Add Snow Ridge ioatdma device id and support for IOATDMA v3.4 - struct_size() usage and useless LIST_HEAD cleanups in subsystem. - qDMA controller driver for Layerscape SoCs - stm32-dma PM Runtime support - And usual updates to imx-sdma, sprd, Documentation, fsl-edma, bcm2835, qcom_hidma etc * tag 'dmaengine-5.1-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (81 commits) dmaengine: imx-sdma: fix consistent dma test failures dmaengine: imx-sdma: add a test for imx8mq multi sdma devices dmaengine: imx-sdma: add clock ratio 1:1 check dmaengine: dmatest: move test data alloc & free into functions dmaengine: dmatest: add short-hand `buf_size` var in dmatest_func() dmaengine: dmatest: wrap src & dst data into a struct dmaengine: ioatdma: support latency tolerance report (LTR) for v3.4 dmaengine: ioatdma: add descriptor pre-fetch support for v3.4 dmaengine: ioatdma: disable DCA enabling on IOATDMA v3.4 dmaengine: ioatdma: Add Snow Ridge ioatdma device id dmaengine: sprd: Change channel id to slave id for DMA cell specifier dt-bindings: dmaengine: sprd: Change channel id to slave id for DMA cell specifier dmaengine: mv_xor: Use correct device for DMA API Documentation :dmaengine: clarify DMA desc. pointer after submission Documentation: dmaengine: fix dmatest.rst warning dmaengine: k3dma: Add support for dma-channel-mask dmaengine: k3dma: Delete axi_config dmaengine: k3dma: Upgrade k3dma driver to support hisi_asp_dma hardware Documentation: bindings: dma: Add binding for dma-channel-mask Documentation: bindings: k3dma: Extend the k3dma driver binding to support hisi-asp ...
2019-01-20dmaengine: xilinx_dma: remove set but not used variable 'tail_segment'YueHaibing1-4/+0
Fixes gcc '-Wunused-but-set-variable' warning: drivers/dma/xilinx/xilinx_dma.c: In function 'xilinx_vdma_start_transfer': drivers/dma/xilinx/xilinx_dma.c:1104:33: warning: variable 'tail_segment' set but not used [-Wunused-but-set-variable] It not used since commit b8349172b400 ("dmaengine: xilinx_dma: Drop SG support for VDMA IP") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-01-08cross-tree: phase out dma_zalloc_coherent()Luis Chamberlain2-10/+10
We already need to zero out memory for dma_alloc_coherent(), as such using dma_zalloc_coherent() is superflous. Phase it out. This change was generated with the following Coccinelle SmPL patch: @ replace_dma_zalloc_coherent @ expression dev, size, data, handle, flags; @@ -dma_zalloc_coherent(dev, size, handle, flags) +dma_alloc_coherent(dev, size, handle, flags) Suggested-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Luis Chamberlain <mcgrof@kernel.org> [hch: re-ran the script on the latest tree] Signed-off-by: Christoph Hellwig <hch@lst.de>
2019-01-07dmaengine: xilinx_dma: Drop SG support for VDMA IPAndrea Merello1-52/+32
xilinx_vdma_start_transfer() is used only for VDMA IP, still it contains conditional code on has_sg variable. has_sg is set only whenever the HW does support SG mode, that is never true for VDMA IP. This patch drops the never-taken branches. Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-01-07dmaengine: xilinx_dma: autodetect whether the HW supports scatter-gatherAndrea Merello1-4/+10
The AXIDMA and CDMA HW can be either direct-access or scatter-gather version. These are SW incompatible. The driver can handle both versions: a DT property was used to tell the driver whether to assume the HW is in scatter-gather mode. This patch makes the driver to autodetect this information. The DT property is not required anymore. No changes for VDMA. Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-01-07dmaengine: xilinx_dma: program hardware supported buffer lengthRadhey Shyam Pandey1-4/+20
AXI-DMA IP supports configurable (c_sg_length_width) buffer length register width, hence read buffer length (xlnx,sg-length-width) DT property and ensure that driver doesn't program buffer length exceeding the supported limit. For VDMA and CDMA there is no change. Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Andrea Merello <andrea.merello@gmail.com> [rebase, reword] Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-01-07dmaengine: xilinx_dma: in axidma slave_sg and dma_cyclic mode align split descriptorsAndrea Merello1-0/+9
Whenever a single or cyclic transaction is prepared, the driver could eventually split it over several SG descriptors in order to deal with the HW maximum transfer length. This could end up in DMA operations starting from a misaligned address. This seems fatal for the HW if DRE (Data Realignment Engine) is not enabled. This patch eventually adjusts the transfer size in order to make sure all operations start from an aligned address. Cc: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-01-07dmaengine: xilinx_dma: commonize DMA copy size calculationAndrea Merello1-8/+31
This patch removes a bit of duplicated code by introducing a new function that implements calculations for DMA copy size, and prepares for changes to the copy size calculation that will happen in following patches. Suggested-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-12-31Merge branch 'topic/xilinx' into for-linusVinod Koul2-21/+25
2018-12-05dmaengine: zynqmp_dma: replace spin_lock_bh with spin_lock_irqsaveMichael Tretter1-15/+22
All device_prep_dma_* functions and device_issue_pending can be called from an interrupt context. As this includes hard IRQs, we must use spin_lock_irqsave() instead of spin_lock_bh() to access chan->lock. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-11-24dmaengine: xilinx_dma: Remove __aligned attribute on zynqmp_dma_desc_llNathan Chancellor1-1/+1
Clang warns: drivers/dma/xilinx/zynqmp_dma.c:166:4: warning: attribute 'aligned' is ignored, place it after "struct" to apply attribute to type declaration [-Wignored-attributes] }; __aligned(64) ^ ./include/linux/compiler_types.h:200:38: note: expanded from macro '__aligned' ^ 1 warning generated. As Nick pointed out in the previous version of this patch, the author likely intended for this struct to be 8-byte (64-bit) aligned, not 64-byte, which is the default. Remove the hanging __aligned attribute. Fixes: b0cc417c1637 ("dmaengine: Add Xilinx zynqmp dma engine driver support") Reported-by: Nick Desaulniers <ndesaulniers@google.com> Suggested-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-11-11dmaengine: xilinx_dma: Fix 64-bit simple CDMA transferRadhey Shyam Pandey1-2/+4
In AXI CDMA simple mode also pass MSB bits of source and destination address to xilinx_write function. This fixes simple CDMA operation mode using 64-bit addressing. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Appana Durga Kedareswara Rao <appana.durga.rao@xilinx.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-11-11dmaengine: xilinx_dma: Introduce helper macro for preparing dma addressRadhey Shyam Pandey1-0/+2
This patch introduces the xilinx_prep_dma_addr_t macro which prepares dma_addr_t from hardware buffer descriptor LSB and MSB fields. It will be used in simple dma 64-bit programming sequence. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Reviewed-by: Appana Durga Kedareswara Rao <appana.durga.rao@xilinx.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-11-11dmaengine: xilinx_dma: Refactor axidma channel allocationRadhey Shyam Pandey1-18/+18
In axidma alloc_chan_resources merge BD and cyclic BD allocation. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-06-29dmaengine: xilinx_dma: Enable VDMA S2MM vertical flip supportRadhey Shyam Pandey1-0/+22
Vertical flip state is exported in xilinx_vdma_config and depending on IP configuration(c_enable_vert_flip) vertical flip state is programmed in hardware. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-06-12treewide: kzalloc() -> kcalloc()Kees Cook1-1/+1
The kzalloc() function has a 2-factor argument form, kcalloc(). This patch replaces cases of: kzalloc(a * b, gfp) with: kcalloc(a * b, gfp) as well as handling cases of: kzalloc(a * b * c, gfp) with: kzalloc(array3_size(a, b, c), gfp) as it's slightly less ugly than: kzalloc_array(array_size(a, b), c, gfp) This does, however, attempt to ignore constant size factors like: kzalloc(4 * 1024, gfp) though any constants defined via macros get caught up in the conversion. Any factors with a sizeof() of "unsigned char", "char", and "u8" were dropped, since they're redundant. The Coccinelle script used for this was: // Fix redundant parens around sizeof(). @@ type TYPE; expression THING, E; @@ ( kzalloc( - (sizeof(TYPE)) * E + sizeof(TYPE) * E , ...) | kzalloc( - (sizeof(THING)) * E + sizeof(THING) * E , ...) ) // Drop single-byte sizes and redundant parens. @@ expression COUNT; typedef u8; typedef __u8; @@ ( kzalloc( - sizeof(u8) * (COUNT) + COUNT , ...) | kzalloc( - sizeof(__u8) * (COUNT) + COUNT , ...) | kzalloc( - sizeof(char) * (COUNT) + COUNT , ...) | kzalloc( - sizeof(unsigned char) * (COUNT) + COUNT , ...) | kzalloc( - sizeof(u8) * COUNT + COUNT , ...) | kzalloc( - sizeof(__u8) * COUNT + COUNT , ...) | kzalloc( - sizeof(char) * COUNT + COUNT , ...) | kzalloc( - sizeof(unsigned char) * COUNT + COUNT , ...) ) // 2-factor product with sizeof(type/expression) and identifier or constant. @@ type TYPE; expression THING; identifier COUNT_ID; constant COUNT_CONST; @@ ( - kzalloc + kcalloc ( - sizeof(TYPE) * (COUNT_ID) + COUNT_ID, sizeof(TYPE) , ...) | - kzalloc + kcalloc ( - sizeof(TYPE) * COUNT_ID + COUNT_ID, sizeof(TYPE) , ...) | - kzalloc + kcalloc ( - sizeof(TYPE) * (COUNT_CONST) + COUNT_CONST, sizeof(TYPE) , ...) | - kzalloc + kcalloc ( - sizeof(TYPE) * COUNT_CONST + COUNT_CONST, sizeof(TYPE) , ...) | - kzalloc + kcalloc ( - sizeof(THING) * (COUNT_ID) + COUNT_ID, sizeof(THING) , ...) | - kzalloc + kcalloc ( - sizeof(THING) * COUNT_ID + COUNT_ID, sizeof(THING) , ...) | - kzalloc + kcalloc ( - sizeof(THING) * (COUNT_CONST) + COUNT_CONST, sizeof(THING) , ...) | - kzalloc + kcalloc ( - sizeof(THING) * COUNT_CONST + COUNT_CONST, sizeof(THING) , ...) ) // 2-factor product, only identifiers. @@ identifier SIZE, COUNT; @@ - kzalloc + kcalloc ( - SIZE * COUNT + COUNT, SIZE , ...) // 3-factor product with 1 sizeof(type) or sizeof(expression), with // redundant parens removed. @@ expression THING; identifier STRIDE, COUNT; type TYPE; @@ ( kzalloc( - sizeof(TYPE) * (COUNT) * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | kzalloc( - sizeof(TYPE) * (COUNT) * STRIDE + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | kzalloc( - sizeof(TYPE) * COUNT * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | kzalloc( - sizeof(TYPE) * COUNT * STRIDE + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | kzalloc( - sizeof(THING) * (COUNT) * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) | kzalloc( - sizeof(THING) * (COUNT) * STRIDE + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) | kzalloc( - sizeof(THING) * COUNT * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) | kzalloc( - sizeof(THING) * COUNT * STRIDE + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) ) // 3-factor product with 2 sizeof(variable), with redundant parens removed. @@ expression THING1, THING2; identifier COUNT; type TYPE1, TYPE2; @@ ( kzalloc( - sizeof(TYPE1) * sizeof(TYPE2) * COUNT + array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2)) , ...) | kzalloc( - sizeof(TYPE1) * sizeof(THING2) * (COUNT) + array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2)) , ...) | kzalloc( - sizeof(THING1) * sizeof(THING2) * COUNT + array3_size(COUNT, sizeof(THING1), sizeof(THING2)) , ...) | kzalloc( - sizeof(THING1) * sizeof(THING2) * (COUNT) + array3_size(COUNT, sizeof(THING1), sizeof(THING2)) , ...) | kzalloc( - sizeof(TYPE1) * sizeof(THING2) * COUNT + array3_size(COUNT, sizeof(TYPE1), sizeof(THING2)) , ...) | kzalloc( - sizeof(TYPE1) * sizeof(THING2) * (COUNT) + array3_size(COUNT, sizeof(TYPE1), sizeof(THING2)) , ...) ) // 3-factor product, only identifiers, with redundant parens removed. @@ identifier STRIDE, SIZE, COUNT; @@ ( kzalloc( - (COUNT) * STRIDE * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) | kzalloc( - COUNT * (STRIDE) * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) | kzalloc( - COUNT * STRIDE * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | kzalloc( - (COUNT) * (STRIDE) * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) | kzalloc( - COUNT * (STRIDE) * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | kzalloc( - (COUNT) * STRIDE * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | kzalloc( - (COUNT) * (STRIDE) * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | kzalloc( - COUNT * STRIDE * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) ) // Any remaining multi-factor products, first at least 3-factor products, // when they're not all constants... @@ expression E1, E2, E3; constant C1, C2, C3; @@ ( kzalloc(C1 * C2 * C3, ...) | kzalloc( - (E1) * E2 * E3 + array3_size(E1, E2, E3) , ...) | kzalloc( - (E1) * (E2) * E3 + array3_size(E1, E2, E3) , ...) | kzalloc( - (E1) * (E2) * (E3) + array3_size(E1, E2, E3) , ...) | kzalloc( - E1 * E2 * E3 + array3_size(E1, E2, E3) , ...) ) // And then all remaining 2 factors products when they're not all constants, // keeping sizeof() as the second factor argument. @@ expression THING, E1, E2; type TYPE; constant C1, C2, C3; @@ ( kzalloc(sizeof(THING) * C2, ...) | kzalloc(sizeof(TYPE) * C2, ...) | kzalloc(C1 * C2 * C3, ...) | kzalloc(C1 * C2, ...) | - kzalloc + kcalloc ( - sizeof(TYPE) * (E2) + E2, sizeof(TYPE) , ...) | - kzalloc + kcalloc ( - sizeof(TYPE) * E2 + E2, sizeof(TYPE) , ...) | - kzalloc + kcalloc ( - sizeof(THING) * (E2) + E2, sizeof(THING) , ...) | - kzalloc + kcalloc ( - sizeof(THING) * E2 + E2, sizeof(THING) , ...) | - kzalloc + kcalloc ( - (E1) * E2 + E1, E2 , ...) | - kzalloc + kcalloc ( - (E1) * (E2) + E1, E2 , ...) | - kzalloc + kcalloc ( - E1 * E2 + E1, E2 , ...) ) Signed-off-by: Kees Cook <keescook@chromium.org>
2018-01-08dmaengine: xilinx_dma: Free BD consistent memoryKedareswara rao Appana1-0/+5
Free BD consistent memory while freeing the channel i.e in free_chan_resources. Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2018-01-08dmaengine: xilinx_dma: Fix warning variable prev set but not usedKedareswara rao Appana1-3/+1
This patch fixes the below sparse warning in the driver drivers/dma/xilinx/xilinx_dma.c: In function ‘xilinx_vdma_dma_prep_interleaved’: drivers/dma/xilinx/xilinx_dma.c:1614:43: warning: variable ‘prev’ set but not used [-Wunused-but-set-variable] struct xilinx_vdma_tx_segment *segment, *prev = NULL; Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2018-01-08dmaengine: xilinx_dma: properly configure the SG mode bit in the driver for cdmaKedareswara rao Appana1-0/+10
If the hardware is configured for Scatter Gather(SG) mode, and hardware is idle, in the control register SG mode bit must be set to a 0 then back to 1 by the software, to force the CDMA SG engine to use a new value written to the CURDESC_PNTR register, failure to do so could result errors from the dmaengine. This patch updates the same. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-12-18dmaengine: xilinx_dma: Fix typosVinod Koul1-3/+3
some typos is comments, so fix them up /s/enusres/ensures /s/descripotrs/descriptors /s/Submited/Submitted /s/pollling/polling Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-12-18dmaengine: xilinx_dma: Differentiate probe based on the ip typeKedareswara rao Appana1-1/+6
This patch updates the probe banner info based on the ip probed. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-12-18dmaengine: xilinx_dma: fix style issues from checkpatchKedareswara rao Appana1-1/+2
This patch fixes below. ERROR: open brace '{' following function definitions go on the next line +static int xilinx_dma_child_probe(struct xilinx_dma_device *xdev, + struct device_node *node) { Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-12-18dmaengine: xilinx_dma: Fix kernel doc warningsKedareswara rao Appana1-13/+24
This patch fixes the kernel doc warnings in the driver. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-12-18dmaengine: xilinx_dma: Fix race condition in the driver for multiple descriptor scenarioKedareswara rao Appana1-51/+84
As per axi dmaengine spec the software must not move the tail pointer to a location that has not been updated (next descriptor field of the h/w descriptor should always point to a valid address). When user submits multiple descriptors on the recv side, with the current driver flow the last buffer descriptor next descriptor field points to a invalid location, resulting the invalid data or errors from the axidma dmaengine. This patch fixes this issue by creating a buffer descritpor chain during channel allocation itself and use those buffer descriptors for the subsequent dma operations. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-12-18dmaeninge: xilinx_dma: Fix bug in multiple frame stores scenario in vdmaKedareswara rao Appana1-22/+19
VDMA engine default frame buffer configuration is cirular mode. in this mode dmaengine continuously circles through h/w configured fstore frame buffers. When vdma h/w is configured for more than one frame. for example h/w is configured for n number of frames, user submits less than n number of frames and triggered the dmaengine using issue_pending API. since the h/w (or) driver default configuraiton is circular mode h/w tries to write/read from an invalid frame buffer resulting errors from the vdma dmaengine. This patch fixes this issue by enabling the park mode as default mode configuration for frame buffers in s/w, so that driver can handle all cases for "k" frames where n%k==0 (n is a multiple of k) by simply replicating the frame pointers. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-12-18dmaengine: xilinx_dma: Check for channel idle state before submitting dma descriptorKedareswara rao Appana1-38/+22
Add variable for checking channel idle state to ensure that dma descriptor is not submitted when dmaengine is in progress. This will avoid the polling for a bit in the status register to know dma state in the driver hot path. Reviewed-by: Jose Abreu <joabreu@synopsys.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-12-18dmaengine: zynqmp_dma: Fix race condition in the probeKedareswara rao Appana1-1/+2
Incase of interrupt property is not present, Driver is trying to free an invalid irq, This patch fixes it by adding a check before freeing the irq. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-12-18dmaengine: zynqmp_dma: Fix issues with overflow interruptKedareswara rao Appana1-1/+5
This patch fixes the below issues. --> Need to clear the channel data count register when overflow interrupts occurs. --> Reduce the log level from _info to _dbg when overflow interrupt occurs. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-12-18dmaengine: zynqmp_dma: Fix warning variable 'val' set but not usedKedareswara rao Appana1-4/+2
This patch fixes the below warning drivers/dma/xilinx/zynqmp_dma.c: In function 'zynqmp_dma_handle_ovfl_int': drivers/dma/xilinx/zynqmp_dma.c:522:6: warning: variable 'val' set but not used [-Wunused-but-set-variable] Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-12-18dmaengine: zynqmp_dma: Fix kernel doc-formatKedareswara rao Appana1-1/+3
This patch fixes the below kernel doc warnings drivers/dma/xilinx/zynqmp_dma.c:552: info: Scanning doc for zynqmp_dma_device_config drivers/dma/xilinx/zynqmp_dma.c:558: warning: No description found for return value of 'zynqmp_dma_device_config' drivers/dma/xilinx/zynqmp_dma.c:649: info: Scanning doc for zynqmp_dma_free_descriptors drivers/dma/xilinx/zynqmp_dma.c:653: warning: No description found for parameter 'chan' drivers/dma/xilinx/zynqmp_dma.c:653: warning: Excess function parameter 'dchan' description in 'zynqmp_dma_free_descriptors' Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-12-18dmaengine: zynqmp_dma: Add runtime pm supportKedareswara rao Appana1-32/+128
This patch adds runtime pm support in the driver. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-09-17dmaengine: xilinx_dma: Move enum xdma_ip_type to driver fileLars-Peter Clausen1-0/+14
The enum xdma_ip_type is only used inside the Xilinx DMA driver and not exported to any consumers (nor should it be). So move it from the global header to driver file itself. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-09-06Merge branch 'topic/dmatest' into for-linusVinod Koul1-94/+0
2017-09-05dmaengine: xilinx_dma: Fix error code format specifierLars-Peter Clausen1-15/+15
'err' is a signed int and error codes are typically negative numbers, so use '%d' instead of '%u' to format the error code in the error message. Fixes: ba16db36b5dd ("dmaengine: vdma: Add clock support") Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Acked-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-08-22dmaengine: remove DMA_SG as it is dead code in kernelDave Jiang1-94/+0
There are no in kernel consumers for DMA_SG op. Removing operation, dead code, and test code in dmatest. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Cc: Gary Hook <gary.hook@amd.com> Cc: Ludovic Desroches <ludovic.desroches@microchip.com> Cc: Kedareswara rao Appana <appana.durga.rao@xilinx.com> Cc: Li Yang <leoyang.li@nxp.com> Cc: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-03dmaengine: zynqmp_dma: Remove max len check in zynqmp_dma_prep_memcpyStefan Roese1-3/+0
Remove check for "len > ZYNQMP_DMA_MAX_TRANS_LEN" as its not needed. If the length is larger, the transfer is split up into multiple parts with the max descriptor length already. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Kedareswara rao Appana <appanad@xilinx.com> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-03-14dmaengine: xilinx: avoid memory corruption for device_prep_dma_memcpy()Akinobu Mita1-12/+2
The device_prep_dma_memcpy() callback for this driver allocates a new xilinx_dma_tx_descriptor whose TX segments list is initialized as empty, but then gets invalid TX segment pointer by list_last_entry() from the empty TX segments list and memory corruption happens by the attempt to update the next descriptor in invalid TX segment pointer. This removes unnecessary memory access for nonexistent tail TX segment which causes memory corruption. Cc: Vinod Koul <vinod.koul@intel.com> Cc: Kedareswara rao Appana <appana.durga.rao@xilinx.com> Cc: Michal Simek <monstr@monstr.eu> Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-03-14dmaengine: xilinx: fix device_terminate_all() callback for AXI CDMAAkinobu Mita1-16/+33
The device_terminate_all() callback for this driver stops current DMA operations by clearing RUNSTOP bit in the control register and waiting HALTED bit set in the status register. But AXI CDMA which is one of the supported DMA engine by this driver does not provide the run / stop controls and those bits in the control and status registers are reserved. So when device_terminate_all() is called, the error message is printed and the channel is marked as having errors in xilinx_dma_halt(). This change adds stop_transfer() callback which differentiates CDMA and other DMA engine. The CDMA's one avoids the unsupported operations and instead polls the status register to check if the DMA operations are in progress for AXI CDMA. Cc: Vinod Koul <vinod.koul@intel.com> Cc: Kedareswara rao Appana <appana.durga.rao@xilinx.com> Cc: Michal Simek <monstr@monstr.eu> Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-08-08dmengine: xilinx_dma: convert callback to helper functionVinod Koul1-6/+4
Move the xilinx driver to new dmaengine callback Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-07-24dmaengine: zynqmp_dma: add missing MODULE_LICENSEArnd Bergmann1-0/+1
We get a warning about the missing MODULE_LICENSE tag for this newly added driver module: WARNING: modpost: missing MODULE_LICENSE() in drivers/dma/xilinx/zynqmp_dma.o see include/linux/module.h for more information This adds a "GPL" license, matching the "version 2 or later" information in the comment at the start of the file. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-07-24dmaengine: zynqmp_dma: Fix static checker warningKedareswara rao Appana1-3/+8
This patch fixes the below static checker warning drivers/dma/xilinx/zynqmp_dma.c:973 zynqmp_dma_chan_probe() warn: was && intended here instead of ||? Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-07-12dmaengine: zynqmp: avoid cast warningArnd Bergmann1-1/+1
The newly added zynqmp_dma driver produces a warning on 32-bit architectures when dma_addr_t is 64-bit wide: drivers/dma/xilinx/zynqmp_dma.c: In function 'zynqmp_dma_config_sg_ll_desc': drivers/dma/xilinx/zynqmp_dma.c:321:9: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast] ((dma_addr_t)sdesc - (dma_addr_t)chan->desc_pool_v); ^ drivers/dma/xilinx/zynqmp_dma.c:321:29: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast] ((dma_addr_t)sdesc - (dma_addr_t)chan->desc_pool_v); This changes the cast to the more appropriate uintptr_t. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-07-12dmaengine: xilinx: Fix race condition in axi dma cyclic dma modeKedareswara rao Appana1-4/+5
In cyclic DMA mode need to link the tail bd segment with the head bd segment to process bd's in cyclic. Current driver is doing this only for tx channel needs to update the same for rx channel case also. This patch fixes the same. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-07-08dmaengine: Add Xilinx zynqmp dma engine driver supportKedareswara rao Appana2-0/+1146
Added the driver for zynqmp dma engine used in Zynq UltraScale+ MPSoC. This dma controller supports memory to memory and I/O to I/O buffer transfers. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-07-08dmaengine: xilinx: Use different channel names for each dmaKedareswara rao Appana1-2/+6
Current driver assumes that child node channel name is either "xlnx,axi-vdma-mm2s-channel" or "xlnx,axi-vdma-s2mm-channel" which is confusing the users of AXI DMA and CDMA. This patch fixes this issue by using different channel names for the AXI DMA and AXI CDMA child nodes. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-07-08dmaengine: xilinx: Rename driver and configKedareswara rao Appana2-1/+1
In the existing vdma driver support for AXI DMA and CDMA got added so the driver is no longer VDMA specific. This patch renames the driver and DT binding doc to xilinx_dma and updates the Kconfig description for all the DMAS. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-07-08dmaengine: vdma: Add support for mulit-channel dma modeKedareswara rao Appana1-23/+190
This patch adds support for AXI DMA multi-channel dma mode Multichannel mode enables DMA to connect to multiple masters and slaves on the streaming side. In Multichannel mode AXI DMA supports 2D transfers. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-06-21dmaengine: vdma: Add 64 bit addressing support for the axi cdmaKedareswara rao Appana1-12/+16
The AXI CDMA is a soft ip, which can be programmed to support 32 bit addressing or greater than 32 bit addressing. When the AXI CDMA ip is configured for 32 bit address space in simple dma mode the source/destination buffer address is specified by a single register(18h for Source buffer address and 20h for Destination buffer address). When configured in SG mode the current descriptor and tail descriptor are specified by a Single register(08h for curdesc 10h for tail desc). When the AXI CDMA core is configured for an address space greater than 32 then each buffer address or descriptor address is specified by a combination of two registers. The first register specifies the LSB 32 bits of address, while the next register specifies the MSB 32 bits of address. For example, 08h will specify the LSB 32 bits while 0Ch will specify the MSB 32 bits of the first start address. So we need to program two registers at a time. This patch adds the 64 bit addressing support to the axicdma IP in the driver. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-06-21dmaengine: vdma: Add 64 bit addressing support for the axi dmaKedareswara rao Appana1-16/+47
The AXI DMA is a soft ip, which can be programmed to support 32 bit addressing or greater than 32 bit addressing. When the AXI DMA ip is configured for 32 bit address space in simple dma mode the buffer address is specified by a single register (18h for MM2S channel and 48h for S2MM channel). When configured in SG mode The current descriptor and tail descriptor are specified by a single Register(08h for curdesc 10h for tail desc for MM2S channel and 38h for Curdesc and 40h for tail desc for S2MM). When the AXI DMA core is configured for an address space greater than 32 then each buffer address or descriptor address is specified by a combination of two registers. The first register specifies the LSB 32 bits of address, while the next register specifies the MSB 32 bits of address. For example, 48h will specify the LSB 32 bits while 4Ch will specify the MSB 32 bits of the first start address. So we need to program two registers at a time. This patch adds the 64 bit addressing support for the axidma IP in the driver. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-06-13dmaengine: xilinx-vdma: add some sanity checksArnd Bergmann1-0/+6
The newly added xilinx_dma_prep_dma_cyclic function sometimes causes a gcc warning about the use of the segment function in case we never run into the inner loop of the function: dma/xilinx/xilinx_vdma.c: In function 'xilinx_dma_prep_dma_cyclic': dma/xilinx/xilinx_vdma.c:1808:23: error: 'segment' may be used uninitialized in this function [-Werror=maybe-uninitialized] segment->hw.control |= XILINX_DMA_BD_SOP; This can only happen if the period len is zero (which would cause other problems earlier), or if the buffer is shorter than a period. Neither of them should ever happen, but by adding an explicit check for these two cases, we can abort in a more controlled way, and the compiler is able to see that we never use uninitialized data. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.