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2017-11-28fpga: clean up fpga KconfigAlan Tull1-54/+54
The fpga menuconfig has gotten messy. The bridges and managers are mixed together. * Separate the bridges and things dependent on CONFIG_FPGA_BRIDGE from the managers. * Group the managers by vendor in order that they were added to the kernel. The following is what the menuconfig ends up looking like more or less (platform dependencies are hiding some of these on any given platform). --- FPGA Configuration Framework <*> Altera SOCFPGA FPGA Manager <*> Altera SoCFPGA Arria10 <*> Altera Partial Reconfiguration IP Core <*> Platform support of Altera Partial Reconfiguration IP Core <*> Altera FPGA Passive Serial over SPI <*> Altera Arria-V/Cyclone-V/Stratix-V CvP FPGA Manager <*> Xilinx Zynq FPGA <*> Xilinx Configuration over Slave Serial (SPI) <*> Lattice iCE40 SPI <*> Technologic Systems TS-73xx SBC FPGA Manager <*> FPGA Bridge Framework <*> Altera SoCFPGA FPGA Bridges <*> Altera FPGA Freeze Bridge <*> Xilinx LogiCORE PR Decoupler <*> FPGA Region <*> FPGA Region Device Tree Overlay Support Signed-off-by: Alan Tull <atull@kernel.org> Acked-by: Moritz Fischer <mdf@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-28fpga: region: move device tree support to of-fpga-region.cAlan Tull1-4/+11
Create of-fpga-region.c and move the following functions without modification from fpga-region.c. * of_fpga_region_find * of_fpga_region_get_mgr * of_fpga_region_get_bridges * child_regions_with_firmware * of_fpga_region_parse_ov * of_fpga_region_notify_pre_apply * of_fpga_region_notify_post_remove * of_fpga_region_notify * of_fpga_region_probe * of_fpga_region_remove Create two new functions with some code from fpga_region_init/exit. * of_fpga_region_init * of_fpga_region_exit Signed-off-by: Alan Tull <atull@kernel.org> Acked-by: Moritz Fischer <mdf@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-07-17fpga manager: Add Altera CvP driverAnatolij Gustschin1-0/+7
Add FPGA manager driver for loading Arria-V/Cyclone-V/Stratix-V and Arria-10 FPGAs via CvP. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Alan Tull <atull@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-07-17fpga manager: Add altera-ps-spi driver for Altera FPGAsJoshua Clayton1-0/+7
altera-ps-spi loads FPGA firmware over SPI, using the "passive serial" interface on Altera Arria 10, Cyclone V or Stratix V FPGAs. This is one of the simpler ways to set up an FPGA at runtime. The signal interface is close to unidirectional SPI with lsb first. Signed-off-by: Joshua Clayton <stillcompiling@gmail.com> Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Alan Tull <atull@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-07-17Make FPGA a menuconfig to ease disabling it allVincent Legoll1-5/+1
No need to get into the submenu to disable all FPGA-related config entries Signed-off-by: Vincent Legoll <vincent.legoll@gmail.com> Acked-by: Moritz Fischer <mdf@kernel.org> Signed-off-by: Alan Tull <atull@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-04-08fpga: Add support for Xilinx LogiCORE PR DecouplerMoritz Fischer1-0/+10
This adds support for the Xilinx LogiCORE PR Decoupler soft-ip that does decoupling of PR regions in the FPGA fabric during partial reconfiguration. Signed-off-by: Moritz Fischer <mdf@kernel.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Cc: Sören Brinkmann <soren.brinkmann@xilinx.com> Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Acked-by: Alan Tull <atull@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-04-08fpga pr ip: Platform driver for Altera Partial Reconfiguration IP.Matthew Gerlach1-0/+7
This adds a platform bus driver for a fpga-mgr driver that uses the Altera Partial Reconfiguration IP component. Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Acked-by: Alan Tull <atull@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-04-08fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.Matthew Gerlach1-0/+5
Adding the core functions necessary for a fpga-mgr driver for the Altera Partial IP component. It is intended for these functions to be used by the various bus implementations like the platform bus or the PCIe bus. Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Acked-by: Alan Tull <atull@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-04-08fpga manager: Add Xilinx slave serial SPI driverAnatolij Gustschin1-0/+7
The driver loads FPGA firmware over SPI, using the "slave serial" configuration interface on Xilinx FPGAs. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Moritz Fischer <mdf@kernel.org> Acked-by: Alan Tull <atull@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-03-17fpga: Add support for Lattice iCE40 FPGAsJoel Holdsworth1-0/+6
This patch adds support to the FPGA manager for configuring the SRAM of iCE40LM, iCE40LP, iCE40HX, iCE40 Ultra, iCE40 UltraLite and iCE40 UltraPlus devices, through slave SPI. Signed-off-by: Joel Holdsworth <joel@airwebreathe.org.uk> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com> Acked-by: Alan Tull <atull@opensource.altera.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-03-17FPGA: Add TS-7300 FPGA managerFlorian Fainelli1-0/+7
Add support for loading bitstreams on the Altera Cyclone II FPGA populated on the TS-7300 board. This is done through the configuration and data registers offered through a memory interface between the EP93xx SoC and the FPGA via an intermediate CPLD device. The EP93xx SoC on the TS-7300 does not have direct means of configuring the on-board FPGA other than by using the special memory mapped interface to the CPLD. No other entity on the system can control the FPGA bitstream. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Alan Tull <atull@opensource.altera.com> Acked-by: Moritz Fischer <moritz.fischer@ettus.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-11-29fpga: Add COMPILE_TEST to all driversJason Gunthorpe1-2/+3
Like Zynq the Altera drivers compile fine on x86 and others too, so make it easier to compile test this stuff. A10 requires REGMAP_MMIO to compile, so be explicit rather than relying on it via ARCH_SOCFPGA. Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Acked-by: Alan Tull <atull@opensource.altera.com>
2016-11-10fpga-manager: Add Socfpga Arria10 supportAlan Tull1-0/+6
Add low level driver to support reprogramming FPGAs for Altera SoCFPGA Arria10. Signed-off-by: Alan Tull <atull@opensource.altera.com> Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-11-10fpga: add altera freeze bridge supportAlan Tull1-0/+9
Add a low level driver for Altera Freeze Bridges to the FPGA Bridge framework. A freeze bridge is a bridge that exists in the FPGA fabric to isolate one region of the FPGA from the busses while that one region is being reprogrammed. Signed-off-by: Alan Tull <atull@opensource.altera.com> Signed-off-by: Matthew Gerlach <mgerlach@opensource.altera.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-11-10ARM: socfpga: fpga bridge driver supportAlan Tull1-0/+7
Supports Altera SOCFPGA bridges: * fpga2sdram * fpga2hps * hps2fpga * lwhps2fpga Allows enabling/disabling the bridges through the FPGA Bridge Framework API functions. The fpga2sdram driver only supports enabling and disabling of the ports that been configured early on. This is due to a hardware limitation where the read, write, and command ports on the fpga2sdram bridge can only be reconfigured while there are no transactions to the sdram, i.e. when running out of OCRAM before the kernel boots. Device tree property 'init-val' configures the driver to enable or disable the bridge during probe. If the property does not exist, the driver will leave the bridge in its current state. Signed-off-by: Alan Tull <atull@opensource.altera.com> Signed-off-by: Matthew Gerlach <mgerlach@altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-11-10fpga: fpga-region: device tree control for FPGAAlan Tull1-0/+7
FPGA Regions support programming FPGA under control of the Device Tree. Signed-off-by: Alan Tull <atull@opensource.altera.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-11-10fpga: add fpga bridge frameworkAlan Tull1-0/+7
This framework adds API functions for enabling/ disabling FPGA bridges under kernel control. This allows the Linux kernel to disable FPGA bridges during FPGA reprogramming and to enable FPGA bridges when FPGA reprogramming is done. This framework is be manufacturer-agnostic, allowing it to be used in interfaces that use the FPGA Manager Framework to reprogram FPGA's. The functions are: * of_fpga_bridge_get * fpga_bridge_put Get/put an exclusive reference to a FPGA bridge. * fpga_bridge_enable * fpga_bridge_disable Enable/Disable traffic through a bridge. * fpga_bridge_register * fpga_bridge_unregister Register/unregister a device-specific low level FPGA Bridge driver. Get an exclusive reference to a bridge and add it to a list: * fpga_bridge_get_to_list To enable/disable/put a set of bridges that are on a list: * fpga_bridges_enable * fpga_bridges_disable * fpga_bridges_put Signed-off-by: Alan Tull <atull@opensource.altera.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-09-08fpga manager: Add hardware dependency to Zynq driverJean Delvare1-0/+1
The Zynq FPGA manager driver serves no purpose on other architectures so hide it unless build-testing. Signed-off-by: Jean Delvare <jdelvare@suse.de> Acked-by: Moritz Fischer <moritz.fischer@ettus.com> Acked-by: Alan Tull <atull@opensource.altera.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-08-04drivers/fpga/Kconfig: fix build failureSudip Mukherjee1-0/+1
While building m32r allmodconfig the build is failing with the error: ERROR: "bad_dma_ops" [drivers/fpga/zynq-fpga.ko] undefined! Xilinx Zynq FPGA is using DMA but there was no dependency while building. Link: http://lkml.kernel.org/r/1464346526-13913-1-git-send-email-sudipm.mukherjee@gmail.com Signed-off-by: Sudip Mukherjee <sudip.mukherjee@codethink.co.uk> Acked-by: Moritz Fischer <moritz.fischer@ettus.com> Cc: Alan Tull <atull@opensource.altera.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2015-10-17fpga manager: Adding FPGA Manager support for Xilinx Zynq 7000Moritz Fischer1-0/+5
This commit adds FPGA Manager support for the Xilinx Zynq chip. The code borrows some from the xdevcfg driver in Xilinx' vendor tree. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-10-07fpga manager: add driver for socfpga fpga managerAlan Tull1-0/+10
Add driver to fpga manager framework to allow configuration of FPGA in Altera SoCFPGA parts. Signed-off-by: Alan Tull <atull@opensource.altera.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Moritz Fischer <moritz.fischer@ettus.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-10-07add FPGA manager coreAlan Tull1-0/+14
API to support programming FPGA's. The following functions are exported as GPL: * fpga_mgr_buf_load Load fpga from image in buffer * fpga_mgr_firmware_load Request firmware and load it to the FPGA. * fpga_mgr_register * fpga_mgr_unregister FPGA device drivers can be added by calling fpga_mgr_register() to register a set of fpga_manager_ops to do device specific stuff. * of_fpga_mgr_get * fpga_mgr_put Get/put a reference to a fpga manager. The following sysfs files are created: * /sys/class/fpga_manager/<fpga>/name Name of low level driver. * /sys/class/fpga_manager/<fpga>/state State of fpga manager Signed-off-by: Alan Tull <atull@opensource.altera.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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