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path: root/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c (follow)
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2021-04-15drm/amdgpu: Calling address translation functions to simplify codesOak Zeng1-2/+1
Use amdgpu_gmc_vram_pa and amdgpu_gmc_vram_cpu_pa to simplify codes. No logic change. Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amdgpu: move mmhub ras_func init to ip specific fileHawking Zhang1-0/+19
mmhub ras is always owned by gpu driver. ras_funcs initialization shall be done at ip level, instead of putting it in common gmc interface file Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amdgpu: split mmhub callbacks into ras and non-ras onesHawking Zhang1-2/+3
mmhub ras is only avaiable in cerntain mmhub ip generation. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amdgpu: do not register df_mca interrupt in certain configHawking Zhang1-2/+4
df/mca ras is not managed by gpu driver when gpu is connected to cpu through xgmi. gpu driver should register x86 mca notifier for umc ras error notification Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amdgpu: split umc callbacks to ras and non-ras onesHawking Zhang1-8/+8
umc ras is not managed by gpu driver when gpu is connected to cpu through xgmi. split umc callbacks into ras and non-ras ones so gpu driver only initializes umc ras callbacks when it manages umc ras. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amdgpu: move xgmi ras functions to xgmi_ras_funcsHawking Zhang1-1/+1
xgmi ras is not managed by gpu driver when gpu is connected to cpu through xgmi. move all xgmi ras functions to xgmi_ras_funcs so gpu driver only initializes xgmi ras functions when it manages xgmi ras. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: Free PDB0 bo before bo_finiLijo Lazar1-2/+1
Cleanup pdb0 bo before bo_fini gets called Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: Replace in_interrupt() usage in gmc_v*_process_interrupt()Sebastian Andrzej Siewior1-1/+1
The usage of in_interrupt() in gmc_v*_process_interrupt() is intended to use a different code path if invoked from the interrupt handler vs invoked from the workqueue. The usage of in_interrupt() in drivers is phased out and Linus clearly requested that code which changes behaviour depending on context should either be separated or the context be conveyed in an argument passed by the caller, which usually knows the context. gmc_v*_process_interrupt() is invoked via the ->process() callback from amdgpu_ih_process() which in turn is invoked either from amdgpu_irq_handler() (the interrupt handler) or from amdgpu_irq_handle_*() which is a workqueue. amdgpu_irq::ih is always processed from the interrupt handler, the other three struct amdgpu_ih_ring members are processed from a workqueue. Replace the in_interrupt() check with a comparison against adev->irq.ih. A similar check is already done to check if the ih pointer is from ih_soft. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: Let KFD use more VMIDs on AldebaranFelix Kuehling1-1/+2
When there is no graphics support, KFD can use more of the VMIDs. Graphics VMIDs are only used for video decoding/encoding and post processing. With two VCE engines, there is no reason to reserve more than 2 VMIDs for that. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: update mmhub client ids for AldebaranAlex Sierra1-13/+16
update mmhub client id table for Aldebaran. Signed-off-by: Alex Sierra <alex.sierra@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: Set up vmid0 PDB0Oak Zeng1-4/+24
If use gart for FB translation, allocate and fill PDB0. Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Christian Konig <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: Use different gart table parameters for 2-level gart tableOak Zeng1-0/+9
If use gart for FB translation, we will squeeze vram into sysvm aperture. This requires 2 level gart table. Add page table depth and page table block size parameters to gmc. This is prepare work to 2-level gart table construction Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Christian Konig <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: Placement of gart and vram in sysvm apertureOak Zeng1-3/+7
If use GART for FB translation, place both vram and gart to sysvm aperture. AGP aperture is not set up in this case because it is not used Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Christian Konig <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: Moved gart_size calculation to mc_init functionsOak Zeng1-0/+2
In amdgpu_gmc_gart_location function, gart_size is adjusted by a smu_prv_buffer_size. This logic shouldn't belong to this function. Move the logic to the mc_init functions Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Christian Konig <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: add mmhub client ids for aldebaranAlex Deucher1-0/+41
Add the mmhub client id table for aldebaran. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: Aldebaran doesn't use semaphoreAmber Lin1-5/+1
Simplify all Aldebaran DIDs into one ASIC type. Signed-off-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: Don't do FB resize under A+A configOak Zeng1-1/+2
Disable PCIe BAR resizing on A+A config. It's not needed because we won't use the PCIe BAR, but it breaks the PCI BAR configuration with the current SBIOS. Error message of FB BAR resize failure under A+A: [ 154.913731] [drm:amdgpu_device_resize_fb_bar [amdgpu]] *ERROR* Problem resizing BAR0 (-22). Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Felix Kuehling <Felix.kuehling@amd.com> Reviewed-by: Christian Koenig <Christian.Koenig@amd.com> Tested-by: Amber Lin <Amber.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: disallow use semaphore on aldebaranHawking Zhang1-0/+7
shall revisit the change later Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: use physical_node_id to calculate aper_baseHawking Zhang1-12/+6
Similar as xgmi connected gpu nodes, physical_node_id * segment_size should be used to calculate the offset of aper_base. The asic type check is redundant. once physical_node_id and segment_size are initialized, it should be count on. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: Clean up mmhub functions for aldebaranOak Zeng1-0/+3
Add more function pointers to amdgpu_mmhub_funcs. ASIC specific implementation of most mmhub functions are called from a general function pointer, instead of calling different function for different ASIC. V2: Split patch into upstreamable and aldebaran Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: new cache coherence change for AldebaranEric Huang1-0/+3
To support new cache coherence HW on A+A platform mainly in KFD. Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Reviewed-by: Oak Zeng <Oak.Zeng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: Fix an omission when adding Aldebaran supportYong Zhao1-1/+2
Aldebaran should be the same as Arcturus in the PTE SNOOPED bit handling. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: define address map for host xgmi link (v3)Rajneesh Bhardwaj1-0/+34
This applies to AMD Accelerated Processing Platforms that support host gpu interconnect throguh a special link (xgmi). Aldebaran systems will support this special feature for utilizing the benefits of host-gpu cache coherence. This change outlines the basic framework for mapping the GPU VRAM (HBM) to system address space making it accesible to the host but managed by the amdgpu driver since this region is marked as reserved memory in host address space by the underlying system firmware. v2: switch to smuio callback function to check the type of host-gpu interface (Hawking) v3: use hub callbacks rather than direct function calls (Alex) Reviewed-by: Oak Zeng <oak.zeng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: Print the IH client ID name when vm fault happensYong Zhao1-2/+3
This gives more information and improves productivity. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-10drm/amdgpu: add gmc v9 block support for AldebaranLe Ma1-0/+3
Add gfx memory controller support Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-09drm/amdgpu/gmc9: fix mmhub client mapping for arcturusAlex Deucher1-34/+32
The hw interface changed on arcturus so the old numbering scheme doesn't work. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-05drm/amdgpu: remove redundant logic related HDPLikun Gao1-18/+0
Remove hdp_flush function from amdgpu_nbio struct as it have been unified into hdp struct. Remove the include about hdp register which was not used. V2: Remove hdp golden setting which is unnecessary. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-05drm/amdgpu: switch hdp callback functions for hdp v4Likun Gao1-19/+2
Switch to use the HDP functions which unified on hdp structure instead of the scattered hdp callback functions. V2: clean up hdp reset ras error count function. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23drm/amdgpu: remove unnecessary asic type checkHawking Zhang1-7/+4
The number of crtc should be 0 for ASICs that don't have display engine. Remove the unnecessary asic type check then. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-08drm/amdgpu: remove amdgpu_ttm_late_init and amdgpu_bo_late_initAlex Deucher1-2/+0
No longer used. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-24drm/amd/amdgpu/gmc_v9_0: Suppy some missing function doc descriptionsLee Jones1-0/+3
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c:382:23: warning: ‘ecc_umc_mcumc_status_addrs’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c:720: warning: Function parameter or member 'vmhub' not described in 'gmc_v9_0_flush_gpu_tlb' drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c:836: warning: Function parameter or member 'flush_type' not described in 'gmc_v9_0_flush_gpu_tlb_pasid' drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c:836: warning: Function parameter or member 'all_hub' not described in 'gmc_v9_0_flush_gpu_tlb_pasid' Acked-by: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-24drm/amd/amdgpu/gmc_v9_0: Remove unused table 'ecc_umc_mcumc_status_addrs'Lee Jones1-35/+0
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c:382:23: warning: ‘ecc_umc_mcumc_status_addrs’ defined but not used [-Wunused-const-variable=] Acked-by: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-24drm/amdgpu: make sure retry faults are handled in a work item on VegaChristian König1-8/+23
Looks like we can't enabled the IH1/IH2 feature for Vega20, make sure retry faults are handled on a separate ring anyway. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-24drm/amdgpu: drop leading zeros from the gmc9 fault addressChristian König1-1/+1
The address space is only 48bit, not 64bit. And the VMHUBs work with sign extended addresses. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-24drm/amdgpu: Fix fall-through warnings for ClangGustavo A. R. Silva1-0/+1
In preparation to enable -Wimplicit-fallthrough for Clang, fix multiple warnings by explicitly adding multiple break statements instead of just letting the code fall through to the next case. Link: https://github.com/KSPP/linux/issues/115 Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-30drm/amdgpu: cleanup gmc_v9_0_process_interruptChristian König1-92/+91
First of all don't snprintf into a char buffer allocated on the stack with a constant hubname. Then cleanup to exit the function early in case of a ratelimit or SRIOV. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-16drm/amdgpu: remove gfxhub_v1_1_funcs setKevin Wang1-9/+1
remove duplicate gfxhub v1.1 function set. put function of gfxhub_v1_1_get_xgmi_info to gfxhub v1_0 function set. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-30drm/amdgpu: drop duplicated ecc check for vega10 (v5)Guchun Chen1-12/+7
The same ECC check has been executed in amdgpu_ras_init for vega10, prior to gmc_v9_0_late_init. v2: drop all atombios helper callings v3: use bit operation v4: correct inline comment, remove parity check statement v5: squash in build fix Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-30drm/amdgpu: use function pointer for gfxhub functionsOak Zeng1-7/+21
gfxhub functions are now called from function pointers, instead of from asic-specific functions. Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-22drm/amdgpu/gmc9: simplify the return expression of gmc_v9_0_suspendLiu Shixin1-6/+1
Simplify the return expression. Signed-off-by: Liu Shixin <liushixin2@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-17amdgpu/gmc_v9: Warn if SDPIF_MMIO_CNTRL_0 is not setShirish S1-1/+4
With IOMMU enabled, if SDPIF_MMIO_CNTRL_0 is not set appropriately the system hangs without any trace during S3. To ease debug and to ensure that the failure, if any, was caused by a race conditions that disabled write access to SDPIF_MMIO_CNTRL_0 register, warn the user about it. Signed-off-by: Shirish S <shirish.s@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-15drm/amdgpu/gmc9: remove mmhub client duplicated caseAlex Deucher1-1/+0
Copy paste typo. Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-08Merge tag 'amd-drm-next-5.10-2020-09-03' of git://people.freedesktop.org/~agd5f/linux into drm-nextDave Airlie1-145/+330
amd-drm-next-5.10-2020-09-03: amdgpu: - RAS fixes - Sienna Cichlid updates - Navy Flounder updates - DCE6 (SI) support in DC - Enable plane rotation - Rework pre-OS vram reservation handling during driver init - Add standard interface to dump GPU metrics table from SMU - Rework tiling and tmz state handling in atomic commits - Pstate fixes - Add voltage and power hwmon interfaces for renoir - SW CTF fixes - S/G display fix for Raven - Print client strings for vmfaults for vega and newer - Manual fan control fixes - Display updates - Reorg power management directory structure - Misc bug fixes - Misc code cleanups amdkfd: - Topology fixes - Add SMI events for thermal throttling and GPU resets radeon: - switch from pci_* to dma_* for dma allocations - PLL fix Scheduler: - Clean up priority levels UAPI: - amdgpu INFO IOCTL query update for TMZ state https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6049 - amdkfd SMI event interface updates https://github.com/RadeonOpenCompute/rocm_smi_lib/tree/therm_thrott From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200903222921.4152-1-alexander.deucher@amd.com
2020-09-03drm/amdgpu/gmc9: print client id string for mmhubAlex Deucher1-9/+230
Print the name of the client rather than the number. This makes it easier to debug what block is causing the fault. Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-03drm/amdgpu/gmc9: print client id string for gfxhubAlex Deucher1-4/+26
Print the name of the client rather than the number. This makes it easier to debug what block is causing the fault. Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-03drm/amdgpu: block ring buffer access during GPU recoveryDennis Li1-4/+7
When GPU is in reset, its status isn't stable and ring buffer also need be reset when resuming. Therefore driver should protect GPU recovery thread from ring buffer accessed by other threads. Otherwise GPU will randomly hang during recovery. v2: correct indent Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Dennis Li <Dennis.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-08-26drm/amdgpu: add pre_asic_init callback for SOC15Alex Deucher1-18/+17
We need to restore some registers prior to running asic init to work around a firmware bug. Acked-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-08-26drm/amdgpu: fix up DCHUBBUB_SDPIF_MMIO_CNTRL_0 handlingAlex Deucher1-2/+5
Properly define this register using a relative offset rather than an absolute offset and use the proper SOC15 macros to access it. It's also DCN, not DCE, so remove it from the DCE12 header. No functional change. Acked-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-08-24drm/amdgpu: refine message print for devices of hiveDennis Li1-1/+1
Using dev_xxx instead of DRM_xxx/pr_xxx to indicate which device of a hive is the message for. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Dennis Li <Dennis.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-08-24drm/amdgpu: refine codes to avoid reentering GPU recoveryDennis Li1-2/+2
if other threads have holden the reset lock, recovery will fail to try_lock. Therefore we introduce atomic hive->in_reset and adev->in_gpu_reset, to avoid reentering GPU recovery. v2: drop "? true : false" in the definition of amdgpu_in_reset Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Dennis Li <Dennis.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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