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path: root/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.h (follow)
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2017-09-26drm/amdgpu/sriov:increate mailbox polling timeoutHorace Chen1-1/+1
increase timeout to 12 seconds,because there may have multiple FLR waiting for done, the waiting time of events may be long, increase to 12s to reduce timeout failure. Signed-off-by: Horace Chen <horace.chen@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-07-14drm/amdgpu: Support passing amdgpu critical error to host via GPU Mailbox.Gavin Wan1-1/+3
This feature works for SRIOV enviroment. For non-SRIOV enviroment, the trans_error function does nothing. The error information includes error_code (16bit), error_flags(16bit) and error_data(64bit). Since there are not many errors, we keep the errors in an array and transfer all errors to Host before amdgpu initialization function (amdgpu_device_init) exit. Signed-off-by: Gavin Wan <Gavin.Wan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29drm/amdgpu/virt: increase mailbox timeout to 5000msPixel Ding1-1/+1
When multiple VFs try to enter exclusive mode at the same time, the looping mechansim doesn't help to ensure each can get it because it only loops active VFs, then the last one has to wait for a long interval. Signed-off-by: Pixel Ding <Pixel.Ding@amd.com> Reviewed-by: Xiangliang.Yu <Xiangliang.Yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu/virt: implement VI virt operation interfacesXiangliang Yu1-0/+55
VI has asic specific virt support, which including mailbox and golden registers init. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Monk Liu <Monk.Liu@amd.com> Signed-off-by: shaoyunl <Shaoyun.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>