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path: root/drivers/gpu/drm/amd/amdgpu/soc15.h (follow)
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2018-11-28drm/amdgpu: Doorbell layout for vega20 and future asicOak Zeng1-0/+1
This introduces new doorbell layout for vega20 and future asics v2: Use enum definition instead of hardcoded value Signed-off-by: Oak Zeng <ozeng@amd.com> Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-28drm/amdgpu: Vega10 doorbell index initializationOak Zeng1-0/+1
v2: Use enum definition instead of hardcoded value v3: Remove unused enum definition Signed-off-by: Oak Zeng <ozeng@amd.com> Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amdgpu: Add nbio 7.4 support for vega20 (v3)Feifei Xu1-0/+1
Some register offset in nbio v7.4 are different with v7.0. We need a seperate nbio_v7_4.c for vega20. v2: fix doorbell range for sdma (Alex) v3: squash in static fix (kbuild test robot) Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17drm/amdgpu/soc15: dynamic initialize ip offset for vega20Feifei Xu1-0/+1
Vega20 need a seperate vega20_reg_init.c due to ip base offset difference. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu: move waiting for VM flush into gmc_v9_0_emit_flush_gpu_tlbChristian König1-1/+2
Keep that at a common place instead of spread over all engines. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu: add PASID mapping for GMC v9Christian König1-1/+1
This way we can see the PASID in VM faults. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu: implement gmc_v9_0_emit_flush_gpu_tlbChristian König1-0/+2
Unify tlb flushing for gmc v9. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-08drm/amdgpu: Avoid use SOC15_REG_OFFSET in static const arrayShaoyun Liu1-0/+18
Handle dynamic offsets correctly in static arrays. Acked-by: Christian Konig <christian.koenig@amd.com> Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-08drm/amdgpu: Dynamic initialize IP base offsetShaoyun Liu1-0/+2
The base offsets of the IP blocks may change across asics even though the relative register offsets are the same for an IP. Handle this dynamically. Acked-by: Christian Konig <christian.koenig@amd.com> Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-24drm/amdgpu: apply nbio7 for Raven (v3)Chunming Zhou1-0/+1
nbio handles misc bus io operations. Handle differences between different nbio bus versions. v2: switch checks from RAVEN to APU (Alex) squash in raven rev id fetch squash in fix uninitalized hdp flush reg index for raven v3: add some missed RAVEN to APU checks (Alex) Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29drm/amdgpu: add common soc15 headersKen Wang1-0/+35
These are used by various IP modules. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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