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path: root/drivers/gpu/drm/amd/amdgpu
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2021-03-23drm/amdgpu: add mmhub client ids for aldebaranAlex Deucher1-0/+41
Add the mmhub client id table for aldebaran. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: enable dpg indirect sram mode on aldebaranJames Zhu1-0/+3
Enable dpg indirect sram mode on aldebaran. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: enable vcn dpg mode on aldebaranJames Zhu1-1/+1
Enable vcn dpg mode on aldebaran Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: enable vcn and jpeg on aldebaranJames Zhu1-2/+2
Enable vcn and jpeg 2.6 on aldebaran. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: Enable swsmu block on aldebaranLijo Lazar1-0/+1
Enable smu13 block on aldebaran Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: switch to cached noretry setting for aldebaranHawking Zhang1-1/+1
global noretry setting now is cached to gmc.noretry Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: bypass hdp read cache invalidation for aldebaran (v2)Hawking Zhang1-0/+3
hdp read cache is removed in aldebaran. don't issue an mmio write or write data packet to hardware. v2: rebase Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: Aldebaran doesn't use semaphoreAmber Lin1-5/+1
Simplify all Aldebaran DIDs into one ASIC type. Signed-off-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: UTLC1 RB SDMA timeout on AldebaranAlex Sierra1-0/+5
[Why] This causes infinite retries on the UTCL1 RB, preventing higher priority RB such as paging RB. [How] Set to one the SDMAx_UTLC1_TIMEOUT registers for all SDMAs. Signed-off-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdpgu: add ATOM_DGPU_VRAM_TYPE_HBM2E vram typeFeifei Xu1-0/+1
0x61 is assigned to HBM2E in atom_dgpu_vram_type. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: retire aldebaran gpu_info firmwareHawking Zhang1-4/+1
driver should use the gfx_info atomfirmware interface Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: query aldebaran gfx_config through atomfirmware i/fHawking Zhang2-1/+22
For ASICs that don't support ip discovery feature, query gfx configuration through atomfirmware interface, rather than gpu_info firmware. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amd/amdgpu: Add smu_pptable module parameterLijo Lazar2-0/+11
Temporarily add smu_pptable module parameter for aldebaran.This is used to force soft PPTable use overriding any VBIOS PPTable. Signed-off-by: Lijo Lazar <Lijo.Lazar@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: Don't do FB resize under A+A configOak Zeng1-1/+2
Disable PCIe BAR resizing on A+A config. It's not needed because we won't use the PCIe BAR, but it breaks the PCI BAR configuration with the current SBIOS. Error message of FB BAR resize failure under A+A: [ 154.913731] [drm:amdgpu_device_resize_fb_bar [amdgpu]] *ERROR* Problem resizing BAR0 (-22). Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Felix Kuehling <Felix.kuehling@amd.com> Reviewed-by: Christian Koenig <Christian.Koenig@amd.com> Tested-by: Amber Lin <Amber.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: pre-map device buffer as cached for A+A configOak Zeng1-2/+7
For A+A configuration, device memory is supposed to be mapped as cachable from CPU side. For kernel pre-map gpu device memory using ioremap_cache Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Christian Koenig <Christian.Koenig@amd.com> Tested-by: Amber Lin <Amber.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: disallow use semaphore on aldebaranHawking Zhang1-0/+7
shall revisit the change later Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: switch to vega20 ih block for aldebaranHawking Zhang1-2/+2
replace vega10 ih block with vega20 ih block for aldebaran. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: correct IH_CHICKEN programming for aldebaranHawking Zhang1-0/+15
For aldebaran, psp firmware won't program IH_CHICKEN. it now depends on driver to program it properly so either bus address or gpu virtual address is just working for ih ring. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: add mmhub error status query callback for aldebaranHawking Zhang1-0/+27
The callback will be invoked to query mmea error status when needed. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Dennis Li<Dennis.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: add mmhub ras error reset callback for aldebaranHawking Zhang1-0/+12
The callback will be invoked to reset mmhub ras error counters when needed. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Dennis Li<Dennis.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: add mmhub ras error query callback for aldebaranHawking Zhang1-49/+687
The callback will be invoked to harvest all kinds of mmhub ras error Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Dennis Li<Dennis.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: add sdma ras error reset callback for aldebaranHawking Zhang1-0/+17
The callback will be invoked to reset sdma ras error counters when needed. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Dennis Li<Dennis.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: add sdma ras error query callback for aldebaranHawking Zhang1-0/+187
The callback will be invoked to harvest all kinds of sdma ras error Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Dennis Li<Dennis.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: add sdma v4_4 ras functionHawking Zhang4-0/+61
sdma ras function is the main structure to support sdma ras on aldebaran. the patch initializes late_init late_fini callbacks. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Dennis Li<Dennis.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: apply sdma golden settings for aldebaranHawking Zhang1-0/+18
perform one-time initialization for sdma registers Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: use physical_node_id to calculate aper_baseHawking Zhang1-12/+6
Similar as xgmi connected gpu nodes, physical_node_id * segment_size should be used to calculate the offset of aper_base. The asic type check is redundant. once physical_node_id and segment_size are initialized, it should be count on. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: skip gds ras workaround for aldebaranHawking Zhang1-1/+2
there won't be any gds useage in either kernel or pm4 anymore for aldebaran. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: init gds for aldebaranHawking Zhang1-0/+10
aldebaran removed gds internal memory for atomic usage. it only supports gws opcode in kernel like barrier, semaphore.etc. there won't be usage of gds in either kernel or pm4 packet. max_wave_id should also be marked as deprecated for aldebaran. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: correct vram_info for HBM2EFeifei Xu1-2/+2
correct atom_vram_info_header_v2_6 and its vram_module. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: support get_vram_info atomfirmware i/f for aldebaranHawking Zhang1-0/+21
Query vram_type, channel_num, channel_width information through atomfirmware i/f Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu:add smu mode1/2 support for aldebaranFeifei Xu4-76/+60
Use MSG_GfxDriverReset for mode reset and retire MSG_Mode1Reset. Centralize soc15_asic_mode1_reset() and nv_asic_mode1_reset()functions. Add mode2_reset_is_support() for smu->ppt_funcs. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: Add DID for aldebaranFeifei Xu1-0/+5
Add 0x7408,0x740C,0x740F in pciidlist. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: added support for register list loading (v2)John Clements1-0/+28
call host to psp cmd to load reg list v2: update to latest interface (Alex) Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: added register list driver ctx (v2)John Clements3-0/+8
updated psp bin parsing and load register list v2: update to latest interface (Alex) Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: updated host to psp mailbox cmd (v2)John Clements1-0/+1
added host to psp cmd for register list v2: update to new interface (Alex) Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: declare smuio v13_0 callbacks as staticHawking Zhang1-2/+2
fix -Wmissing-protoypes warning Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: initialize external rev_id for aldebaranHawking Zhang1-0/+1
add exteranal rev_id for aldebaran Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: declare sdma firmware binary file for aldebaranKevin Wang1-0/+1
declare sdma firmware binary file for aldebaran Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: comments out vcn/jpeg ip blocks for aldebaranHawking Zhang1-2/+2
vcn fw front door loading is not functional. comments out vcn/jpeg ip blocks so people can load amdgpu driver without specify ip_mask module parameter. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: initialize ta firmware for aldebaranHawking Zhang1-0/+5
only xgmi ta is supported at this stage Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: switch to use reg distance member for mmhub v1_7Kevin Wang1-15/+29
switch to use register distance member for mmhub v1_7 instead of hardcode Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: Clean up mmhub functions for aldebaranOak Zeng3-34/+18
Add more function pointers to amdgpu_mmhub_funcs. ASIC specific implementation of most mmhub functions are called from a general function pointer, instead of calling different function for different ASIC. V2: Split patch into upstreamable and aldebaran Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu/jpeg: enable JPEG on aldebaranJames Zhu1-0/+1
enable JPEG on aldebaran Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu/vcn: enable VCN on aldebaranJames Zhu1-0/+2
Enable VCN on aldebaran Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu/nbio: add aldebaran supportJames Zhu1-3/+17
Aldebaran has a new mmBIF_MMSCH1_DOORBELL_RANGE setting. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: skip MEC2_JT initialization for aldebaranHawking Zhang1-2/+3
MEC2_JT is not supported Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: new cache coherence change for AldebaranEric Huang2-2/+31
To support new cache coherence HW on A+A platform mainly in KFD. Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Reviewed-by: Oak Zeng <Oak.Zeng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu/jpeg2.6: Add jpeg2.6 supportJames Zhu2-2/+64
Aldebaran is using jpeg2.6, and the main change is jpeg2.6 using AMDGPU_MMHUB_0, and jpeg2.5 using AMDGPU_MMHUB_1. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: Fix an omission when adding Aldebaran supportYong Zhao1-1/+2
Aldebaran should be the same as Arcturus in the PTE SNOOPED bit handling. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: Fix IH client ID naming tableOak Zeng1-0/+1
Client ID 26 is reserved. Add it to the table. Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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