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2020-05-14drm/amdgpu: turn back rlcg write for gfx_v10Yintian Tao1-8/+6
There is no need to use amdgpu_mm_wreg_mmio_rlc() during initialization time because this interface is only designed for debugfs case to access the registers which are only permitted by RLCG during run-time. Therefore, turn back rlcg write for gfx_v10. If we not turn back it, it will raise amdgpu load failure. [ 54.904333] amdgpu: SMU driver if version not matched [ 54.904393] amdgpu: SMU is initialized successfully! [ 54.905971] [drm] kiq ring mec 2 pipe 1 q 0 [ 55.115416] amdgpu 0000:00:06.0: [drm:amdgpu_ring_test_helper [amdgpu]] *ERROR* ring gfx_0.0.0 test failed (-110) [ 55.118877] [drm:amdgpu_device_init [amdgpu]] *ERROR* hw_init of IP block <gfx_v10_0> failed -110 [ 55.126587] amdgpu 0000:00:06.0: amdgpu_device_ip_init failed [ 55.133466] amdgpu 0000:00:06.0: Fatal error during GPU init Signed-off-by: Yintian Tao <yttao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-14drm/amdgpu: Add AQUIRE_MEM PACKET3 fields defintionAndrey Grodzovsky2-1/+72
Add this for gfx10 and gfx9. v2: Fix identation Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-14Merge tag 'amd-drm-next-5.8-2020-05-12' of git://people.freedesktop.org/~agd5f/linux into drm-nextDave Airlie29-689/+771
amd-drm-next-5.8-2020-05-12: amdgpu: - Misc cleanups - RAS fixes - Expose FP16 for modesetting - DP 1.4 compliance test fixes - Clockgating fixes - MAINTAINERS update - Soft recovery for gfx10 - Runtime PM cleanups - PSP code cleanups amdkfd: - Track GPU memory utilization per process - Report PCI domain in topology Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200512213703.4039-1-alexander.deucher@amd.com
2020-05-12drm/amd/amdgpu: add raven1 part to the gfxoff quirk listTom St Denis1-0/+2
On my raven1 system (rev c6) with VBIOS 113-RAVEN-114 GFXOFF is not stable (resulting in large block tiling noise in some applications). Disabling GFXOFF via the quirk list fixes the problems for me. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2020-05-11drm/amd/amdgpu: remove defined but not used 'crtc_offsets'Jason Yan1-11/+0
Fix the following gcc warning: drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c:65:18: warning: ‘crtc_offsets’ defined but not used [-Wunused-const-variable=] static const u32 crtc_offsets[6] = ^~~~~~~~~~~~ Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Jason Yan <yanaijie@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-11drm/amd/amdgpu: add raven1 part to the gfxoff quirk listTom St Denis1-0/+2
On my raven1 system (rev c6) with VBIOS 113-RAVEN-114 GFXOFF is not stable (resulting in large block tiling noise in some applications). Disabling GFXOFF via the quirk list fixes the problems for me. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-11mm/hmm: remove the customizable pfn format from hmm_range_faultJason Gunthorpe1-25/+10
Presumably the intent here was that hmm_range_fault() could put the data into some HW specific format and thus avoid some work. However, nothing actually does that, and it isn't clear how anything actually could do that as hmm_range_fault() provides CPU addresses which must be DMA mapped. Perhaps there is some special HW that does not need DMA mapping, but we don't have any examples of this, and the theoretical performance win of avoiding an extra scan over the pfns array doesn't seem worth the complexity. Plus pfns needs to be scanned anyhow to sort out any DEVICE_PRIVATE pages. This version replaces the uint64_t with an usigned long containing a pfn and fixed flags. On input flags is filled with the HMM_PFN_REQ_* values, on successful output it is filled with HMM_PFN_* values, describing the state of the pages. amdgpu is simple to convert, it doesn't use snapshot and doesn't use per-page flags. nouveau uses only 16 hmm_pte entries at most (ie fits in a few cache lines), and it sweeps over its pfns array a couple of times anyhow. It also has a nasty call chain before it reaches the dma map and hardware suggesting performance isn't important: nouveau_svm_fault(): args.i.m.method = NVIF_VMM_V0_PFNMAP nouveau_range_fault() nvif_object_ioctl() client->driver->ioctl() struct nvif_driver nvif_driver_nvkm: .ioctl = nvkm_client_ioctl nvkm_ioctl() nvkm_ioctl_path() nvkm_ioctl_v0[type].func(..) nvkm_ioctl_mthd() nvkm_object_mthd() struct nvkm_object_func nvkm_uvmm: .mthd = nvkm_uvmm_mthd nvkm_uvmm_mthd() nvkm_uvmm_mthd_pfnmap() nvkm_vmm_pfn_map() nvkm_vmm_ptes_get_map() func == gp100_vmm_pgt_pfn struct nvkm_vmm_desc_func gp100_vmm_desc_spt: .pfn = gp100_vmm_pgt_pfn nvkm_vmm_iter() REF_PTES == func == gp100_vmm_pgt_pfn() dma_map_page() Link: https://lore.kernel.org/r/5-v2-b4e84f444c7d+24f57-hmm_no_flags_jgg@mellanox.com Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Tested-by: Ralph Campbell <rcampbell@nvidia.com> Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
2020-05-11mm/hmm: remove HMM_PFN_SPECIALJason Gunthorpe1-1/+0
This is just an alias for HMM_PFN_ERROR, nothing cares that the error was because of a special page vs any other error case. Link: https://lore.kernel.org/r/4-v2-b4e84f444c7d+24f57-hmm_no_flags_jgg@mellanox.com Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Reviewed-by: John Hubbard <jhubbard@nvidia.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
2020-05-11drm/amdgpu: remove dead code after hmm_range_fault()Jason Gunthorpe1-10/+6
Since amdgpu does not use the snapshot mode of hmm_range_fault() a successful return already proves that all entries in the pfns are HMM_PFN_VALID, there is no need to check the return result of hmm_device_entry_to_page(). Link: https://lore.kernel.org/r/3-v2-b4e84f444c7d+24f57-hmm_no_flags_jgg@mellanox.com Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
2020-05-11mm/hmm: make hmm_range_fault return 0 or -1Jason Gunthorpe1-2/+2
hmm_vma_walk->last is supposed to be updated after every write to the pfns, so that it can be returned by hmm_range_fault(). However, this is not done consistently. Fortunately nothing checks the return code of hmm_range_fault() for anything other than error. More importantly last must be set before returning -EBUSY as it is used to prevent reading an output pfn as an input flags when the loop restarts. For clarity and simplicity make hmm_range_fault() return 0 or -ERRNO. Only set last when returning -EBUSY. Link: https://lore.kernel.org/r/2-v2-b4e84f444c7d+24f57-hmm_no_flags_jgg@mellanox.com Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Tested-by: Ralph Campbell <rcampbell@nvidia.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
2020-05-08drm/amdgpu: implement soft_recovery for gfx10Alex Deucher1-0/+14
Same as gfx9. This allows us to kill the waves for hung shaders. Acked-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-08drm/amdgpu: enable hibernate support on Navi1XEvan Quan2-0/+3
BACO is needed to support hibernate on Navi1X. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2020-05-08drm/amdgpu: Use GEM obj reference for KFD BOsFelix Kuehling1-2/+3
Releasing the AMDGPU BO ref directly leads to problems when BOs were exported as DMA bufs. Releasing the GEM reference makes sure that the AMDGPU/TTM BO is not freed too early. Also take a GEM reference when importing BOs from DMABufs to keep references to imported BOs balances properly. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Tested-by: Alex Sierra <alex.sierra@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Sierra <alex.sierra@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-08drm/amdgpu: force fbdev into vramAlex Deucher1-2/+1
We set the fb smem pointer to the offset into the BAR, so keep the fbdev bo in vram. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=207581 Fixes: 6c8d74caa2fa33 ("drm/amdgpu: Enable scatter gather display support") Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2020-05-08drm/amdgpu: drop unnecessary cancel_delayed_work_sync on PG ungateEvan Quan2-14/+4
As this is already properly handled in amdgpu_gfx_off_ctrl(). In fact, this unnecessary cancel_delayed_work_sync may leave a small time window for race condition and is dangerous. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-08drm/amdgpu: disable MGCG/MGLS also on gfx CG ungateEvan Quan1-1/+1
Otherwise, MGCG/MGLS will be left enabled. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-08drm/amdgpu: only set DPM_FLAG_NEVER_SKIP for legacy ATPX BOCOAlex Deucher1-1/+4
We only need to set DPM_FLAG_NEVER_SKIP for the legacy ATPX BOCO case. D3cold and BACO work as expected. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-08drm/amdgpu: drop extra runtime pm handling in resume pmopAlex Deucher1-8/+0
The core handles this for us. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-08drm/amdgpu: fix runpm logic in amdgpu_pmops_resumeAlex Deucher1-2/+2
We should be checking whether the driver enabled runtime pm rather than whether the asic supports BOCO or BACO. That said in general they are equivalent unless the user has disabled runpm or it has been disabled for a specific asic. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-08drm/amdgpu: drop pm_runtime_set_activeAlex Deucher1-1/+0
The pci core handles this for us in pci_pm_init. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-08drm/amdgpu: implement soft_recovery for gfx10Alex Deucher1-0/+14
Same as gfx9. This allows us to kill the waves for hung shaders. Acked-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-08drm/amdgpu: cleanup sysfs file handlingNirmoy Das1-24/+12
Create sysfs file using attributes. Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-08drm/amdgpu: enable hibernate support on Navi1XEvan Quan2-0/+3
BACO is needed to support hibernate on Navi1X. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-08drm/amdgpu: use node_id and node_size to calcualte dram_base_addressHawking Zhang3-82/+2
physical_node_id * node_segment_size should be the dram_base_address for current gpu node in xgmi config Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-08drm/amdgpu: switch to common rlc_autoload helperHawking Zhang3-10/+1
drop IP specific psp function for rlc autoload since the autoload_supported was introduced to mark ASICs that support rlc_autoload Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-08drm/amdgpu: drop unused ras ta helper functionHawking Zhang2-32/+0
cure posion command was replaced by ras recovery solution and was not a formal command supported by ras ta anymore Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-08drm/amdgpu: switch to common ras ta helperHawking Zhang3-33/+30
TRIGGER_ERROR is common ras ta command for all the ASICs that support RAS feature. switch to common helper to avoid duplicate implementation per IP generation Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-08drm/amdgpu: switch to common xgmi ta helpersHawking Zhang3-137/+123
get_hive_id/get_node_id/get_topology_info/set_topology_info are common xgmi command supported by TA for all the ASICs that support xgmi link. They should be implemented as common helper functions to avoid duplicated code per IP generation Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-08Merge tag 'amd-drm-next-5.8-2020-04-30' of git://people.freedesktop.org/~agd5f/linux into drm-nextDave Airlie52-353/+738
amd-drm-next-5.8-2020-04-30: amdgpu: - SR-IOV fixes - SDMA fix for Navi - VCN 2.5 DPG fixes - Display fixes - Display stuttering fixes for pageflip and cursor - Add support for handling encrypted GPU memory - Add UAPI for encrypted GPU memory - Rework IB pool handling amdkfd: - Expose asic revision in topology - Add UAPI for GWS (Global Wave Sync) resource management UAPI: - Add amdgpu UAPI for encrypted GPU memory Used by: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4401 - Add amdkfd UAPI for GWS (Global Wave Sync) resource management Thunk usage of KFD ioctl: https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface/blob/roc-2.8.0/src/queues.c#L840 ROCr usage of Thunk API: https://github.com/RadeonOpenCompute/ROCR-Runtime/blob/roc-3.1.0/src/core/runtime/amd_gpu_agent.cpp#L597 HCC code using ROCr API: https://github.com/RadeonOpenCompute/hcc/blob/98ee9f34945d3b5f572d7a4c15cbffa506487734/lib/hsa/mcwamp_hsa.cpp#L2161 HIP code using HCC API: https://github.com/ROCm-Developer-Tools/HIP/blob/cf8589b8c8a40ddcc55fa3a51e23390a49824130/src/hip_module.cpp#L567 Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200430212951.3902-1-alexander.deucher@amd.com
2020-05-07drm/amd/amdgpu: cleanup coding style a bitBernard Zhao1-30/+13
There is DEVICE_ATTR mechanism in separate attribute define. So this change is to use attr array, also use sysfs_create_files in init function & sysfs_remove_files in fini function. This maybe make the code a bit readable. Signed-off-by: Bernard Zhao <bernard@vivo.com> Changes since V1: *Use DEVICE_ATTR mechanism Link for V1: *https://lore.kernel.org/patchwork/patch/1228076/ V2: make array const to fix build errors Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-07drm/amdgpu: Fix bug in RAS invokeJohn Clements1-3/+3
Invoke sequence should abort when ras interrupt is detected before reading TA host shared memory Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-06drm/amdgpu: Use GEM obj reference for KFD BOsFelix Kuehling1-2/+3
Releasing the AMDGPU BO ref directly leads to problems when BOs were exported as DMA bufs. Releasing the GEM reference makes sure that the AMDGPU/TTM BO is not freed too early. Also take a GEM reference when importing BOs from DMABufs to keep references to imported BOs balances properly. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Tested-by: Alex Sierra <alex.sierra@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Sierra <alex.sierra@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-06drm/amdgpu: force fbdev into vramAlex Deucher1-2/+1
We set the fb smem pointer to the offset into the BAR, so keep the fbdev bo in vram. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=207581 Fixes: 6c8d74caa2fa33 ("drm/amdgpu: Enable scatter gather display support") Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-06drm/amdgpu: drop unnecessary cancel_delayed_work_sync on PG ungateEvan Quan2-14/+4
As this is already properly handled in amdgpu_gfx_off_ctrl(). In fact, this unnecessary cancel_delayed_work_sync may leave a small time window for race condition and is dangerous. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-06drm/amdgpu: disable MGCG/MGLS also on gfx CG ungateEvan Quan1-1/+1
Otherwise, MGCG/MGLS will be left enabled. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-06drm/amdgpu: use the BAR if possible in amdgpu_device_vram_access v2Christian König1-0/+26
This should speed up debugging VRAM access a lot. v2: add HDP flush/invalidate Unrevert: RAS issue at root of the issue has been addressed Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Jonathan Kim <Jonathan.Kim@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Kent Russell <kent.russell@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-05drm/amdgpu: allocate large structures dynamicallyArnd Bergmann1-10/+21
After the structure was padded to 1024 bytes, it is no longer suitable for being a local variable, as the function surpasses the warning limit for 32-bit architectures: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:587:5: error: stack frame size of 1072 bytes in function 'amdgpu_ras_feature_enable' [-Werror,-Wframe-larger-than=] int amdgpu_ras_feature_enable(struct amdgpu_device *adev, ^ Use kzalloc() instead to get it from the heap. Fixes: a0d254820f43 ("drm/amdgpu: update RAS TA to Host interface") Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-05amdgpu_acpi: add backlight control for the DC caseAndriy Gapon1-1/+21
This uses backlight_device_set_brightness() to set the brightness level requested via ATIF. Signed-off-by: Andriy Gapon <avg@FreeBSD.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-05drm/amdgpu: Avoid integer overflow in amdgpu_device_suspend_display_audioNathan Chancellor1-1/+1
When building with Clang: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4160:53: warning: overflow in expression; result is -294967296 with type 'long' [-Winteger-overflow] expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4L; ^ 1 warning generated. Multiplication happens first due to order of operations and both NSEC_PER_SEC and 4 are long literals so the expression overflows. To avoid this, make 4 an unsigned long long literal, which matches the type of expires (u64). Fixes: 3f12acc8d6d4 ("drm/amdgpu: put the audio codec into suspend state before gpu reset V3") Link: https://github.com/ClangBuiltLinux/linux/issues/1017 Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-01amd/amdgpu: Limit rlcg write registers only for nv12shaoyunl1-7/+25
Create gfx_v10_0_rlc_funcs_sriov for nv12 with rlcg_write function pointers be initialized so driver can use RLCG to write aceess CSIB and CP_ME_CNTL registers when nv12 in sriov mode Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-01drm/amdkfd: Use a systematic method to calculate queue mask bitYong Zhao1-0/+3
The queue mask used for set_resources always assumes the queue number per pipe is 8, so KFD needs to align with that by using function amdgpu_queue_mask_bit_to_set_resource_bit(). Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-01drm/amdgpu: Rename amdgpu_gfx_kcq_queue_mask_transform()Yong Zhao2-9/+9
Rename it to amdgpu_queue_mask_bit_to_set_resource_bit() to be more specific about its functionality. KFD will use it later. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-01drm/amdgpu: skip reservation of discovery tmr region in pre-NaviHawking Zhang1-3/+5
IP discovery is only supported in Navi series and onwards. There is no need to reserve a portion of vram as discovery tmr region for pre-Navi adapters. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-01drm/amdgpu: re-structue members for ip discoveryHawking Zhang3-35/+38
This is to prepare for initializing discovery tmr size per ASIC type Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-01drm/amdgpu: update the method to set kcq queue maskLikun Gao1-1/+14
Use a common method to set queue mask before set kiq resource. The value of queue mask must suitablt for the designated form. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-01drm/amdgpu: check SMU NULL ptr on gfx hw initLikun Gao1-7/+9
Check SMU NULL ptr before load smu fw. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-01drm/amdgpu: change HWIP from UVD to VCN for VCN2.5Boyuan Zhang1-196/+196
Rename hardware IP name from UVD to VCN to reduce confusion. Hardware IP name UVD and VCN are equivalent for VCN2.5 asics. Use name VCN for future VCN based asics. V2: update description V3: rebase Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-01drm/amdgpu: Add missing parameter description in commentsFelix Kuehling2-0/+2
Kerneldoc comments should describe all function parameters. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-01drm/amdgpu: Changed CU reservation golden settingsOak Zeng1-2/+2
With previous golden settings, compute task can't use reserved LDS (32K) on CU0 and CU1. On 64K LDS system, if compute work group allocate more than 32K LDS, then it can't be dispatched to CU0 and CU1 because of the reservation. This enables compute task to use reserved LDS on CU0 and CU1. Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
2020-05-01drm/amdgpu: drop redundant cg/pg ungate on runpm enterEvan Quan1-3/+0
CG/PG ungate is already performed in ip_suspend_phase1. Otherwise, the CG/PG ungate will be performed twice. That will cause gfxoff disablement is performed twice also on runpm enter while gfxoff enablemnt once on rump exit. That will put gfxoff into disabled state. Fixes: b2a7e9735ab286 ("drm/amdgpu: fix the hw hang during perform system reboot and reset") Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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