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path: root/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c (follow)
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2018-07-10drm/amd/display: make function tables constChristian König1-3/+3
It is good practice to make global function tables const to avoid accidental override. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-10drm/amd/display: fix invalid function table overrideChristian König1-2/+25
Otherwise we try to program hardware with the wrong watermark functions when multiple DCE generations are installed in one system. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-04-11drm/amd/display: Separate mem input constuctors for dce 112 and 120Mikita Lipski1-7/+68
Override the memory input functions for dce120 not to program new registers on dce112. This will fix warnings thrown on Polaris asics. Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-04-11drm/amd/display: Implementing new bandwidth registers for DCE120Mikita Lipski1-17/+41
Registers are added and defined. Programmed to default values. Stutter level watermark register is being set to calculated value. Urgent level registers are programmed to the same as urgency. The programming of the registers is not expected to have any functional difference in performance. Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: Fix warning about uninitialized variableHarry Wentland1-1/+1
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-21drm/amd/display: rename struct mem_input to hubp for dcnYue Hin Lau1-3/+0
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: fix hubp mpcc and opp trackingDmytro Laktyushkin1-0/+2
This should be handled by mi and mpc only Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Move DCHUBBUB block from MemInput to HW sequencer.Zeyu Fan1-53/+1
Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com> Reviewed-by: Zeyu Fan <Zeyu.Fan@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: remove GRPH_SURFACE_UPDATE_IMMEDIATE_EN field programmingDmytro Laktyushkin1-6/+1
This is causing asserts for dce 8 and 10 since they do not contain this field. It is also unnecessary for later DCEs as it is left in it's default state of 0 Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Tidy up mem_input_program_surface_flip_and_addr()Tom St Denis1-16/+9
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: dce 8 - 12 mem_input refactor to new styleDmytro Laktyushkin1-38/+268
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: fix mpo blanking out on one of planes being set not visibleDmytro Laktyushkin1-2/+1
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: refactor bw related variable structure in val_ctxDmytro Laktyushkin1-3/+3
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: increase timeout for dmif deallocRoman Li1-1/+1
In some use-cases, e.g. multiple 4K displays, exisitng wait time for reg update of 30msec timed out during mode setiing that sometimes resulted in system bad state as we continue without waiting for registry update complete. Increasing timeout to 35msec fixes that problem. Signed-off-by: Roman Li <Roman.Li@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Remove DCE12 guardsAlex Deucher1-6/+2
Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Enable DCE12 supportAlex Deucher1-0/+35
This wires DCE12 support into DC and enables it. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: rename BGRA8888 to ABGR8888Tony Cheng1-2/+2
DC actually support ABGR8888 instead of BGRA8888 (R/B swap rather than endian swap) , rename to avoid confusion Signed-off-by: Tony Cheng <tony.cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Pass visible flag into surface programmingYongqiang Sun1-1/+2
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: Moved swizzle parameter translation to dc.Yongqiang Sun1-10/+1
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/display: refactor DCE11 DVVMTony Cheng1-3/+132
- move to new programming style - clean up table to make it obvious what we are programming Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Zeyu Fan <Zeyu.Fan@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/dc: Add dc display driver (v2)Harry Wentland1-0/+384
Supported DCE versions: 8.0, 10.0, 11.0, 11.2 v2: rebase against 4.11 Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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