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path: root/drivers/gpu/drm/amd/display/dc
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2020-05-05drm/amd/display: Move panel_cntl specific register from abm to panel_cntl.Yongqiang Sun18-463/+339
[Why] panel_cntl specific register should be access in panel_cntl object. [How] Move these register access from abm to panel_cntl. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-30drm/amd/display: Fix unsigned comparison to zeroZou Wei1-1/+2
Fixes coccicheck warning: drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c:1398:60-61: WARNING: Unsigned expression compared with zero: j >= 0 Fixes: 238387774232 ("drm/amd/display: fix rn soc bb update") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zou Wei <zou_wei@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-30drm/amd/display: remove set but not used variable 'speakers' in dcn10_stream_encoder.cZheng Bin1-2/+0
Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c:1277:11: warning: variable ‘speakers’ set but not used [-Wunused-but-set-variable] It is introduced by commit 0c41891c81c0 ("drm/amd/display: Refactor stream encoder for HW review"), but never used, so remove it. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zheng Bin <zhengbin13@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-30drm/amd/display: remove set but not used variable 'speakers' in dce_stream_encoder.cZheng Bin1-2/+0
Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c:1339:11: warning: variable ‘speakers’ set but not used [-Wunused-but-set-variable] It is introduced by commit 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)"), but never used, so remove it. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zheng Bin <zhengbin13@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-30drm/amd/display: remove set but not used variable 'pixel_width'Zheng Bin1-7/+0
Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c:137:11: warning: variable ‘pixel_width’ set but not used [-Wunused-but-set-variable] It is introduced by commit 70ccab604049 ("drm/amdgpu/display: Add core dc support for DCN"), but never used, so remove it. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zheng Bin <zhengbin13@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-30drm/amd/display: work around fp code being emitted outside of DC_FP_START/ENDDaniel Kolesa1-8/+23
The dcn20_validate_bandwidth function would have code touching the incorrect registers emitted outside of the boundaries of the DC_FP_START/END macros, at least on ppc64le. Work around the problem by wrapping the whole function instead. Signed-off-by: Daniel Kolesa <daniel@octaforge.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-30drm/amdgpu/dc: Use WARN_ON_ONCE for ASSERTMichel Dänzer1-1/+1
Once should generally be enough for diagnosing what lead up to it, repeating it over and over can be pretty annoying. Signed-off-by: Michel Dänzer <mdaenzer@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-30drm/amd/display: remove duplicate assignment of dcn21_funcs membersJason Yan1-5/+0
Fix the following coccicheck warning: drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c:31:51-52: exit_optimized_pwr_state: first occurrence line 86, second occurrence line 92 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c:31:51-52: optimize_pwr_state: first occurrence line 85, second occurrence line 91 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c:31:51-52: set_cursor_attribute: first occurrence line 71, second occurrence line 89 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c:31:51-52: set_cursor_position: first occurrence line 70, second occurrence line 88 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c:31:51-52: set_cursor_sdr_white_level: first occurrence line 72, second occurrence line 90 Signed-off-by: Jason Yan <yanaijie@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-30drm: Correct DP DSC macro typoRodrigo Siqueira1-1/+1
In the file drm_dp_helper.h we have a macro named DP_DSC_THROUGHPUT_MODE_{0,1}_UPSUPPORTED, the correct name should be DP_DSC_THROUGHPUT_MODE_{0,1}_UNSUPPORTED. This commits adjusts this typo in the header file and in other places that attempt to access this macro. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200429184142.1867987-1-Rodrigo.Siqueira@amd.com
2020-04-30Merge tag 'amd-drm-next-5.8-2020-04-24' of git://people.freedesktop.org/~agd5f/linux into drm-nextDave Airlie64-543/+1927
amd-drm-next-5.8-2020-04-24: amdgpu: - Documentation improvements - Enable FRU chip access on boards that support it - RAS updates - SR-IOV updates - Powerplay locking fixes for older SMU versions - VCN DPG (dynamic powergating) cleanup - VCN 2.5 DPG enablement - Rework GPU scheduler handling - Improve scheduler priority handling - Add SPM (streaming performance monitor) golden settings for navi - GFX10 clockgating fixes - DC ABM (automatic backlight modulation) fixes - DC cursor and plane fixes - DC watermark fixes - DC clock handling fixes - DC color management fixes - GPU reset fixes - Clean up MMIO access macros - EEPROM access fixes - Misc code cleanups amdkfd: - Misc code cleanups radeon: - Clean up safe reg list generation - Misc code cleanups From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200424190827.4542-1-alexander.deucher@amd.com
2020-04-28drm/amd/display: 3.2.83.1Aric Cyr1-1/+1
Update firmware blobs Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-28drm/amd/display: 3.2.83Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-28drm/amd/display: Use cursor locking to prevent flip delaysAric Cyr16-45/+88
[Why] Current locking scheme for cursor can result in a flip missing its vsync, deferring it for one or more vsyncs. Result is a potential for stuttering when cursor is moved. [How] Use cursor update lock so that flips are not blocked while cursor is being programmed. Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-28drm/amd/display: Internal refactoring to abstract color capsKrunoslav Kovac4-3/+146
[Why&How] modules/color calculates various colour operations which are translated to abstracted HW. DCE 5-12 had almost no important changes, but starting with DCN1, every new generation comes with fairly major differences in color pipeline. We would hack it with some DCN checks, but a better approach is to abstract color pipe capabilities so modules/DM can decide mapping to HW block based on logical capabilities, Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-28drm/amd/display: Add set backlight to hw sequencer.Yongqiang Sun7-25/+55
[Why & How] Add set backlight to hw sequencer, dmu communication will be handled in hw sequencer for new asics. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-28drm/amd/display: Add dummy p-state latency bounding box overrideJoshua Aberback2-0/+8
[Why] For debugging, it can be useful to be able to modify the dummy p-state latency, this will make it easier to do so. Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-28drm/amd/display: Add panel cntl id for set backlight level.Yongqiang Sun7-22/+39
[Why & How] Add panel cntl instance when calling set backlight. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-28drm/amd/display: Pass command instead of header into DMUB serviceNicholas Kazlauskas7-47/+75
[Why] We read memory that we shouldn't be touching if the struct isn't a full union dmub_rb_cmd. [How] Fix up all the callers and functions that take in the dmub_cmd_header to use the dmub_rb_cmd instead. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-28drm/amd/display: Update downspread percent to match spreadsheet for DCN2.1Sung Lee1-1/+1
[WHY] The downspread percentage was copied over from a previous version of the display_mode_lib spreadsheet. This value has been updated, and the previous value is too high to allow for such modes as 4K120hz. The new value is sufficient for such modes. [HOW] Update the value in dcn21_resource to match the spreadsheet. Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-28drm/amd/display: Defer cursor update around VUPDATE for all ASICNicholas Kazlauskas1-14/+14
[Why] Fixes the following scenario: - Flip has been prepared sometime during the frame, update pending - Cursor update happens right when VUPDATE would happen - OPTC lock acquired, VUPDATE is blocked until next frame - Flip is delayed potentially infinitely With the igt@kms_cursor_legacy cursor-vs-flip-legacy test we can observe nearly *13* frames of delay for some flips on Navi. [How] Apply the Raven workaround generically. When close enough to VUPDATE block cursor updates from occurring from the dc_stream_set_cursor_* helpers. This could perhaps be a little smarter by checking if there were pending updates or flips earlier in the frame on the HUBP side before applying the delay, but this should be fine for now. This fixes the kms_cursor_legacy test. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-28drm/amd/display: Change viewport limit to 12 for DCN2Sung Lee1-2/+2
[WHY & HOW] Viewport limit was set to 16 pixels due to an issue with MPO on small viewports. This restriction does not apply and the viewport limit can now be lowered. Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-28drm/amd/display: Fail validation if building scaling params failsSung Lee2-7/+11
[WHY & HOW] If building scaling parameters fails, validation should also fail. Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-28drm/amd/display: fix rn soc bb updateDmytro Laktyushkin1-42/+27
Currently RN SOC bounding box update assumes we will get at least 2 clock states from SMU. This isn't always true and because of special casing on first clock state we end up with low disp, dpp, dsc and phy clocks. This change removes the special casing allowing the first state to acquire correct clocks. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-28drm/amd/display: check if REFCLK_CNTL register is presentDmytro Laktyushkin1-1/+2
Check before programming the register since it isn't present on all IPs using this code. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-28drm/amd/display: Add DML variable for future asicsJoshua Aberback3-0/+3
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-28drm/amd/display: clean up some header pathsAnthony Koo3-4/+4
[Why] Some include paths don't need to have relative paths And some types missing [How] make some changes to headers and modify include path Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-28drm/amd/display: Do not disable pipe split if mode is not supportedSung Lee1-2/+7
[WHY] If mode is not supported, pipe split should not be disabled. This may cause more modes to fail. [HOW] Check for mode support before disabling pipe split. This commit was previously reverted as it was thought to have problems, but those issues have been resolved. Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-28drm/amd/display: 3.2.82Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-27drm/amd/display: remove conversion to bool in dc_link_ddc.cJason Yan1-1/+1
The '>' expression itself is bool, no need to convert it to bool again. This fixes the following coccicheck warning: drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c:602:28-33: WARNING: conversion to bool not needed here Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jason Yan <yanaijie@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-27drm/amd/display: remove conversion to bool in dcn20_mpc.cJason Yan1-1/+1
The '==' expression itself is bool, no need to convert it to bool again. This fixes the following coccicheck warning: drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c:455:70-75: WARNING: conversion to bool not needed here Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jason Yan <yanaijie@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-24amdgpu/dc: remove redundant assignment to variable 'option'Colin Ian King1-2/+1
The variable option is being initialized with a value that is never read and it is being updated later with a new value. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-24drm/amd/display: remove redundant assignment to variable retColin Ian King1-1/+1
The variable ret is being initialized with a value that is never read and it is being updated later with a new value. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: fix bug in the logic for panel power controlAnthony Koo1-1/+1
[Why] there's a bug in the new logic for panel power control. the check is wrong, and will skip panel power control under the wrong conditions. [How] fix to check for NULL panel_cntl Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Ashley Thomas <Ashley.Thomas2@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: access ABM from stream resource.Yongqiang Sun1-16/+23
[Why] Since ABM resource is mapped to stream res, all the ABM access should via stream res. [How] Get ABM instance from stream res instead of resource pool. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: blank dp stream before re-train the linkXiaodong Yan1-0/+12
[Why] When link loss happened, monitor can not light up if only re-train the link. [How] Blank all the DP streams on this link before re-train the link, and then unblank the stream Signed-off-by: Xiaodong Yan <Xiaodong.Yan@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: DispalyPort: Write OUI only if panel supports itAurabindo Pillai1-0/+15
[why] Organizational Unit Identifier register is optional, and its presence is published via Down Stream Port Count register. Writing this register when not available will result in errors [how] Read this register and continue writing OUI only if the panel has the support advertised. Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: change from panel to panel cntlAnthony Koo16-248/+250
[Why] it doesn't represent panel specifically, it's more like the control logic for the panel [How] change from panel to panel cntl to make it a bit more clear Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Add HW rotation cursor changes to dcn10Jaehyun Chung1-5/+13
[Why] HW rotation was enabled in DAL3 but hubp cursor calculations for HW roation were only added to dcn20. [How] Add hubp cursor position calculation changes to dcn10. Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Factor in immediate flip support into DLG calculationsNicholas Kazlauskas1-1/+1
[Why] We expect to be able to perform immediate flipping without having to recalculate and update all the watermarks. There are certain usecases today (1080p @ 90deg, 2160p @ 90deg) such that we get a urgency value of 0 for frac_urg_bw_flip because we're explicitly passing in a value of "false" for requiring immediate flip support into the DLG calculation. [How] Always pass in true into the calculation. With this we get a correct non-zero value for frac_urg_bw_flip. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: fix virtual signal dsc setupDmytro Laktyushkin1-1/+1
This prevents dpcd access on virtual links. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: destroy panel on link destructAnthony Koo1-0/+3
[Why] without destroy it is causing a memory leak [How] destroy panel on link destruct Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Wyatt Wood <Wyatt.Wood@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: dmcu wait loop calculation is incorrect in RVPaul Hsieh1-3/+0
[Why] Driver already get display clock from SMU base on MHz, but driver read again and mutiple 1000 cause wait loop value is overflow. [How] remove coding error Signed-off-by: Paul Hsieh <paul.hsieh@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: move panel power seq to new panel structAnthony Koo22-94/+572
[Why] panel power sequencer is currently just sitting in hwseq but it really it tied to internal panels [How] make a new panel struct to contain power sequencer code Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: make all backlight calls link basedAnthony Koo4-28/+27
[Why] Backlight adjustment is tied to a specific display. So make the calls target a link rather than making it a global state. [How] make all backlight calls link based Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Cap certain DML values for Low Pix Clk on DCN2.1Sung Lee1-2/+10
[WHY] In certain conditions with low pixel clock, some values in DML may go past the max due to margining for latency hiding. This causes assertions to get hit. [HOW] If the pixel clock is low and some values are high, cap it to the max. Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Various fixes for PSR on DMCUBWyatt Wood2-1/+45
[Why] - Driver does not recognize new definitions of psr states. - Internal tool is required for checking if psr is active. [How] - Parse psr state correctly so that driver will recognize psr state. - Add visual confirmation that psr is active using existing mechanisms. Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: 3.2.81Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Update MPCC if requestedAric Cyr1-1/+2
Don't skip MPCC tree updates if requested. Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Fix HDR visual confirmAric Cyr1-10/+10
Some cases were incorrectly reporting the wrong visual confirm, even though they were working as expected. Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amd/display: Avoid NULL pointer in set_backlight when ABM is NULLNicholas Kazlauskas1-2/+1
[Why] On ASIC without ABM support (most dGPU) we run into a null pointer dereference when attempting to set the backlight level. [How] This function requires ABM, so fix up the condition to only allow DMCU to be optional. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Wyatt Wood <Wyatt.Wood@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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