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2020-11-16drm/amd/display: Increase sr enter/exit in rn ddr4 watermark tableWyatt Wood1-2/+2
[Why] After removing added latency for HostVM by default, DDR4 sr exit latencies were no longer large enough for some panels and caused underflow. [How] Add 1us to sr enter/exit watermark. Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-16drm/amd/display: 3.2.112Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-16drm/amd/display: correct data typeRaymond Yang1-1/+1
[Why] We should use int for counting variable [How] Change type from bool to uint32_t Signed-off-by: Raymond Yang <rayyang@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-16drm/amd/display: Expose new CRC window propertyWayne Lin5-9/+201
[Why] Instead of calculating CRC on whole frame, add flexibility to calculate CRC on specific frame region. [How] Add few crc window coordinate properties. By default, CRC is calculated on whole frame unless user space specifies the CRC calculation window. Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-16drm/amd/display: [FW Promotion] Release 0.0.42Anthony Koo1-2/+2
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-16drm/amd/display: Add dual edp optimization flag.Yongqiang Sun4-1/+6
[Why & How] Add a dual edp power optimization flag, so driver will notify this flag to dmub FW to determine if apply the power optimization. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-16drm/amd/display: set dpp dto as per requested clk for lower case.Yongqiang Sun1-5/+23
[Why] Blue screen when PNP with multiple monitor or hotplug external monitor when playing video due to dpp dto isn't programmed properly. If lower dpp clock, dpp dto need to be programmed first, and actual dpp clk not avalable yet. [How] set dpp dto as per request clk for lower case before dpp clk update, and after dpp clk updated set dpp dto again with actual dpp clk. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-16drm/amd/display: Add I2C memory low power supportJacky Liao4-3/+32
[Why] The I2C memory blocks should be powered down when they are not in use. This will reduce power consumption. [How] 1. Write to I2C_LIGHT_SLEEP_FORCE to put memory in light sleep when released 2. Added a debug option to allow this behaviour to be turned off Signed-off-by: Jacky Liao <ziyu.liao@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-16drm/amd/display: Detect dynamic backlight support in eDP sinkRoy Chan2-0/+8
[Why] Check if the eDP sink supports the dynamic backlight control [How] Query the dynamic backlight capability in DPCD (eDP case only) Signed-off-by: Roy Chan <roy.chan@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-16drm/amd/display: minor restructuring of pbn calculation functionsWenjing Liu1-4/+10
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-16drm/amd/display: fix cursor calculation for 1xnY rotated display groupsSamson Tam1-5/+57
[Why] Cursor is missing on displays 2 and up when doing rotated display groups in 1xnY setup. Calculation puts cursor out of bounds so it is not enabled. [How] In dcn10_set_cursor_position(), add in viewport.y into cursor calculations for 1xnY rotated display groups. For pipe split, check viewport.y for both pipes and use lower one to normalize cursor position before calculations. Add odm 2:1 support ( using same calculations as pipe split ). Signed-off-by: Samson Tam <Samson.Tam@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-16drm/amd/display: remove unused dml variablesDmytro Laktyushkin3-5/+0
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-16drm/amd/display: Handle Unknown Result for SMU Periodic Retraining on DCN2.1Sung Lee1-1/+2
[WHY & HOW] Currently if VBIOSSMC_Result_UnknownCmd is returned as result of smu msg there is no way to know. Put 1 in param so if 1 is returned, this unknown case is handled. Signed-off-by: Sung Lee <sung.lee@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-16drm/amd/display: Populate hostvm parameter before DML calculationSung Lee3-1/+4
[Why] If the system does not have hostvm enabled, disabling it for DML validation will allow more modes to pass at lower voltage levels. [How] When initializing HostVM save state to hubbub and read back when populating DML pipes from context. Signed-off-by: Sung Lee <sung.lee@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-16drm/amd/display: Hook up PSR residency command to DSATWyatt Wood4-0/+29
[Why] Use GPINT command to get PSR residency from FW. [How] Hook up PSR residency command to DSAT. Since PSR Count Request is deprecated, we will use this. Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-16drm/amd/display: Program dpp dto based on actual dpp clkYongqiang Sun1-3/+26
[Why] dpp dto phase and modulo are programmed with actual dpp global clk and pipe clk. Need to use actual dpp clk to prgoram dpp dto modulo to get more accuracy ratio. [How] assign actual dpp clk to dccg for dpp modulo programming. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-16drm/amd/display: Update dmub codeBhawanpreet Lakha9-21/+70
There is a delta in the dmub code - add boot options - add boot status - remove unused auto_load_is_done func pointer Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-13drm/amd/display: Set new format info for converted metadata.Bas Nieuwenhuizen1-87/+1
If we use DCC modifiers this can increase the number of planes from the initial 1 plane with metadata, so that we get a valid modifier from getfb2. Since the code didn't update the format_info getfb2 would only ever return 1 plane with a modifier for which userspace expects > 1. This moves the format lookup to amdgpu_display.c so we do not have issues when DC is not compiled. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-13drm/amd/display: Add missing pflip irq for dcn2.0Alex Deucher1-2/+2
If we have more than 4 displays we will run into dummy irq calls or flip timout issues. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-13drm/amd/display/dc/core/dc_link_ddc: Move DP_DVI_CONVERTER_ID_{4, 5} to where they're usedLee Jones2-4/+4
This patch fixes >200 warnings. Fixes the following W=1 kernel build warning(s): from drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:31: drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:126:22: warning: ‘DP_DVI_CONVERTER_ID_5’ defined but not used [-Wunused-const-variable=] 126 | static const uint8_t DP_DVI_CONVERTER_ID_5[] = "3393N2"; | ^~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:125:22: warning: ‘DP_DVI_CONVERTER_ID_4’ defined but not used [-Wunused-const-variable=] 125 | static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa"; | ^~~~~~~~~~~~~~~~~~~~~ Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-13drm/amd/display/dc/core/dc_link_dp: Move DP_VGA_LVDS_CONVERTER_ID_{2, 3} to where they're usedLee Jones2-4/+5
This patch fixes >200 warnings. Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:123:22: warning: ‘DP_VGA_LVDS_CONVERTER_ID_3’ defined but not used [-Wunused-const-variable=] 123 | static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA"; | ^~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:121:22: warning: ‘DP_VGA_LVDS_CONVERTER_ID_2’ defined but not used [-Wunused-const-variable=] 121 | static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT"; NB: Repeated ~100 times - snipped for brevity Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-13drm/amdgpu/display: fix FP handling in DCN30Alex Deucher1-37/+6
Adjust the FP handling to avoid nested calls. The nested calls cause the warning below WARNING: CPU: 3 PID: 384 at arch/x86/kernel/fpu/core.c:129 kernel_fpu_begin Fixes: 582e2ce5b4ece3 ("drm/amdgpu/display: FP fixes for DCN3.x (v4)") Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-10amd/display/amdgpu_dm: delete same check in if conditionBernard Zhao1-1/+1
In function amdgpu_dm_connector_get_modes, drm_edid_is_valid will check weather (!edid), no need to check again in the if branch. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Bernard Zhao <bernard@vivo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-10drm/amd/display/dc/basics/fixpt31_32: Move variables to where they're usedLee Jones2-6/+5
Also rid some unused ones. This patch solves 2000 warnings! Fixes the following W=1 kernel build warning(s): In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dc_types.h:33, from drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services_types.h:30, from drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services.h:35, from drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_helpers.c:35: At top level: drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:76:32: warning: ‘dc_fixpt_ln2_div_2’ defined but not used [-Wunused-const-variable=] 76 | static const struct fixed31_32 dc_fixpt_ln2_div_2 = { 1488522236LL }; | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:75:32: warning: ‘dc_fixpt_ln2’ defined but not used [-Wunused-const-variable=] 75 | static const struct fixed31_32 dc_fixpt_ln2 = { 2977044471LL }; | ^~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:74:32: warning: ‘dc_fixpt_e’ defined but not used [-Wunused-const-variable=] 74 | static const struct fixed31_32 dc_fixpt_e = { 11674931555LL }; | ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:73:32: warning: ‘dc_fixpt_two_pi’ defined but not used [-Wunused-const-variable=] 73 | static const struct fixed31_32 dc_fixpt_two_pi = { 26986075409LL }; | ^~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:72:32: warning: ‘dc_fixpt_pi’ defined but not used [-Wunused-const-variable=] 72 | static const struct fixed31_32 dc_fixpt_pi = { 13493037705LL }; | ^~~~~~~~~~~ Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-10drm/amd/display: cap dpp dto phase not more than modulo.Yongqiang Sun1-21/+25
[Why] 4K monitor shows corruption if dpp dto phase is larger than modulo. [How] cap phase value never larger than modulo. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-10drm/amd/display: check actual clock value.Yongqiang Sun3-3/+16
[Why] Actual dpp/disp clock PMFW set are always equal or more than requested. Need to cache the actual clock for debugging purpose. [How] Add actuall dpp/disp clk in clock manager and save it when set clocks. Add an ASSERT in case of actual clock less than requested. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-10drm/amd/display: 3.2.111Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-10drm/amd/display: [FW Promotion] Release 0.0.41Anthony Koo1-2/+2
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-10drm/amd/display: Check other planes for iflip only if GSL already enabledAlvin Lee1-5/+7
[Why] We don't want GSL to be enabled when only updating plane address [How] Only check other pipes for immediate flip if GSL is already enabled Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-10drm/amd/display: Explicitly disable cursor when disabling CRTCVictor Lu1-0/+10
[why] On DCE, the cursor is not being disabled on commits where there is no CRTC or FB enabled. [how] Explicitly disable the cursor in the commit tail only if the pending commit disables the CRTC. Signed-off-by: Victor Lu <victorchengchi.lu@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-10drm/amd/display: update dpp dto phase and modulo.Yongqiang Sun5-6/+166
[Why & How] Program modulo with ref dpp clk Mhz/10. Program phase with pipe dpp clk Mhz /10. DMUB FW could use these value to determine optimization clk for PSR power saving. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-10drm/amd/display: force use sRGB for video TF is sRGB or BT709Jing Zhou7-0/+7
[Why] When mpo enabled, video comes is 709. Desktop use sRGB. So color change easily noticeable especially when switch between mpo/non-mpo. [How] Force use sRGB for video TF is sRGB or BT709. DCN1/DCN2 use predefined type with YUV. DCN3 use distributed points type with YUV. Signed-off-by: Jing Zhou <Jing.Zhou@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-10drm/amd/display: Only wait for flip pending on immediate flipsAric Cyr1-13/+14
[Why] We want to make sure all immediate flips are completed before locking the pipes, but not pipes that are not flip immediate as they will be locked by the OTG [How] Skip non flip immediate pipes when checking for flip pending. Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-10drm/amd/display: Move common speakersToChannels definition to hw_shared.hEric Bernstein5-247/+85
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-10drm/amd/display: correct dml dsc bpc assignmentDmytro Laktyushkin1-2/+1
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-10drm/amd/display: Engage PSR synchronouslyKrunoslav Kovac12-76/+129
[Why & How] The intended use is to force PSR into active state and ignore all events until explicit EXIT. A new event force_static is added to power module. It is then sent to FW. Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-10drm/amd/display: Prevent freesync power optimization during validationIsabel Zhang6-26/+47
[Why] Due to the freesync power optimization increasing vtotal, the driver believes that MPO is supported. MPO is turned on. Freesync then exits, MPO can no longer be supported and immediate flip fails. This causes corruption on the panel. [How] Avoid the freesync optimization when doing validation so in the case freesync exits, driver can still support the configuration. Signed-off-by: Isabel Zhang <isabel.zhang@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-10drm/amd/display: Add fallback to prefetch mode 1 if 0 failsIsabel Zhang2-7/+23
[Why] In some cases, prefetch mode 0 is unsupported but prefetch 1 is supported. Due to previous change always forcing prefetch mode to 0, we are failing bandwidth validation in cases where we should not. [How] By default try prefetch mode 0 but in the case validation fails, attempt to do prefetch mode 1 to see if it is supported. Signed-off-by: Isabel Zhang <isabel.zhang@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-10drm/amdgpu: Add and use seperate reg headers for dcn302Bhawanpreet Lakha1-2/+2
Currently we are using dcn3 reg headers for dcn302. The offsets are different between the two so they need seperate headers. Add dcn302 header files and use these instead of dcn3 header Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-10Merge v5.10-rc3 into drm-nextDaniel Vetter1-0/+4
We need commit f8f6ae5d077a ("mm: always have io_remap_pfn_range() set pgprot_decrypted()") to be able to merge Jason's cleanup patch. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2020-11-10Merge tag 'amd-drm-next-5.11-2020-11-05' of git://people.freedesktop.org/~agd5f/linux into drm-nextDave Airlie186-1297/+10643
amd-drm-next-5.11-2020-11-05: amdgpu: - Add initial support for Vangogh - Add support for Green Sardine - Add initial support for Dimgrey Cavefish - Scatter/Gather display support for Renoir - Updates for Sienna Cichlid - Updates for Navy Flounder - SMU7 power improvements - Modifier support for gfx9+ - CI BACO fixes - Arcturus SMU fixes - Lots of code cleanups - DC fixes - Kernel doc fixes - Add more GPU HW client information to page fault error logging - MPO clock tuning for RV - FP fixes for DCN3 on ARM and PPC radeon: - Expose voltage via hwmon on Sumo APUs amdkfd: - Fix unique id handling - Misc fixes From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201105222749.201798-1-alexander.deucher@amd.com
2020-11-06Merge tag 'drm-fixes-2020-11-06-1' of git://anongit.freedesktop.org/drm/drmLinus Torvalds4-0/+17
Pull drm fixes from Dave Airlie: "It's Friday here so that means another installment of drm fixes to distract you from the counting process. Changes all over the place, the amdgpu changes contain support for a new GPU that is close to current one already in the tree (Green Sardine) so it shouldn't have much side effects. Otherwise imx has a few cleanup patches and fixes, amdgpu and i915 have around the usual smattering of fixes, fonts got constified, and vc4/panfrost has some minor fixes. All in all a fairly regular rc3. We have an outstanding nouveau regression, but the author is looking into the fix, so should be here next week. I now return you to counting. fonts: - constify font structures. MAINTAINERS: - Fix path for amdgpu power management amdgpu: - Add support for more navi1x SKUs - Fix for suspend on CI dGPUs - VCN DPG fix for Picasso - Sienna Cichlid fixes - Polaris DPM fix - Add support for Green Sardine amdkfd: - Fix an allocation failure check i915: - Fix set domain's cache coherency - Fixes around breadcrumbs - Fix encoder lookup during PSR atomic - Hold onto an explicit ref to i915_vma_work.pinned - gvt: HWSP reset handling fix - gvt: flush workaround - gvt: vGPU context pin/unpin - gvt: mmio cmd access fix for bxt/apl imx: - drop unused functions and callbacks - reuse imx_drm_encoder_parse_of - spinlock rework - memory leak fix - minor cleanups vc4: - resource cleanup fix panfrost: - madvise/shrinker fix" * tag 'drm-fixes-2020-11-06-1' of git://anongit.freedesktop.org/drm/drm: (55 commits) drm/amdgpu/display: remove DRM_AMD_DC_GREEN_SARDINE drm/amd/display: Add green_sardine support to DM drm/amd/display: Add green_sardine support to DC drm/amdgpu: enable vcn support for green_sardine (v2) drm/amdgpu: enable green_sardine_asd.bin loading (v2) drm/amdgpu/sdma: add sdma engine support for green_sardine (v2) drm/amdgpu: add gfx support for green_sardine (v2) drm/amdgpu: add soc15 common ip block support for green_sardine (v3) drm/amdgpu: add green_sardine support for gpu_info and ip block setting (v2) drm/amdgpu: add Green_Sardine APU flag drm/amdgpu: resolved ASD loading issue on sienna amdkfd: Check kvmalloc return before memcpy drm/amdgpu: update golden setting for sienna_cichlid amd/amdgpu: Disable VCN DPG mode for Picasso drm/amdgpu/swsmu: remove duplicate call to smu_set_default_dpm_table drm/i915: Hold onto an explicit ref to i915_vma_work.pinned drm/i915/gt: Flush xcs before tgl breadcrumbs drm/i915/gt: Expose more parameters for emitting writes into the ring drm/i915: Fix encoder lookup during PSR atomic check drm/i915/gt: Use the local HWSP offset during submission ...
2020-11-04drm/amdgpu/display: FP fixes for DCN3.x (v4)Alex Deucher5-7/+104
Add proper FP_START/END handling and adjust Makefiles per previous asics. v2: fix up harder. v3: fix clkmgr Makefile for dcn30 v4: fix old gcc handling is only required for x86 Build-tested-by: Nathan Chancellor <natechancellor@gmail.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> (v1) Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> (v1) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-04drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)Alex Deucher76-599/+79
Avoids confusion in configurations. v2: fix build when CONFIG_DRM_AMD_DC_DCN is disabled v3: rebase on latest code Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> (v1) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-04drm/amd/display: fix psr panel lightupRoman Li1-1/+1
[Why] The change for correct asic type check caused a psr regression due to incorrect chip family id for Raven. [How] Use correct family id. Signed-off-by: Roman Li <roman.li@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-04drm/amdgpu/display: remove DRM_AMD_DC_GREEN_SARDINEAlex Deucher5-20/+0
No need for a separate config option at this point. Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-04drm/amd/display: Add green_sardine support to DMRoman Li1-0/+12
Display Manager support for green_sardine Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-04drm/amd/display: Add green_sardine support to DCRoman Li4-0/+25
Display Core support for green_sardine Signed-off-by: Roman Li <Roman.Li@amd.com> Acked-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-03Merge tag 'docs-5.10-warnings' of git://git.lwn.net/linuxLinus Torvalds2-4/+4
Pull documentation build warning fixes from Jonathan Corbet: "This contains a series of warning fixes from Mauro; once applied, the number of warnings from the once-noisy docs build process is nearly zero. Getting to this point has required a lot of work; once there, hopefully we can keep things that way. I have packaged this as a separate pull because it does a fair amount of reaching outside of Documentation/. The changes are all in comments and in code placement. It's all been in linux-next since last week" * tag 'docs-5.10-warnings' of git://git.lwn.net/linux: (24 commits) docs: SafeSetID: fix a warning amdgpu: fix a few kernel-doc markup issues selftests: kselftest_harness.h: fix kernel-doc markups drm: amdgpu_dm: fix a typo gpu: docs: amdgpu.rst: get rid of wrong kernel-doc markups drm: amdgpu: kernel-doc: update some adev parameters docs: fs: api-summary.rst: get rid of kernel-doc include IB/srpt: docs: add a description for cq_size member locking/refcount: move kernel-doc markups to the proper place docs: lockdep-design: fix some warning issues MAINTAINERS: fix broken doc refs due to yaml conversion ice: docs fix a devlink info that broke a table crypto: sun8x-ce*: update entries to its documentation net: phy: remove kernel-doc duplication mm: pagemap.h: fix two kernel-doc markups blk-mq: docs: add kernel-doc description for a new struct member docs: userspace-api: add iommu.rst to the index file docs: hwmon: mp2975.rst: address some html build warnings docs: net: statistics.rst: remove a duplicated kernel-doc docs: kasan.rst: add two missing blank lines ...
2020-11-02drm/amdgpu/display: fix warnings when CONFIG_DRM_AMD_DC_DCN is not setAlex Deucher1-1/+4
Properly protect the relevant code with CONFIG_DRM_AMD_DC_DCN. Fixes: 0b08c54bb7a3 ("drm/amd/display: Fix the display corruption issue on Navi10") Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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