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2022-08-29drm/amd/display: clean up some inconsistent indentingsYang Li1-3/+3
The indentation of statements in the same curly bracket should be consistent. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1892 Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: clean up some inconsistent indentingsYang Li1-10/+10
The indentation of statements in the same curly bracket should be consistent. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1890 Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1891 Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: clean up some inconsistent indentingsYang Li1-5/+8
The indentation of statements in the same curly bracket should be consistent. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1886 Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: clean up one inconsistent indentingYang Li3-9/+12
1. The indentation of statements in the same curly bracket should be consistent. 2. Variable declarations in the same function should be aligned. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1887 Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1888 Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1889 Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: remove redundant vertical_line_start variableJinpeng Cui1-4/+1
Return value from expression directly instead of taking this in another redundant variable. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: Jinpeng Cui <cui.jinpeng2@zte.com.cn> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Correct cursor position on horizontal mirrorMartin Tsai4-32/+63
[Why] Incorrect cursor position will induce system hang on pipe split. [How] 1.Handle horizontal mirror on rotation, 2.Correct cursor set on piep split. Reviewed-by: Ariel Bernstein <Eric.Bernstein@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Martin Tsai <martin.tsai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Fix black flash when switching from ODM2to1 to ODMBypassVladimir Stempen1-1/+2
[Why] On secondary display hotplug we switch primary stream from ODM2to1 to ODMBypass mode. Current logic will trigger disabling front end for this stream. [How] We need to check if prev_odm_pipe is equal to NULL in order to disable dangling planes in this scenario. Reviewed-by: Ariel Bernstein <Eric.Bernstein@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Vladimir Stempen <vladimir.stempen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Fix check for stream and planeEthan Wellenreiter1-1/+1
[WHY] Function wasn't returning false when it had a no stream [HOW] Made it return false when it had no stream. Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Ethan Wellenreiter <Ethan.Wellenreiter@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Re-initialize viewport after pipe mergeEthan Wellenreiter1-0/+9
[Why] Pipes get merged in preparation for SubVP but if they don't get used, and are in ODM or some other multi pipe config, it would calculate the voltage level with a viewport of just one pipe from when they were split resulting in too low of a voltage level. [How] Made it so that the viewport and other timing settings get rebuilt and re- initialized after the pipe merge, before calculating the voltage level so it would calculate it correctly. Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Ethan Wellenreiter <Ethan.Wellenreiter@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Use correct plane for CAB cursor size allocationAurabindo Pillai1-11/+21
[Why&How] plane and stream variables used for cursor size allocation calculation were stale from previous iteration. Redo the iteration to find the correct cursor plane for the calculation. Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: 3.2.201Aric Cyr1-1/+1
Reviewed-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Add visual confirm color support for SubVPLeo (Hanghong) Ma4-0/+46
[Why && How] We would like to have visual confirm color support for SubVP. 1. Set visual confirm color to red: SubVP is enable on this display; 2. Set visual confirm color to green: SubVP is enable on other display and DRR is on this display; 3. Set visual confirm color to blue: SubVP is enable on other display and DRR is off on this display; Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: [FW Promotion] Release 0.0.132.0Anthony Koo1-2/+1
- Fix comment to indicate correct visual confirm option Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Add comments.Ian Chen1-0/+1
Reviewed-by: Dennis Chan <dennis.chan@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Ian Chen <ian.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Revert "program k1/k2 divider for virtual signal for DCN32"Aurabindo Pillai1-1/+1
[Why & How] This reverts commit e6cf22ef5fae493a99e162c3f2e7233448d2b970 since it causes a SubVP related regression: "Switching between windowed video and fullscreen can intermittently cause black screen" Fixes: e6cf22ef5fae49 ("drm/amd/display: program k1/k2 divider for virtual signal for DCN32") Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Fix primary EDP link detectionIswara Nagulendran2-12/+13
[HOW&WHY] EDP link detection must be updated to support a primary EDP with a link index of greater than 0. * SWDEV-342936 - dc: DSC bringup for SAG 1.5 [WHY] SmartAccess Graphics 1.5 (a.k.a SmartMux 1.5) requires seamless switching between GPUs with DSC enabled. [HOW] Moved DSC programming to apply_single_control_ctx_to_hw before the stream enablement logic to ensure the CRC checker provides valid values for non-black frames allowing the system to come out of forced PSR on d2i. Added additional logic to both generate a black frame through setVisibility calls and keep track of the CRCs values for this black frame when coming out of forced PSR. Updating logic for DalRegKey_DisableDSC to disable DSC on EDP and all ports for systems. [CLEANED] dc: Moved DSC programming to before stream enablement [HOW&WHY] Moved DSC programming to apply_single_control_ctx_to_hw before the stream enablement logic. Co-authored-by: sregolui <sregolui@amd.com> Reviewed-by: Jayendran Ramani <Jayendran.Ramani@amd.com> Reviewed-by: Harry Vanzylldejong <Harry.Vanzylldejong@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: sregolui <sregolui@amd.com> Signed-off-by: Iswara Nagulendran <Iswara.Nagulendran@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: fix wrong register accessCharlene Liu2-0/+4
[why] fw version check was for release branch. for staging, it has a chance to enter wrong code path. Reviewed-by: Hansen Dsouza <hansen.dsouza@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: use actual cursor size instead of max for CAB allocationAurabindo Pillai1-1/+14
[Why&How] When calculating allocation for cursor size, get the real cursor through the HUBP instead of using the maximum cursor size for more optimal allocation Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: disable display fresh from MALL on an edge case for DCN321Aurabindo Pillai1-16/+27
[Why&How] When using a 4k monitor when cursor caching is not supported due to framebuffer being on an uncacheable address, enabling display refresh from MALL would trigger corruption if SS is enabled. Prevent entering SS if we are on the edge case and cursor caching is not possible. Do this only if cursor size larger than a 64x64@4bpp. Pull the cursor size calculation out of if condition since cursor address may not be set on all platforms Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Fix CAB cursor size allocation for DCN32/321Aurabindo Pillai1-1/+1
For calculating cursor size allocation, surface size was used, resulting in over allocation Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Missing HPO instance addedLeo Chen1-0/+1
[Why & How] Number of encoder is set to 4 but only 3 instances are created. Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Leo Chen <sancchen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Refactor edp dsc codes.Ian Chen7-8/+48
Refactor edp dsc codes. We split out edp dsc config from "global" to "per-panel" config settings. Reviewed-by: Mike Hsieh <mike.hsieh@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Ian Chen <ian.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: SubVP missing scaling caseAlvin Lee2-3/+13
[Description] For SubVP scaling case we have to combine the plane scaling and stream scaling. Use UCLK dummy p-state WM for FCLK WM set C [Description] For DCN32/321 program dummy UCLK P-state watermark into FCLK watermark set C register. Reviewed-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Add support for visual confirm colorLeo (Hanghong) Ma7-2/+84
[Why] We want to get the visual confirm color of the bottom-most pipe for test automation. [How] Save the visual confirm color to plane_state before program to MPC; Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Allow PHY state update between same statesTaimur Hassan1-3/+0
[Why & How] In some cases, there are calls to transition from TX_ON to TX_ON, such as when using MST or during resolution change. This is expected, so allow HW programming to continue. Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Cleanup PSR flagGabe Teeger7-11/+5
[Why] enable_sw_cntl_psr flag is not needed. For PSR1 and PSR2, we should be passing dirty rectangle and cursor updates to FW regardless of enable_sw_cntl_psr flag. [How] Remove enable_sw_cntl_psr flag from driver. Send cursor info and dirty rectagle status to dmub only in the case of dcn31 and above. Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Robin Chen <robin.chen@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Gabe Teeger <gabe.teeger@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Cursor lag with PSR1 eDPGabe Teeger1-5/+1
[Why] On edp with psr1, we do not provide updates of the cursor position regularly to firmware like with PSR2. To send updates regularly, the flag enable_sw_cntl_psr has to equal 1, but cursor update should be provided regularly to FW regardless of that flag. [How] Ensure that we always send cursor updates to firmware when PSR version equals 1. Reviewed-by: Robin Chen <robin.chen@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Gabe Teeger <gabe.teeger@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Add DC debug option to force LTTPR modeMichael Strauss2-0/+5
[WHY] Useful for external teams debugging LTTPR issues Reviewed-by: George Shen <George.Shen@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: add a override flag as wa for some specific dongleLeo Chen1-0/+1
[Why & How] Add a override flag as wa for some specific dongle Co-authored-by: Leo Chen <sancchen@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Leo Chen <SanChuan.Chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Only commit SubVP state after pipe programmingAlvin Lee1-8/+7
[Description] We only want to commit the SubVP config to DMCUB after the main and phantom pipe programming has completed. Commiting the state early can cause issues such as P-State being allowed by the HW early which causes the SubVP state machine to go into a bad state Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Remove assert from PHY state updateTaimur Hassan1-3/+1
[Why & How] In some cases, there are calls to transition from TX_ON to TX_ON. This is expected, so do not assert. However, these are redundant, so return prematurely. Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: set dig fifo read start level to 7 before dig fifo resetWang Fudong1-0/+5
[Why] DIG_FIFO_ERROR = 1 caused mst daisy chain 2nd monitor black. [How] We need to set dig fifo read start level = 7 before dig fifo reset during dig fifo enable according to hardware designer's suggestion. If it is zero, it will cause underflow or overflow and DIG_FIFO_ERROR = 1. Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Wang Fudong <Fudong.Wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Fix OTG H timing reset for dcn314Duncan Ma1-1/+2
[Why] When ODM is enabled, H timing control register reset to 0. Div mode manual field get overwritten causing no display on certain modes for dcn314. [How] Use REG_UPDATE instead of REG_SET to set div_mode field. Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Duncan Ma <duncan.ma@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Refine aux transaction before retrieve capsLewis Huang1-11/+34
[Why] LTTPR caps will read fail if aux channel is not active. [How] 1.Perform 600 read upto 10 retry with 1ms delay in between. 2.If fail, return false and trigger another retry detection. 3.If pass, read LTTPR caps in retrieve link caps. Reviewed-by: Jimmy Kizito <Jimmy.Kizito@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Lewis Huang <Lewis.Huang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Fix DCN32 DPSTREAMCLK_CNTL programmingGeorge Shen2-6/+6
[Why] Each index in the DPSTREAMCLK_CNTL register phyiscally maps 1-to-1 with HPO stream encoder instance. On the other hand, each index in DTBCLK_P_CNTL physically maps 1-to-1 with OTG instance. Current DCN32 DPSTREAMCLK_CLK programing assumes that OTG instance always maps 1-to-1 with HPO stream encoder instance. This is not always guaranteed and can result in blackscreen. [How] Program the correct dpstreamclk instance with the correct dtbclk_p source. Reviewed-by: Ariel Bernstein <Eric.Bernstein@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Don't choose SubVP display if ActiveMargin > 0Alvin Lee3-4/+20
[Description] There can be SubVP scheduling issues if a SubVP display is chosen has ActiveDramClockChangeLatency > 0. Block this case for now, and enable Vactive case (later) to handle this. Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Set ODM policy based on number of DSC slicesTaimur Hassan3-2/+8
[Why & How] Add addtional check in CalculateODMMode for cases where the ODM combine is needed due to number of DSC slices. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: 3.2.200Aric Cyr1-1/+1
This version brings along following fixes: - Modify pipe split policy - Fix odm 2:1 policy in 4k144 mode - Correct HDMI ODM combine policy - Change AUX NACK behavior - Change runtime initialization for DCN32/321 - Fix cursor flicker in PSRSU - Fix k1/k2 divider for virtual signal for DCN32 - Free phantom plane after removing the context - Add interface to track PHY state - Add SubVP scaling case - Add log clock table for SMU - Fix atomic_check check - Fix SMU 13.0.0 driver_if header - Fix doorbells allocation Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-29drm/amd/display: Fix variable dereferenced before checksunliming1-1/+3
Fixes the following smatch warning: drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dmub_srv.c:311 dc_dmub_srv_p_state_delegate() warn: variable dereferenced before check 'dc' (see line 309) Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: sunliming <sunliming@kylinos.cn> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-25drm/amd/display: enable PCON support for dcn314Roman Li1-0/+1
[Why] DCN314 supports PCON. [How] Explicitly enable it in dcn314 resources. Signed-off-by: Roman Li <roman.li@amd.com> Reviewed-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-25drm/amd: remove possible condition with no effect (if == else)Bernard Zhao1-2/+0
This patch fix cocci warning: drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c:1816:6-8: WARNING: possible condition with no effect (if == else). Signed-off-by: Bernard Zhao <bernard@vivo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-25drm/amd: remove possible condition with no effect (if == else)Bernard Zhao1-7/+2
This patch fix cocci warning: drivers/gpu/drm/amd/display/dc/core/dc.c:3335:2-4: WARNING: possible condition with no effect (if == else). Signed-off-by: Bernard Zhao <bernard@vivo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-25drm/amd: fix potential memory leakBernard Zhao1-0/+1
This patch fix potential memory leak (clk_src) when function run into last return NULL. Signed-off-by: Bernard Zhao <bernard@vivo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-25drm/amd: fix potential memory leakBernard Zhao1-0/+1
This patch fix potential memory leak (clk_src) when function run into last return NULL. s/free/kfree/ - Alex Signed-off-by: Bernard Zhao <bernard@vivo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-25drm/amd/display: Remove redundant check in atomic_checkRoman Li1-3/+0
[Why] We have 2 back-to-back checks for skipping connectors. Logically one of them will do the job. [How] Remove redundant check. Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-25drm/amd/display: Adding log clock table from SMULeo Chen3-0/+140
[Why & How] Adding log for clock table from SMU helps with the debugging process. Implemented using DC_LOG_SMU to output log. Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Leo Chen <sancchen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-25drm/amd/display: Uncomment SubVP scaling caseAlvin Lee1-3/+2
[Description] Uncomment scaling cmd assignment since FW headers are now promoted. Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-25drm/amd/display: Add interface to track PHY stateAlvin Lee11-13/+88
[Why] Sometimes pixel clock needs to remain active after transmitter disable. [How] Use update_phy_state to track PHY state after stream enable/disable and program pixel clock as needed. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-25drm/amd/display: Free phantom plane and stream properlyAlvin Lee1-0/+13
[Description] Refcount is incremented on allocation and when adding to the context. Therefore we must release the phantom plane and stream after removing from the context. Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-25drm/amd/display: program k1/k2 divider for virtual signal for DCN32Aurabindo Pillai1-1/+1
[Why&How] When using IGT, kms_bw multi display tests trigger an assert since we ignore virtual signal type. k1/k2 dividers should be correctly programmed if VSYNC needs to be correct. Add the appropriate condition to the if arm to fix this. Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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