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2022-07-25drm/amd/display: Create a file dedicated for CRTCRodrigo Siqueira4-433/+516
[Why] The amdgpu_dm file contains most of the code that works as an interface between DRM API and DC. As a result, this file becomes very large since it comprises multiple abstractions such as CRTC manipulation. [How] This commit extracts the CRTC code to its specific file named amdgpu_dm_crtc. This change does not change anything inside the functions; the only exception is converting some static functions to a global function. v2: fix ifdef merge mix up (Alex) Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-21Merge tag 'amd-drm-fixes-5.19-2022-07-20' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixesDave Airlie1-8/+19
amd-drm-fixes-5.19-2022-07-20: amdgpu: - Drop redundant buffer cleanup that can lead to a segfault - Add a bo_list mutex to avoid possible list corruption in CS Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220720210917.6202-1-alexander.deucher@amd.com
2022-07-20drm/amd/display: Create a file dedicated to planesRodrigo Siqueira4-1617/+1878
[Why] The amdgpu_dm file contains most of the code that works as an interface between DRM API and DC. As a result, this file becomes very large since it comprises multiple abstractions such as plane manipulation. [How] This commit extracts the plane code to its specific file named amdgpu_dm_plane. This change does not change anything inside the functions; the only exception is converting some static functions to a global function. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-20drm/amd/display: Add tags for indicating mst progress statusWayne Lin4-3/+94
[Why & How] In order to leverage igt tool to maintain mst feature, expose new debugfs entry "mst_progress_status". In our dm flow, record down the result of each phase of mst and user can examine the mst result by checking whether each phase get completed successfully. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-20drm/amd/display: Add is_mst_connector debugfs entryWayne Lin1-0/+53
[Why & How] Add "is_mst_connector" debugfs entry to help distinguish whether a connector is in a mst topology or not. Access it with the following command: cat /sys/kernel/debug/dri/0/DP-X/is_mst_connector Result: - "root" stands for the root connector of the topology - "branch" stands for branch device of the topology - "end" stands for leaf node connector of the topology - "no" stands for the connector is not a device of a mst topology Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-20drm/amd/display: fix trigger_hotplug to support mst caseWayne Lin1-3/+14
[Why & How] Correct few problems below to have debugfs trigger_hotplug entry supports mst case * Adjust the place for acquiring the hpd_lock. We'll also access dc_link when simulate unplug * When detect the connector is a mst root, call reset_cur_dp_mst_topology() to simulate unplug * Don't support hotplug caused by CSN message since we can't change mst topology info directly. We can't simulate that * Clean up redundant code Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-20drm/amd/display: Expose function reset_cur_dp_mst_topologyWayne Lin2-1/+4
[Why & How] Need to leverage this function out of dc_link.c. Change it to public. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-20drm/amd/display: Update in dmlAlvin Lee2-0/+2
Update DML to configure drr_display in vba struct. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-20drm/amd/display: Remove unused variableJun Lei1-1/+0
Remove an unused variable "remove_disconnect_edp" which was a workaround bit. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Jun Lei <Jun.Lei@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-20drm/amd/display: Support vertical interrupt 0 for all dcn ASICWayne Lin2-7/+26
[Why] When CONFIG_DRM_AMD_SECURE_DISPLAY is enabled, it will try to register vertical interrupt 0 for specific task. Currently, only dcn10 have defined relevant info for vertical interrupt 0. If we enable CONFIG_DRM_AMD_SECURE_DISPLAY for other dcn ASIC, will get DC_IRQ_SOURCE_INVALID while calling dc_interrupt_to_irq_source() and cause pointer errors. [How] Add support of vertical interrupt 0 for all dcn ASIC. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-20drm/amd/display: Change get_pipe_idx function scopeMaíra Canal2-2/+1
Turn previously global function into a static function as it is not used outside the file. Reviewed-by: André Almeida <andrealmeid@igalia.com> Signed-off-by: Maíra Canal <mairacanal@riseup.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-18drm/amd/display: Remove unnecessary NULL check in commit_planes_for_stream()Dan Carpenter1-1/+1
Smatch complains that: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:3369 commit_planes_for_stream() warn: variable dereferenced before check 'stream' (see line 3114) The 'stream' pointer cannot be NULL and the check can be removed. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-18drm/amd/display: Fix spelling mistake "supporing" -> "supporting"Colin Ian King1-1/+1
There is a spelling mistake in a dml_print message. Fix it. Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-18drm/amd/display: Enable building new display engine with KCOV enabledGuenter Roeck2-1/+4
The new display engine uses floating point math, which is not supported by KCOV. Commit 9d1d02ff3678 ("drm/amd/display: Don't build DCN1 when kcov is enabled") tried to work around the problem by disabling CONFIG_DRM_AMD_DC_DCN if KCOV_INSTRUMENT_ALL and KCOV_ENABLE_COMPARISONS are enabled. The result is that KCOV can not be enabled on systems which require this display engine. A much simpler and less invasive solution is to disable KCOV selectively when compiling the display enagine while keeping it enabled for the rest of the kernel. Fixes: 9d1d02ff3678 ("drm/amd/display: Don't build DCN1 when kcov is enabled") Cc: Arnd Bergmann <arnd@arndb.de> Cc: Leo Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-15Merge tag 'drm-fixes-2022-07-15' of git://anongit.freedesktop.org/drm/drmLinus Torvalds4-9/+111
Pull drm fixes from Dave Airlie: "This is the regular fixes pull for this week. This has a bunch of amdgpu fixes, major one reverts the buddy allocator until it can be tested more, otherwise just small ones, then i915 has a bunch of fixes. The outstanding firmware regressions reported by phoronix will hopefully be dealt with ASAP. amdgpu: - revert buddy allocator support for now - DP MST blank screen fix for specific platforms - MEC firmware check fix for GC 10.3.7 - Deep color fix for DCE - Fix possible divide by 0 - Coverage blend mode fix - Fix cursor only commit timestamps i915: - Selftest fix - TTM fix sg_table construction - Error return fixes - Fix a performance regression related to waitboost - Fix GT resets" * tag 'drm-fixes-2022-07-15' of git://anongit.freedesktop.org/drm/drm: drm/amd/display: Ensure valid event timestamp for cursor-only commits drm/amd/display: correct check of coverage blend mode drm/amd/pm: Prevent divide by zero drm/amd/display: Only use depth 36 bpp linebuffers on DCN display engines. drm/amdkfd: correct the MEC atomic support firmware checking for GC 10.3.7 drm/amd/display: Ignore First MST Sideband Message Return Error drm/i915/selftests: fix subtraction overflow bug drm/i915/gem: Look for waitboosting across the whole object prior to individual waits drm/i915/gt: Serialize TLB invalidates with GT resets drm/i915/gt: Serialize GRDOM access between multiple engine resets drm/i915/ttm: fix sg_table construction drm/i915/selftests: fix a couple IS_ERR() vs NULL tests drm/i915: Fix vm use-after-free in vma destruction drm/i915/guc: ADL-N should use the same GuC FW as ADL-S drm/i915: fix a possible refcount leak in intel_dp_add_mst_connector() drm/i915/gvt: IS_ERR() vs NULL bug in intel_gvt_update_reg_whitelist() Revert "drm/amdgpu: add drm buddy support to amdgpu"
2022-07-15drm/amd/display: Fix new dmub notification enabling in DMStylon Wang1-8/+19
[Why] Changes from "Fix for dmub outbox notification enable" need to land in DM or DMUB outbox notification would be disabled. [How] Enable outbox notification only after interrupt are enabled and IRQ handlers registered. Any pending notification will be sent by DMUB once outbox notification is enabled. Fixes: ed7208706448 ("drm/amd/display: Fix for dmub outbox notification enable") Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Stylon Wang <stylon.wang@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2022-07-15Merge tag 'amd-drm-next-5.20-2022-07-14' of https://gitlab.freedesktop.org/agd5f/linux into drm-nextDave Airlie171-1153/+20379
amd-drm-next-5.20-2022-07-14: amdgpu: - DCN3.2 updates - DC SubVP support - DP MST fixes - Audio fixes - DC code cleanup - SMU13 updates - Adjust GART size on newer APUs for S/G display - Soft reset for GFX 11 - Soft reset for SDMA 6 - Add gfxoff status query for vangogh - Improve BO domain pinning - Fix timestamps for cursor only commits - MES fixes - DCN 3.1.4 support - Misc fixes - Misc code cleanup amdkfd: - Simplify GPUVM validation - Unified memory for CWSR save/restore area - fix possible list corruption on queue failure radeon: - Fix bogus power of two warning UAPI: - Unified memory for CWSR save/restore area for KFD Proposed userspace: https://lists.freedesktop.org/archives/amd-gfx/2022-June/080952.html Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220714214716.8203-1-alexander.deucher@amd.com
2022-07-14amdgpu: disable powerpc support for the newer display engineLinus Torvalds1-1/+1
The DRM_AMD_DC_DCN display engine support (Raven, Navi, and newer) has not been building cleanly on powerpc and causes link errors due to mixing hard- and soft-float object files: powerpc64-linux-ld: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.o uses hard float, drivers/gpu/drm/amd/amdgpu/../display/dc/dcn31/dcn31_resource.o uses soft float powerpc64-linux-ld: failed to merge target specific data of file drivers/gpu/drm/amd/amdgpu/../display/dc/dcn31/dcn31_resource.o [..] and while patches are floating around, it's not exactly obvious what is going on. The problem bisects to commit 41b7a347bf14 ("powerpc: Book3S 64-bit outline-only KASAN support") but that is probably more about changing config variables than the fundamental cause. Despite the bisection result, a more directly related commit seems to be 26f4712aedbd ("drm/amd/display: move FPU related code from dcn31 to dml/dcn31 folder"). It's probably a combination of the two. This has been going on since the merge window, without any final word. So instead of blindly applying patches that may or may not be the right thing, let's disable this for now. As Michael Ellerman says: "IIUIC this code was never enabled on ppc before, so disabling it seems like a reasonable fix to get the build clean" and once we have more actual feedback (and find any potential users) we can always re-enable it with the patch that fixes the issues and back-port as necessary. Fixes: 41b7a347bf14 ("powerpc: Book3S 64-bit outline-only KASAN support") Fixes: 26f4712aedbd ("drm/amd/display: move FPU related code from dcn31 to dml/dcn31 folder") Reported-and-tested-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/all/20220606153910.GA1773067@roeck-us.net/ Link: https://lore.kernel.org/all/20220618232737.2036722-1-linux@roeck-us.net/ Link: https://lore.kernel.org/all/20220713050724.GA2471738@roeck-us.net/ Acked-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2022-07-13drm/amd/display: remove duplicate dcn314 includesAlex Deucher3-3/+0
Several headers were included twice. Fix that. Reported-by: kernel test robot <yujie.liu@intel.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: André Almeida <andrealmeid@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: Enable DCN314 in DMRoman Li2-0/+12
Add support for DCN 3.1.4 in Display Manager Signed-off-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: Add DMUB support for DCN314Roman Li1-0/+1
Initialize DMUB for DCN 3.1.4. Use same funcs as DCN31. Signed-off-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: Enable DCN314 in DCRoman Li17-15/+366
Add support for DCN 3.1.4 in Display Core Signed-off-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: Add DCN314 version identifiersRoman Li3-0/+3
DCN 3.1.4 version and family ids Signed-off-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: Add DCN314 DML calculation supportRoman Li4-0/+9267
Display mode library for DCN 3.1.4 v2: squash in checkpatch fix (Alex) Signed-off-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: Add DCN314 DC resourcesRoman Li13-0/+4693
Display Core support for DCN 3.1.4 v2:(squash)fix non-x86 in dc/dcn314/Makefile Properly handle PPC as well. (Alex) v3: minor cleanup (Alex) v4: fix comment (Alex) Signed-off-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: Add DCN314 clock managerRoman Li4-0/+1278
Clock and SMU interfaces for DCN 3.1.4 Signed-off-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: Add DCN314 IRQ servicesRoman Li2-0/+469
IRQ services to support DCN 3.1.4 interrupts. v2: make to_dal_irq_source_dcn314 static (Alex) Signed-off-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: Ensure valid event timestamp for cursor-only commitsMichel Dänzer1-3/+39
Requires enabling the vblank machinery for them. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2030 Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Michel Dänzer <mdaenzer@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: Ensure valid event timestamp for cursor-only commitsMichel Dänzer1-3/+40
Requires enabling the vblank machinery for them. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2030 Signed-off-by: Michel Dänzer <mdaenzer@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2022-07-13drm/amd/display: correct check of coverage blend modeMelissa Wen1-1/+1
Check the value of per_pixel_alpha to decide whether the Coverage pixel blend mode is applicable or not. Fixes: 76818cdd11a2 ("drm/amd/display: add Coverage blend mode for overlay plane") Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: Only use depth 36 bpp linebuffers on DCN display engines.Mario Kleiner1-5/+6
Various DCE versions had trouble with 36 bpp lb depth, requiring fixes, last time in commit 353ca0fa5630 ("drm/amd/display: Fix 10bit 4K display on CIK GPUs") for DCE-8. So far >= DCE-11.2 was considered ok, but now I found out that on DCE-11.2 it causes dithering when there shouldn't be any, so identity pixel passthrough with identity gamma LUTs doesn't work when it should. This breaks various important neuroscience applications, as reported to me by scientific users of Polaris cards under Ubuntu 22.04 with Linux 5.15, and confirmed by testing it myself on DCE-11.2. Lets only use depth 36 for DCN engines, where my testing showed that it is both necessary for high color precision output, e.g., RGBA16 fb's, and not harmful, as far as more than one year in real-world use showed. DCE engines seem to work fine for high precision output at 30 bpp, so this ("famous last words") depth 30 should hopefully fix all known problems without introducing new ones. Successfully retested on DCE-11.2 Polaris and DCN-1.0 Raven Ridge on top of Linux 5.19.0-rc2 + drm-next. Fixes: 353ca0fa5630 ("drm/amd/display: Fix 10bit 4K display on CIK GPUs") Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Tested-by: Mario Kleiner <mario.kleiner.de@gmail.com> Cc: stable@vger.kernel.org # 5.14.0 Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: Ignore First MST Sideband Message Return ErrorFangzhi Zuo3-0/+64
[why] First MST sideband message returns AUX_RET_ERROR_HPD_DISCON on certain intel platform. Aux transaction considered failure if HPD unexpected pulled low. The actual aux transaction success in such case, hence do not return error. [how] Not returning error when AUX_RET_ERROR_HPD_DISCON detected on the first sideband message. v2: squash in additional DMI entries v3: squash in static fix Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2022-07-13drm/amd/display: attempt to fix the logic in commit_planes_for_stream()Alex Deucher1-21/+24
The indentation is screwed up. I'm not sure quite how the logic should flow. Someone more familiar with this code should verify this. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: correct check of coverage blend modeMelissa Wen1-1/+1
Check the value of per_pixel_alpha to decide whether the Coverage pixel blend mode is applicable or not. Fixes: 76818cdd11a2 ("drm/amd/display: add Coverage blend mode for overlay plane") Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: Only use depth 36 bpp linebuffers on DCN display engines.Mario Kleiner1-5/+6
Various DCE versions had trouble with 36 bpp lb depth, requiring fixes, last time in commit 353ca0fa5630 ("drm/amd/display: Fix 10bit 4K display on CIK GPUs") for DCE-8. So far >= DCE-11.2 was considered ok, but now I found out that on DCE-11.2 it causes dithering when there shouldn't be any, so identity pixel passthrough with identity gamma LUTs doesn't work when it should. This breaks various important neuroscience applications, as reported to me by scientific users of Polaris cards under Ubuntu 22.04 with Linux 5.15, and confirmed by testing it myself on DCE-11.2. Lets only use depth 36 for DCN engines, where my testing showed that it is both necessary for high color precision output, e.g., RGBA16 fb's, and not harmful, as far as more than one year in real-world use showed. DCE engines seem to work fine for high precision output at 30 bpp, so this ("famous last words") depth 30 should hopefully fix all known problems without introducing new ones. Successfully retested on DCE-11.2 Polaris and DCN-1.0 Raven Ridge on top of Linux 5.19.0-rc2 + drm-next. Fixes: 353ca0fa5630 ("drm/amd/display: Fix 10bit 4K display on CIK GPUs") Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Tested-by: Mario Kleiner <mario.kleiner.de@gmail.com> Cc: stable@vger.kernel.org # 5.14.0 Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: make some dc_dmub_srv functions staticAlex Deucher1-2/+2
Not used outside of dc_dmub_srv.c. Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: André Almeida <andrealmeid@igalia.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: 3.2.194Aric Cyr1-1/+1
This version brings along following fixes: - Fixes for MST, MPO, PSRSU, DP 2.0, Freesync and others - Add register offsets of NBI and DCN. - Improvement of ALPM - Removing assert statement for Linux DM - Re-implementing ARGB16161616 pixel format Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: Fix lag when moving windowed MPO across display using ODM 2:1 combineSamson Tam2-2/+57
[Why] With single display odm 2:1 policy, when moving windowed MPO across the display, we experience a momentary lag when we move between the centre of the display and the right half of the display. This is caused by the MPO pipe being reallocated when it crosses this boundary [How] Handle two cases: 1. if the head pipe has a MPO pipe already allocated in the old context, then use that pipe if it is available in the current context 2. if the head pipe is on the left side, check the right side to see if it has a MPO pipe already allocated. If so, don't use that pipe if it is selected as the idle pipe in the current context Add new function pointer called .acquire_idle_pipe_for_head_pipe that will pass in the head pipe and handle case 1 Add find_idle_secondary_pipe_check_mpo() to handle case 2 if we don't hit case 1. In dc_add_plane_to_context(), start with head pipe and check case 1 and 2 in call acquire_free_pipe_for_head(). If we are on the right side of the display, check case 1 again by passing in right side pipe as the new head in call acquire_free_pipe_for_head(). Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Ariel Bernstein <Eric.Bernstein@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Samson Tam <Samson.Tam@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: Add NBIO reg offsets to DCAurabindo Pillai4-0/+6
[Why&How] Add a field to store the NBIO IP offset for use with runtime offset calculation Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: Add DCN reg offsets to DCHarry Wentland4-1/+16
[Why&How] Add a field to store the DCN IP offset for use with runtime offset calculation This offset is indexed using reg*_BASE_IDX for the corresponding group of registers. For example, address of DIG_BE_CNTL instance 0 is calculated like: dcn_reg_offsets[regDIG0_DIG_BE_CNTL_BASE_IDX] + regDIG0_DIG_BE_CNTL. {dcn,nbio}_reg_offsets are used only for the ASICs for which runtime initializaion of offsets are enabled through the modified SR* macros that contain an additional REG_STRUCT element in the macro definition. DCN3.5+ will fail dc_create() if {dcn,nbio}_reg_offsets are null. They are applicable starting with DCN32/321 and are not used for ASICs upstreamed before them. ASICs before DCN32/321 will not contain any computation that involves {dcn,nbio}_reg_offsets. For them, the address/offset computation is done during compile time. This is evident from the BASE_INNER definition for compile time vs run time initialization: Compile time init: #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg Run time init: #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] BASE_INNER macro is local to each dcnxx_resource.c and hence different ASICs can have either runtime or compile time initialization of offsets. The computation of offset is done for registers all at once during driver load and hence it does not introduce any performance overhead during normal operation. Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: add system info table logCharlene Liu1-0/+30
[why] insert log for debug use. v2: squash in fix (Alex) Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: Grab dc_lock before detecting linkWayne Lin2-33/+63
[Why & How] There is chance we change dc state while calling dc_link_detect(). As the result of that, grab the dm.dc_lock before detecting link. Reviewed-by: Hersen Wu <hersen.wu@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: Re-implementing ARGB16161616 pixel format as 22Ethan Wellenreiter5-0/+12
[Why] ABGR16161616 colour format was added to dcn10/20/30, and set any ARGB16161616 to the same value as it (26). As such, the HDR10 Green Point y value was too far off of the EDID stated value for DisplayPort. [How] Added back the pixel format as 22 for ARGB16161616 for dcn10/20/30. Reviewed-by: Reza Amini <reza.amini@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Ethan Wellenreiter <Ethan.Wellenreiter@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: 3.2.193Aric Cyr1-1/+1
Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: update DML1 logic for unbounded req handlingJun Lei2-0/+18
[why] Unbounded request logic in resource/DML has some issues where unbounded request is being enabled incorrectly. SW today enables unbounded request unconditionally in hardware, on the assumption that HW can always support it in single pipe scenarios. This worked until now because the same assumption is made in DML. A new DML update is needed to fix a bug, where there are single pipe scenarios where unbounded cannot be enabled, and this change in DML needs to be ported in, and dcn32 resource logic fixed. [how] First, dcn32_resource should program unbounded req in HW according to unbounded req enablement output from DML, as opposed to DML input Second, port in DML1 update which disables unbounded req in some scenarios to fix an issue with poor stutter performance Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Jun Lei <jun.lei@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: Reduce SCDC Status Flags DefinitionChris Park1-5/+2
[Why] Status flags definition is reduced to read less bytes in SCDC transaction for status update. [How] Reduce definition of reserved bytes from 3 to 1 for status update. Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Chris Park <chris.park@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: make enable link independent from verified link capsWenjing Liu7-53/+44
[why] Ideally link capability should be independent from the link configuration that we decide to use in enable link. Otherwise if link capability is changed after validation has completed, we could end up enabling a link configuration with invalid configuration. This would lead to over link bandwidth subscription or in the extreme case causes us to enable HPO link to a DIO stream. [how] Add a new struct in pipe ctx called link config. This structure will contain link configuration to enable a link. It will be populated during map pool resources after we validate link bandwidth. Remove the reference of verified link cap during enable link process and use link config in pipe ctx instead. Reviewed-by: George Shen <George.Shen@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-13drm/amd/display: Ignore First MST Sideband Message Return ErrorFangzhi Zuo3-0/+64
[why] First MST sideband message returns AUX_RET_ERROR_HPD_DISCON on certain intel platform. Aux transaction considered failure if HPD unexpected pulled low. The actual aux transaction success in such case, hence do not return error. [how] Not returning error when AUX_RET_ERROR_HPD_DISCON detected on the first sideband message. v2: squash in additional DMI entries v3: squash in static fix Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-12drm/amd/display: fix unnecessary pipe split playing NV12 1080p MPO videoSamson Tam1-28/+3
[Why] When playing NV12 1080p MPO video, it is pipe splitting so we see two pipes in fullscreen and four pipes in windowed mode. Pipe split is happening because we are setting MaximumMPCCombine = 1 [How] Algorithm for MaximumMPCCombine has extra conditions we do not need. Use DCN31 algorithm instead Signed-off-by: Samson Tam <Samson.Tam@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-12drm/amd/display: Fix black screen when disabling Freesync in OSDIlya Bakoulin1-0/+10
[Why] Black screen encountered when disabling Freesync through OSD on some displays. [How] Set the should_disable flag when new top pipe has no plane state to ensure that pipes get cleaned up. Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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