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2018-09-14drm/amd/display: Add DMCU firmware versionDavid Francis2-0/+3
Read the version number from the common firmware header and store it in the dm struct Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-14drm/amd/display: Add DC config flag for Raven2 (v2)Bhawanpreet Lakha1-0/+6
Add DRM_AMD_DC_DCN1_01 config flag for Raven2 v2: Make DC select DRM_AMD_DC_DCN1_01 (Alex) Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-14drm/amd/display: Add Raven2 definitions in dcBhawanpreet Lakha9-1/+78
Add Raven2 definitions in the dc code Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-14drm/amd/display/dm: add picasso supportLikun Gao1-2/+6
Add support for picasso to the display manager. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-13drm/amd/display: Fix pflip IRQ status after gpu reset.Andrey Grodzovsky1-0/+1
Problem: After GPU reset pflip completion IRQ is disabled and hence any subsequent mode set or plane update leads to hang. Fix: Unless acrtc->otg_inst is initialized to -1 during display block initializtion then durng resume from GPU reset amdgpu_irq_gpu_reset_resume_helper will override CRTC 0 pflip IRQ value with whatever value was on every other unused CRTC because dm_irq_state will do irq_source = dal_irq_type + acrtc->otg_inst where acrtc->otg_inst will be 0 for every unused CRTC. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-12drm/amd/display: fix ptr_ret.cocci warningskbuild test robot1-4/+1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:771:1-3: WARNING: PTR_ERR_OR_ZERO can be used Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR Generated by: scripts/coccinelle/api/ptr_ret.cocci Fixes: e498eb713604 ("drm/amd/display: Add support for hw_state logging via debugfs") CC: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-12drm/amd: Add DM DMCU supportDavid Francis2-1/+92
DMCU (Display Microcontroller Unit) is a GPU chip involved in eDP features like Adaptive Backlight Modulation and Panel Self Refresh. DC is already fully equipped to initialize DMCU as long as the firmware is loaded. At the moment only the raven firmware is available. A single .bin file is loaded by the kernel's loading mechanism and split into two ucodes according to the header. DMCU is optional, so if the firmware is not found, no error or warning is raised. Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-10drm/amd/display: Add invariant support instrumentation in driverJun Lei3-27/+61
Existing debug dump are all invariant, new “low 32-bit of address” dump is not invariant Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-10drm/amd/display: clean code for transition event log.Chiawen Huang3-29/+0
[Why] There are same purpose transition events. [How] remove the redundant event log. Signed-off-by: Chiawen Huang <chiawen.huang@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-10drm/amd/display: Remove call to amdgpu_pm_compute_clocksDavid Francis1-8/+0
[Why] The extraneous call to amdgpu_pm_compute_clocks is deprecated. [How] Remove it. Signed-off-by: David Francis <David.Francis@amd.com> Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-10drm/amd/display: use link type to decide stream enc acquisitionEric Yang1-1/+1
[Why] Virtual sink is used when set mode happens on a disconnected display to allow the mode set to proceed. This did not work with MST because the logic for acquiring stream encoder uses stream signal to determine the special handling is required, and stream signal is virtual instead of DP in this case. [How] Use link type to decide instead. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-10drm/amd/display: dc 3.1.65Tony Cheng1-1/+1
Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Steven Chiu <Steven.Chiu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-10drm/amd/display: Reorder resource_pool to put i2c with auxDavid Francis1-1/+1
[Why] The i2c and aux engines are similar, and should be placed next to eachother for readability [How] Reorder the elements of the resource_pool struct Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-10drm/amd/display: Use DRM helper for best_encoderLeo Li1-23/+1
[Why] Our implementation is functionally identical to DRM's Note that instead of checking if the provided id is 0, the helper follows through with the mode object search. However, It will still return NULL, since 0 is not a valid object id, and missed searches will return NULL. [How] Remove our implementation, and replace it with drm_atomic_helper_best_encoder. Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-10drm/amd/display: num of sw i2c/aux engines less than num of connectorsHersen Wu7-5/+52
[why] AMD Stoney reference board, there are only 2 pipes (not include underlay), and 3 connectors. resource creation, only 2 I2C/AUX engines are created. Within dc_link_aux_transfer, when pin_data_en =2, refer to enengines[ddc_pin->pin_data->en] = NULL. NULL point is referred later causing system crash. [how] each asic design has fixed number of ddc engines at hw side. for each ddc engine, create its i2x/aux engine at sw side. Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-10drm/amd/display: add aux transition event log.Chiawen Huang4-1/+76
[Why] Enhance aux transition debugging information. [How] Added Aux request and reply event log. Signed-off-by: Chiawen Huang <chiawen.huang@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-10drm/amd/display: add disconnect_delay to dc_panel_patchDerek Lai1-0/+1
Some display need disconnect delay. Adding this parameter for future use Signed-off-by: Derek Lai <Derek.Lai@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-10drm/amd/display: remove unused clk_src codeDmytro Laktyushkin2-90/+1
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-10drm/amd/display: remove dead dc vbios codeDmytro Laktyushkin3-1514/+39
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-10drm/amd/display: Add driver-side parsing for CMJun Lei1-4/+25
Although 4 unique register values exist for gamma modes, two are actually the same (the two RAMs) It’s not possible for caller to understand this HW specific behavior, so some parsing is necessary in driver Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-10drm/amd/display: Fix DAL217 tests modify DTN logs for other testsGary Kattan1-6/+8
[Why]Update Code to get DTN golden log check to pass for tests run after DAL217 tests. [How]Change how dcn10_log_hw_state function prints HW state info (CM_GAMUT_REMAP_Cx_Cx registers) when GAMUT REMAP is in bypass mode. Signed-off-by: Gary Kattan <gary.kattan@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-10drm/amd/display: Add DP YCbCr 4:2:0 supportEric Bernstein1-1/+188
[Why] For supporting DP YCbCr 4:2:0 output. [How] Update mod_build_vsc_infopacket to support Pixel Encoding/Colorimetry Format indication for VSC SDP rev5. Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-10drm/amd/display: Build stream update and plane updates in dmBhawanpreet Lakha1-1/+115
[Why] We currently lock modeset by setting a boolean in dm. We want to lock Based on what DC tells us. [How] Build stream_updates and plane_update based on what changed. Then we call check_update_surfaces_for_stream() to get the update type We lock only if update_type is not fast Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-10drm/amd/display: dc 3.1.64Tony Cheng1-1/+1
Signed-off-by: Tony Cheng <tony.cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-09-07Merge tag 'drm-misc-next-2018-09-05' of git://anongit.freedesktop.org/drm/drm-misc into drm-nextDave Airlie4-6/+33
drm-misc-next for 4.20: UAPI Changes: - Add userspace dma-buf device to turn memfd regions into dma-bufs (Gerd) - Add per-plane blend mode property (Lowry) - Change in drm_fourcc.h is documentation only (Brian) Cross-subsystem Changes: - None Core Changes: - Remove user logspam and useless lock in vma_offset_mgr destroy (Chris) - Add get/verify_crc_source for improved crc source selection (Mahesh) - Add __drm_atomic_helper_plane_reset to reduce copypasta (Alexandru) Driver Changes: - various: Replance ref/unref calls with drm_dev_get/put (Thomas) - bridge: Add driver for TI SN65DSI86 chip (Sandeep) - rockchip: Add PX30 support (Sandy) - sun4i: Add support for R40 TCON (Jernej) - vkms: Continued building out vkms, added gem support (Haneen)Driver Changes: - various: fbdev: Wrap remove_conflicting_framebuffers with resource_len accessors to remove a bunch of cargo-cult (Michał) - rockchip: Add rgb output iface support + fixes (Sandy/Heiko) - nouveau/amdgpu: Add cec-over-aux support (Hans) - sun4i: Add support for Allwinner A64 (Jagan) Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michał Mirosław <mirq-linux@rere.qmqm.pl> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Sandy Huang <hjc@rock-chips.com> Cc: Hans Verkuil <hans.verkuil@cisco.com> Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Dave Airlie <airlied@redhat.com> From: Sean Paul <sean@poorly.run> Link: https://patchwork.freedesktop.org/patch/msgid/20180905202210.GA95199@art_vandelay
2018-08-31drm/amdgpu: add DisplayPort CEC-Tunneling-over-AUX supportHans Verkuil2-1/+10
Add DisplayPort CEC-Tunneling-over-AUX support to amdgpu. Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/de9586bb-151e-bae9-b8e3-14db107a60df@xs4all.nl
2018-08-27drm/amd/display: Flatten unnecessary i2c functionsDavid Francis1-77/+34
[Why] The dce_i2c_hw code contained four funtcions that were only called in one place and did not have a clearly delineated purpose. [How] Inline these functions, keeping the same functionality. This is not a functional change. The functions disable_i2c_hw_engine and release_engine_dce_hw were pulled into their respective callers. The most interesting part of this change is the acquire functions. dce_i2c_hw_engine_acquire_engine was pulled into dce_i2c_engine_acquire_hw, and dce_i2c_engine_acquire_hw was pulled into acquire_i2c_hw_engine. Some notes to show that this change is not functional: -Failure conditions in any function resulted in a cascade of calls that ended in a 'return NULL'. Those are replaced with a direct 'return NULL'. -The variable result is the one from dce_i2c_hw_engine_acquire_engine. The boolean result used as part of return logic was removed. -As the second half of dce_i2c_hw_engine_acquire_engine is only executed if that function is returning true and therefore exiting the do-while loop in dce_i2c_engine_acquire_hw, those lines were moved outside of the loop. Signed-off-by: David Francis <David.Francis@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/display: support 48 MHZ refclk offEric Yang1-3/+33
[Why] On PCO and up, whenever SMU receive message to indicate active display count = 0. SMU will turn off 48MHZ TMDP reference clock by writing to 1 TMDP_48M_Refclk_Driver_PWDN. Once this clock is off, no PHY register will respond to register access. This means our current sequence of notifying display count along with requesting clock will cause driver to hang when accessing PHY registers after displays count goes to 0. [How] Separate the PPSMC_MSG_SetDisplayCount message from the SMU messages that request clocks, have display own sequencing of this message so that we can send it at the appropriate time. Do not redundantly power off HW when entering S3, S4, since display should already be called to disable all streams. And ASIC soon be powered down. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/display: Remove redundant i2c structsDavid Francis4-177/+28
[Why] The i2c code contains two structs that contain the same information as i2c_payload [How] Replace references to those structs with references to i2c_payload dce_i2c_transaction_request->status was written to but never read, so all references to it are removed Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Jordan Lazare <Jordan.Lazare@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/display: Support reading hw state from debugfs fileNicholas Kazlauskas7-29/+140
[Why] Logging hardware state can be done by triggering a write to the debugfs file. It would also be useful to be able to read the hardware state from the debugfs file to be able to generate a clean log without timestamps. [How] Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log Threading is an obvious concern when dealing with multiple debugfs operations and blocking on global state in dm or dc seems unfavorable. Adding an extra parameter for the debugfs log context state is the implementation done here. Existing code that made use of DTN_INFO and its associated macros needed to be refactored to support this. We don't know the size of the log in advance so it reallocates the log string dynamically. Once the log has been generated it's copied into the user supplied buffer for the debugfs. This allows for seeking support but it's worth nothing that unlike triggering output via dmesg the hardware state might change in-between reads if your buffer size is too small. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Jordan Lazare <Jordan.Lazare@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/display: Improve spelling, grammar, and formatting of amdgpu_dm.c commentsDavid Francis1-80/+109
[Why] Good spelling and grammar makes comments more pleasant and clearer. Linux has coding standards for comments that we should try to follow. [How] Fix obvious spelling and grammar issues Ensure all comments use '/*' and '*/' and multi-line comments follow linux convention Remove line-of-stars comments that do not separate sections of code and comments referring to lines of code that have since been removed Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/display: Fix memory leak caused by missed dc_sink_releaseSivapiriyanKumarasamy1-1/+5
[Why] There is currently an intermittent hang from a memory leak in DTN stress testing. It is caused by unfreed memory during driver disable. [How] Do a dc_sink_release in the case that skips it incorrectly. Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/display: eliminate long wait between register polls on MaximusKen Chalmers1-7/+2
[Why] Now that we "scale" time delays correctly on Maximus (as of diags svn r170115), the forced "35 ms" wait time now becomes 35 ms * 500 = 17.5 seconds, which is far too long. Even having to repeat polling a register once causes excessive delays on Maximus. [How] Just use the regular wait time passed to the generic_reg_wait() function. This is sufficient for Maximus now, and it also means that there's one less "Maximus-only" code path in DAL. Also disable the "REG_WAIT taking a while:" message on Maximus, since things do take a while longer there and 1-2ms delays are not uncommon (and nothing to worry about). Signed-off-by: Ken Chalmers <ken.chalmers@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/display: Add support for hw_state logging via debugfsNicholas Kazlauskas4-4/+77
[Why] We have logging methods for printing hardware state for newer ASICs but no way to trigger the log output. [How] Add support for triggering the output via writing to a debugfs file entry. Log output currently goes into dmesg for convenience, but accessing via a read should be possible later. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Jordan Lazare <Jordan.Lazare@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/display: Use non-deprecated vblank handlerLeo (Sunpeng) Li1-6/+4
[Why] drm_handle_vblank is deprecated. Use drm_crtc_handle_vblank instead. Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/display: dc 3.1.63Tony Cheng1-1/+1
Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Steven Chiu <Steven.Chiu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/display: Eliminate i2c hw function pointersDavid Francis2-345/+291
[Why] The function pointers of the dce_i2c_hw struct were never accessed from outside dce_i2c_hw.c and had only one version. As function pointers take up space and make debugging difficult, and they are not needed in this case, they should be removed. [How] Remove the dce_i2c_hw_funcs struct and make static all functions that were previously a part of it. Reorder the functions in dce_i2c_hw.c. Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/display: Fix memory leak caused by missed dc_sink_releaseSivapiriyanKumarasamy1-1/+5
[Why] There is currently an intermittent hang from a memory leak in DTN stress testing. It is caused by unfreed memory during driver disable. [How] Do a dc_sink_release in the case that skips it incorrectly. Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amdgpu/display: add support for LVDS (v5)Alex Deucher10-0/+135
This adds support for LVDS displays. v2: add support for spread spectrum, sink detect v3: clean up enable_lvds_output v4: fix up link_detect v5: remove assert on 888 format Bug: https://bugs.freedesktop.org/show_bug.cgi?id=105880 Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/display: indent an if statementDan Carpenter1-1/+1
The if statement isn't indented and it makes static checkers complain. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/display: fix a compile warningWen Yang1-1/+1
Fix comile warning like, CC [M] drivers/gpu/drm/i915/gvt/execlist.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.o CC [M] drivers/gpu/drm/radeon/btc_dpm.o CC [M] drivers/isdn/hisax/avm_a1p.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_dpp.o drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c: In function ‘dcn10_update_mpcc’: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:1903:9: warning: missing braces around initializer [-Wmissing-braces] struct mpcc_blnd_cfg blnd_cfg = {0}; ^ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:1903:9: warning: (near initialization for ‘blnd_cfg.black_color’) [-Wmissing-braces] Acked-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Wen Yang <wen.yang99@zte.com.cn> Reviewed-by: Jiang Biao <jiang.biao2@zte.com.cn> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/display: implement DPMS DTN test v2Jun Lei5-2/+518
[why] Existing DTN infrastructure in driver is hacky. It uses implicit log names, and also incorrect escape ID. [how] - Implement using generic DTN escape ID. - Move file logging functionality from driver to to script; driver now outputs to string/buffer - Move HWSS debug functionality to separate c file - Add debug functionalty for per-block logging as CSV - Add pretty print in python Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/display: move edp fast boot optimization flag to streamAnthony Koo4-14/+21
[Why] During S4/S3 stress test it is possible to resume from S4 without calling mode set on eDP, meaning high level optimization flag is not reset. If this is followed by an S3 resume call, driver will see optimization flag is set and consume it and think backend is powered on when in fact it is not. This results in PHY being off in sequence where S4->Resume->S3->Resume->ApplyOpt->black screen. [How] Move optimization flag to stream instead of a DC flag. Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/display: Combine dce80 and dce100 i2c hw functionsDavid Francis1-197/+40
[Why] There are two versions of the hw function pointers: one for dce80 and one for all other versions. These paired functions are nearly identical. dce80 and dce100 should not require different i2c access functions. [How] Combine each pair of functions into a single function. Mostly the new functions are based on the dce100 versions as those versions are newer, support more features, and were more maintained. Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/display: Define registers for dcn10Nikola Cornij1-0/+2
Define register for dcn10 for future changes Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/display: Program csc matrix as part of stream updateSivapiriyanKumarasamy2-0/+28
Add csc_transform struct to dc_stream_update, and program if set when updating streams Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/display: Create new i2c resourceDavid Francis18-30/+2452
[Why] I2C code did not match dc resource model and was generally unpleasant [How] Move code into new svelte dce_i2c files, replacing various i2c objects with two structs: dce_i2c_sw and dce_i2c_hw. Fully split sw and hw code paths. Remove all redundant declarations. Use address lists to distinguish between versions. Change dce80 code to newer register access macros. Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/display: Program gamut remap as part of stream updateSivapiriyanKumarasamy2-0/+28
Add gamut remap to dc_stream_update struct, and program if set when updating streams. Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/display: HDR dynamic meta should be treated as stream updateKrunoslav Kovac1-1/+1
[Why] Recently we fixed HDR static meta using AFMT registers to be treated as fast stream update. Dynamic meta is still being treated as (full) surface update because it touches HUBP and it travels with pipe data. Here we change it to be (fast) stream update. Note, originally we also wanted to redesign here a bit, but without OS level support for true dynamic meta, it's left the same. We are simply using HW that can do dynamic meta to send HDR static meta, I still prefer keeping it in one static meta type then defining dynamic meta types to hold the same info. Once we know how OS interfaces look like, we can do proper design. [How] Move dyn meta update from update_hubp_dpp to commit_planes_do_stream_update Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amd/display: Handle HDR meta update as fast updateKrunoslav Kovac1-7/+7
[Why] Vesa DPMS tool sends different HDR meta in OS flips without changing output parameters. We don't properly update HDR info frame: - we label HDR meta update as fast update - when updating HW info frame, we only do it if full update [How] It should still be fast update, so when doing HW infoframe update, do it always no matter the update type. Also, don't request passive flip for HDR meta update only without output transfer function or color space changed. Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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