aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd/display (follow)
AgeCommit message (Collapse)AuthorFilesLines
2022-07-05drm/amd/display: guard for virtual calling destroy_link_encodersMartin Leung1-2/+8
[Why]: On power down, virtual dal may try to delete link_encoders by referencing uninitialized res_pool. [How]: Added guard against empty res_pool. Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Martin Leung <martin.leung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-05drm/amd/display: disable timing sync b/w odm halvesDmytro Laktyushkin1-1/+3
Fix for a bug where we would try to timing sync 2 odm halves. Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-05drm/amd/display: Add minimal pipe split transition stateRodrigo Siqueira2-0/+295
[WHY?] When adding/removing a plane to some configurations, unsupported pipe programming can occur when moving to a new plane. Such cases include pipe split on multi-display, with MPO, and/or ODM. [HOW?] Add a safe transistion state that minimizes pipe usage before programming new configuration. When adding a plane, the current state has the least pipes required so it is applied without splitting. This must be applied prior to updating the plane_state for seamless transition. When removing a plane, the new state has the least pieps required so it is applied without splitting. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-05drm/amd/display: Add SubVP control lockRodrigo Siqueira1-4/+8
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-05drm/amd/display: Fix stream->link_enc unassigned during stream removalNicholas Kazlauskas1-3/+0
[Why] Found when running igt@kms_atomic. Userspace attempts to do a TEST_COMMIT when 0 streams which calls dc_remove_stream_from_ctx. This in turn calls link_enc_unassign which ends up modifying stream->link = NULL directly, causing the global link_enc to be removed preventing further link activity and future link validation from passing. [How] We take care of link_enc unassignment at the start of link_enc_cfg_link_encs_assign so this call is no longer necessary. Fixes global state from being modified while unlocked. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-05drm/amd/display: Add basic infrastructure for enabling FAMSRodrigo Siqueira10-8/+328
We want to enable Firmware Assisted Memory (FAMS) Switching, but first, we need to add the required code infrastructure in DC before allowing it in amdgpu_dm. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-05drm/amd/display: Make OPTC3 function accessible to other DCNAlvin Lee4-2/+8
[Why] Newer DCN should use optc3 [How] Declare optc3 vmin/vmax function in header. Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-05drm/amd/display: Update gpuvm_max_page_table_levels IP paramEric Bernstein2-2/+2
After some experimental tests, we noticed that we need to set gpuvm_max_page_table_levels to '4' to meet the hardware requirements. Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-05drm/amd/display: Switch to correct DTO on HDMIChris Park2-0/+6
[Why] For Pixel Rate control, when on HDMI, HDMI DTO should be selected instead of DP DTO. [How] Pass HDMI parameter for HDMI stream, and select correct DTO. Signed-off-by: Chris Park <chris.park@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-05drm/amd/display: Change DET policy for MPO casesAlvin Lee2-14/+22
For MPO we want to allocate less than maximum DET for MPO pipes because we need enogh buffer to move DET back to other pipes when removing an MPO plane. Also update regular DET allocation to use DET override (DCN32 has an internal policy which driver does not want to use) Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-05drm/amd/display: Use two pixel per container for k1/k2 divRodrigo Siqueira1-4/+4
Currently, we check if pixel_encoding is equal to PIXEL_ENCODING_YCBCR422 to get the k1/k2 div parameters. This commit changes this logic slightly by checking if two pixels per container are used. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-05drm/amd/display: Apply ODM 2:1 policy for single display configurationSamson Tam10-7/+83
[Why] Most of the time, a single display uses the ODM combine. When using multi-display, we use ODM combine only if it is necessary. These cases are not flexible enough for us, and we can improve them to take advantage of our hardware. We want to have more control over the ODM policy. [How] This commit add a new debug flag named enable_single_display_2to1_odm_policy to control the ODM policy and another flag named enable_dp_dig_pixel_rate_div_policy to fine control the ODM combine. This is possible by adding a new "pipe.dest" parameter that can be set to ODM 2:1 combined if we use a single display. For dynamic ODM combine, when using DP-DIG, DCN applies K2=2 settings for ODM combine. Note that this feature affects the following registers: - timing.pix_clk_100khz -> DP_VID_M, DP_VID_N - requested_pix_clk_100hz -> DP_DTOn_PHASE - OTGn_PIXEL_RATE_DIVK2 - DP_PIXEL_PER_CYCLE_PROCESSING_MODE - DIG_FIFO_OUTPUT_PIXEL_MODE - DP_VID_N_MUL Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Samson Tam <Samson.Tam@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-05drm/amd/display: Add function to set pixels per cycleEric Bernstein8-5/+27
Add function to set pixels per cycle in DIG stream encoder Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-05drm/amd/display: Prepare for new interfacesMartin Leung8-28/+564
[WHY]: Lut pipeline will be hooked up differently in some asics need to add new interfaces and missing registers. [HOW]: Add missing registers and hook up programming from DPP for pre-blend lut. Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Martin Leung <Martin.Leung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-05drm/amd/display: Add SubVP required codeAlvin Lee20-67/+1185
This commit enables the SubVP feature. To achieve that, we need to: - Don't force p-state disallow on SubVP (can't block dummy p-state) - Send calculated watermark to DMCUB for SubVP - Adjust CAB mode message to PMFW - Add a proper locking sequence for SubVP - Various fixes to SubVP static analysis and determining SubVP config - Currently SubVP not supported with pipe split so merge all pipes before setting up SubVp Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-05drm/amd: Add debug mask for subviewport mclk switchAurabindo Pillai1-0/+3
[Why&How] Expose a new dc debug mask enum to force a subviewport memory clock switch to facilitate easy testing. Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-30drm/amdgpu/display: add missing FP_START/END checks dcn32_clk_mgr.cAlex Deucher1-0/+4
Properly handle FP code in dcn32_clk_mgr.c. Fixes: 265280b99822 ("drm/amd/display: add CLKMGR changes for DCN32/321") Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-30drm/amd/display: Fix __nedf2 undefined for 32 bit compilationRodrigo Siqueira1-4/+7
When we tried to compile DCN32/321 for 32-bit architecture, we got this error message: ERROR: modpost: "__nedf2" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! This commit fixes this issue by rewriting a small part of the dcn32_build_wm_range_table. Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Randy Dunlap <rdunlap@infradead.org> Fixes: 265280b99822 ("drm/amd/display: add CLKMGR changes for DCN32/321") Acked-by: Randy Dunlap <rdunlap@infradead.org> Tested-by: Randy Dunlap <rdunlap@infradead.org> # build-tested Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-30drm/amd/display: Fix __muldf3 undefined for 32 bit compilationRodrigo Siqueira1-2/+2
Sometimes when trying to enable some feature, we have to define some values with educated guesses, but we mark those values as TBD, which means "To Be Determined". However, the correct way to approach it is by loading that information from the firmware. Anyway, some of the values that we were experimenting with caused this issue: ERROR: modpost: "__muldf3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! This commit fixes this issue by removing the division by two since it is harmless in this case. Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Randy Dunlap <rdunlap@infradead.org> Fixes: 265280b99822 ("drm/amd/display: add CLKMGR changes for DCN32/321") Acked-by: Randy Dunlap <rdunlap@infradead.org> Tested-by: Randy Dunlap <rdunlap@infradead.org> # build-tested Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-30drm/amd/display: Fix __floatunsidf undefined for 32 bit compilationRodrigo Siqueira1-1/+1
When we tried to compile DCN32/321 for 32-bit architecture, we got this error message: ERROR: modpost: "__floatunsidf" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! This was caused because we were trying to assign an unsigned int to a double value which causes issues for 32-bit architecture. This issue can be fixed by changing the value type. Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Randy Dunlap <rdunlap@infradead.org> Fixes: 265280b99822 ("drm/amd/display: add CLKMGR changes for DCN32/321") Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Acked-by: Randy Dunlap <rdunlap@infradead.org> Tested-by: Randy Dunlap <rdunlap@infradead.org> # build-tested Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-30drm/amd/display: Fix __umoddi3 undefined for 32 bit compilationRodrigo Siqueira1-1/+3
While we tried to build amdgpu on i386, we got this error: ERROR: modpost: "__umoddi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! This commit fixes this issue by replacing the standard module operator with div_u64_rem. Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Randy Dunlap <rdunlap@infradead.org> Fixes: d3dfceb58de5 ("drm/amd/display: Add dependant changes for DCN32/321") Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Acked-by: Randy Dunlap <rdunlap@infradead.org> Tested-by: Randy Dunlap <rdunlap@infradead.org> # build-tested Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-29drm/amd/display: Re-org and cleanup the redundant codeChandan Vurdigere Nataraj1-9/+7
[Why] Redundant if-else cases for repeater and non-repeater checks [How] Without changing the core logic, rearranged the code by removing redundant checks Signed-off-by: Chandan Vurdigere Nataraj <chandan.vurdigerenataraj@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-29drm/amd/display: expose additional modifier for DCN32/321Aurabindo Pillai1-31/+35
[Why&How] Some userspace expect a backwards compatible modifier on DCN32/321. For hardware with num_pipes more than 16, we expose the most efficient modifier first. As a fall back method, we need to expose slightly inefficient modifier AMD_FMT_MOD_TILE_GFX9_64K_R_X after the best option. Also set the number of packers to fixed value as required per hardware documentation. This value is cached during hardware initialization and can be read through the base driver. Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-29drm/amdgpu/amdgpu_dm: fix kernel-doc markupsMauro Carvalho Chehab1-0/+7
There are 4 undocumented fields at struct amdgpu_display_manager. Add documentation for them, fixing those warnings: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:544: warning: Function parameter or member 'dmub_outbox_params' not described in 'amdgpu_display_manager' drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:544: warning: Function parameter or member 'num_of_edps' not described in 'amdgpu_display_manager' drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:544: warning: Function parameter or member 'disable_hpd_irq' not described in 'amdgpu_display_manager' drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:544: warning: Function parameter or member 'dmub_aux_transfer_done' not described in 'amdgpu_display_manager' drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:544: warning: Function parameter or member 'delayed_hpd_wq' not described in 'amdgpu_display_manager' Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-29drm/amd/display: change to_dal_irq_source_dnc32() storage class specifier to staticTom Rix1-1/+1
sparse reports drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn32/irq_service_dcn32.c:39:20: warning: symbol 'to_dal_irq_source_dcn32' was not declared. Should it be static? to_dal_irq_source_dnc32() is only referenced in irq_service_dnc32.c, so change its storage class specifier to static. Fixes: 0efd4374f6b4 ("drm/amd/display: add dcn32 IRQ changes") Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Tom Rix <trix@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-29drm/amd/display: Remove unused globals FORCE_RATE and FORCE_LANE_COUNTTom Rix1-3/+0
sparse reports drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:3885:6: warning: symbol 'FORCE_RATE' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:3886:10: warning: symbol 'FORCE_LANE_COUNT' was not declared. Should it be static? Neither of thse variables is used in dc_link_dp.c. Reviewing the commit listed in the fixes tag shows neither was used in the original patch. So remove them. Fixes: 265280b99822 ("drm/amd/display: add CLKMGR changes for DCN32/321") Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Tom Rix <trix@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-29drm/amdgpu/display: drop set but unused variableAlex Deucher1-2/+0
No longer used so drop it. Fixes: ec457f837890 ("drm/amd/display: Drop unnecessary detect link code") Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-29drm/amd/display: Removed unused variable retSouptick Joarder (HPE)1-2/+1
Kernel test robot throws below warning -> drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c: In function 'dc_link_reduce_mst_payload': drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c:3782:32: warning: variable 'ret' set but not used [-Wunused-but-set-variable] 3782 | enum act_return_status ret; Removed the unused ret variable. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Souptick Joarder (HPE) <jrdr.linux@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-29Revert "drm/amdgpu/display: set vblank_disable_immediate for DC"Alex Deucher1-3/+0
This reverts commit 92020e81ddbeac351ea4a19bcf01743f32b9c800. This causes stuttering and timeouts with DMCUB for some users so revert it until we understand why and safely enable it to save power. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1887 Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Cc: stable@vger.kernel.org
2022-06-28drm/amdgpu/display/dc: Fix null pointer exceptionRahul Kumar1-1/+1
We observed hard hang due to NULL derefrence This issue is seen after running system all the time after two or three days struct dc *dc = plane_state->ctx->dc; Randomly in long run we found plane_state or plane_state->ctx is found NULL which causes exception. BUG: kernel NULL pointer dereference, address: 0000000000000000 PF: supervisor read access in kernel mode PF: error_code(0x0000) - not-present page PGD 1dc7f2067 P4D 1dc7f2067 PUD 222c75067 PMD 0 Oops: 0000 [#1] SMP NOPTI CPU: 5 PID: 29855 Comm: kworker/u16:4 ... ... Workqueue: events_unbound commit_work [drm_kms_helper] RIP: 0010:dcn10_update_pending_status+0x1f/0xee [amdgpu] Code: 41 5f c3 0f 1f 44 00 00 b0 01 c3 0f 1f 44 00 00 41 55 41 54 55 53 48 8b 1f 4c 8b af f8 00 00 00 48 8b 83 88 03 00 00 48 85 db <4c> 8b 20 0f 84 bf 00 00 00 48 89 fd 48 8b bf b8 00 00 00 48 8b 07 RSP: 0018:ffff942941997ab8 EFLAGS: 00010286 RAX: 0000000000000000 RBX: ffff8d7fd98d2000 RCX: 0000000000000000 RDX: 0000000000000000 RSI: ffff8d7e3e87c708 RDI: ffff8d7f2d8c0690 RBP: ffff8d7f2d8c0000 R08: ffff942941997a34 R09: 00000000ffffffff R10: 0000000000005000 R11: 00000000000000f0 R12: ffff8d7f2d8c0690 R13: ffff8d8035a41680 R14: 00000000000186a0 R15: ffff8d7f2d8c1dd8 FS: 0000000000000000(0000) GS:ffff8d8037340000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 0000000000000000 CR3: 0000000148030000 CR4: 00000000003406e0 Call Trace: dc_commit_state+0x6a2/0x7f0 [amdgpu] amdgpu_dm_atomic_commit_tail+0x460/0x19bb [amdgpu] Tested-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-28drm/amd/display : Log DP link training failure reasonChandan Vurdigere Nataraj1-2/+2
[Why] Existing logs doesn't print DP LT failure reason [How] Update the existing log with DP LT failure reason Signed-off-by: Chandan Vurdigere Nataraj <chandan.vurdigerenataraj@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-28drm/amdgpu/display: reduce stack size in dml32_ModeSupportAndSystemConfigurationFull()Alex Deucher2-44/+36
Move more stack variable in to dummy vars structure on the heap. Fixes stack frame size errors: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c: In function 'dml32_ModeSupportAndSystemConfigurationFull': drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:3833:1: error: the frame size of 2720 bytes is larger than 2048 bytes [-Werror=frame-larger-than=] 3833 | } // ModeSupportAndSystemConfigurationFull | ^ Fixes: dda4fb85e433 ("drm/amd/display: DML changes for DCN32/321") Cc: Stephen Rothwell <sfr@canb.auug.org.au> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Rodrigo Siqueira Jordao <Rodrigo.Siqueira@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-23Revert "drm/amd/display: ignore modifiers when checking for format support"Bas Nieuwenhuizen1-46/+7
This reverts commit 5089c4a8ebea3c3ad9eedf038dad7098ebc06131. This breaks validation and enumeration of display capable modifiers. The early return true means the rest of the validation code never gets executed, and we need that to enumerate the right modifiers to userspace for the format. The modifiers that are in the initial list generated for a plane are the superset for all formats and we need the proper checks in this function to filter some of them out for formats with which they're invalid to be used. Furthermore, the safety contract here is that we validate the incoming modifiers to ensure the kernel can handle them and the display hardware can handle them. This includes e.g. rejecting multi-plane images with DCC. Note that the legacy swizzle mechanism allows encoding more swizzles, and at fb creation time we convert them to modifiers and reject those with no corresponding modifiers. If we are seeing rejections I'm happy to help define modifiers that correspond to those, or if absolutely needed implement a fallback path to allow for less strict validation of the legacy path. However, I'd like to revert this patch, since any of these is going to be a significant rework of the patch, and I'd rather not the regression gets into a release or forgotten in the meantime. Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-23drm/amdgpu/display: Fix spelling mistake "supporing" -> "supporting"Colin Ian King1-1/+1
There is a spelling mistake in a dml_print message. Fix it. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-23Revert "drm/amdgpu/display: set vblank_disable_immediate for DC"Alex Deucher1-3/+0
This reverts commit 92020e81ddbeac351ea4a19bcf01743f32b9c800. This causes stuttering and timeouts with DMCUB for some users so revert it until we understand why and safely enable it to save power. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1887 Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
2022-06-23drm/amd/display: Fix indentation in dcn32_get_vco_frequency_from_reg()Nathan Chancellor1-1/+1
Clang warns: drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c:549:4: warning: misleading indentation; statement is not part of the previous 'else' [-Wmisleading-indentation] pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int); ^ drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c:542:3: note: previous statement is here else ^ 1 warning generated. Indent this statement to the left, as it was clearly intended to be called unconditionally, which will fix the warning. Link: https://github.com/ClangBuiltLinux/linux/issues/1655 Fixes: 3e838f7ccf64 ("drm/amd/display: Get VCO frequency from registers") Signed-off-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-22amd/display/dc: Fix COLOR_ENCODING and COLOR_RANGE doing nothing for DCN20+Joshua Ashton3-0/+9
For DCN20 and above, the code that actually hooks up the provided input_color_space got lost at some point. Fixes COLOR_ENCODING and COLOR_RANGE doing nothing on DCN20+. Tested using Steam Remote Play Together + gamescope. Update other DCNs the same wasy DCN1.x was updates in commit a1e07ba89d49 ("drm/amd/display: Use plane->color_space for dpp if specified") Fixes: a1e07ba89d49 ("drm/amd/display: Use plane->color_space for dpp if specified") Signed-off-by: Joshua Ashton <joshua@froggi.es> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2022-06-22drm/amd/display: Fix typo in override_lane_settingsGeorge Shen1-1/+1
[Why] The function currently skips overriding the drive settings of the first lane. [How] Change for loop to start at 0 instead of 1. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2022-06-22drm/amd/display: Fix DC warning at driver loadQingqing Zhuo1-1/+1
[Why] Wrong index was checked for dcfclk_mhz, causing false warning. [How] Fix the assertion index. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org # 5.18.x
2022-06-22drm/amd: Revert "drm/amd/display: keep eDP Vdd on when eDP stream is already enabled"Mario Limonciello1-22/+2
A variety of Lenovo machines with Rembrandt APUs and OLED panels have stopped showing the display at login. This behavior clears up after leaving it idle and moving the mouse or touching keyboard. It was bisected to be caused by commit 559e2655220d ("drm/amd/display: keep eDP Vdd on when eDP stream is already enabled"). Revert this commit to fix the issue. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2047 Reported-by: Aaron Ma <aaron.ma@canonical.com> Fixes: 559e2655220d ("drm/amd/display: keep eDP Vdd on when eDP stream is already enabled") Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Tested-by: Mark Pearson <markpearson@lenovo.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-21drm/amd/display: fix incorrect comparison in DMLAurabindo Pillai1-1/+1
[Why&How] GCC 12 catches the following incorrect comparison in the if arm drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dml/dcn32/display_mode_vba_32.c: In function ‘dml32_ModeSupportAndSystemConfigurationFull’: drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dml/dcn32/display_mode_vba_32.c:3740:33: error: the comparison will always evaluate as ‘true’ for the address of ‘USRRetrainingSupport’ will never be NULL [-Werror=address] 3740 | || &mode_lib->vba.USRRetrainingSupport[i][j])) { | ^~ In file included from ./drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dml/display_mode_lib.h:32, from ./drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dc.h:45, from drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dml/dcn32/display_mode_vba_32.c:30: ./drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dml/display_mode_vba.h:1175:14: note: ‘USRRetrainingSupport’ declared here 1175 | bool USRRetrainingSupport[DC__VOLTAGE_STATES][2]; | Fix this by remove preceding & so that value is compared instead of address Fixes: dda4fb85e433 ("drm/amd/display: DML changes for DCN32/321") Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-21drm/amd/display: fix array index in DMLAurabindo Pillai1-1/+1
[Why&How] When the a 3d array is used by indexing with only one dimension in an if condition, the addresses get compared instead of the intended value stored in the array. GCC 12.1 caught this error: drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dml/dcn32/display_mode_vba_32.c: In function ‘DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation’: drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dml/dcn32/display_mode_vba_32.c:1007:45: error: the comparison will always evaluate as ‘true’ for the address of ‘use_one_row_for_frame_flip’ will never be NULL [-Werror=address] 1007 | if (v->use_one_row_for_frame_flip[k]) { | ^ In file included from ./drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dml/display_mode_lib.h:32, from ./drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dc.h:45, from drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dml/dcn32/display_mode_vba_32.c:30: ./drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dml/display_mode_vba.h:605:14: note: ‘use_one_row_for_frame_flip’ declared here 605 | bool use_one_row_for_frame_flip[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; | Fix this by explicitly specifying the last two indices. Fixes: dda4fb85e433 ("drm/amd/display: DML changes for DCN32/321") Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-21drm/amdgpu: Drop CONFIG_BACKLIGHT_CLASS_DEVICE ifdefsHans de Goede1-14/+1
The DRM_AMDGPU Kconfig code contains: select BACKLIGHT_CLASS_DEVICE So the condition these ifdefs test for is always true, drop them. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-21amd/display/dc: Fix COLOR_ENCODING and COLOR_RANGE doing nothing for DCN20+Joshua Ashton3-0/+9
For DCN20 and above, the code that actually hooks up the provided input_color_space got lost at some point. Fixes COLOR_ENCODING and COLOR_RANGE doing nothing on DCN20+. Tested using Steam Remote Play Together + gamescope. Update other DCNs the same wasy DCN1.x was updates in commit a1e07ba89d49 ("drm/amd/display: Use plane->color_space for dpp if specified") Fixes: a1e07ba89d49 ("drm/amd/display: Use plane->color_space for dpp if specified") Signed-off-by: Joshua Ashton <joshua@froggi.es> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-21drm/amd/display: 3.2.191Aric Cyr1-1/+1
This DC patchset brings improvements in multiple areas. In summary, we highlight: - Remove unnecessary code; - Small fixes (compilation warnings, typos, etc); - Improvements in the DPMS code; - Fix eDP issues - Improvements in the MST code Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-21drm/amd/display: Drop duplicate defineRodrigo Siqueira1-2/+0
We already have DALSMC_MSG_TransferTableDram2Smu in the file dalsmc.h; for this reason, we don't need this definition in the smu msg file. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-21drm/amd/display: Update hook dcn32_funcsRodrigo Siqueira1-1/+2
In DCN32 clk hook functions, we are using the wrong reference for get_dp_ref_clk_frequency and missing the get_dtb_ref_clk_frequency reference. This commit adds those references. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-21drm/amd/display: Implement a pme workaround functionChaitanya Dhere3-1/+10
[Why] For DCN32 we do not have a pme workaround function defined that sends a BacoAudio message. Default code had uses the DCN30 function for pme workaround. PMFW headers are inconsistent with their message ID definitions which cause ID's to clash leading to inconsistent system behaviour. There is a clash with FCLK message due to inconsitent PMFW headers. [How] Implement a new BacoAudio function to workaround the problem of inconsistent PMFW headers in order to avoid BacoAudio message clasing with FCLK Enable message. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Chaitanya Dhere <chaitanya.dhere@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-21drm/amd/display: Get VCO frequency from registersRodrigo Siqueira2-1/+96
Add support to get VCO frequency from registers. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Aurabindo Jayamohanan Pillai <Aurabindo.Pillai@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-21drm/amd/display: Update SW state correctly for FCLKAlvin Lee1-3/+3
FCLK not supported for DCN321, but still need to update the software state accordingly to prevent unneeded full updates in driver Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.