aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd/pm
AgeCommit message (Collapse)AuthorFilesLines
2021-03-23drm/amdgpu/pm: Remove unsupported MP1 messages from aldebaranLijo Lazar2-5/+0
PrepareMp1Reset and SoftReset messages are not supported on aldebaran. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amd/pm: Set no fan control flag as needed.Lijo Lazar1-0/+4
For GPUs that don't support fan control, set the no fan control flag so that they don't appear in hwmon sensors. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amd/pm: Remove CPU virtual address notification in aldebaranLijo Lazar1-17/+0
PPSMC_MSG_SetSystemVirtualDramAddrHigh/Low messages are not handled by PMFW in aldebaran Signed-off-by: Lijo Lazar <Lijo.Lazar@amd.com> Reviewed-by: Kenneth Feng <Kenneth.Feng@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amd/pm: Add support to override pptable id for aldebaranLijo Lazar1-2/+11
Temporarily force to use BU PPTable defined in VBIOS. Add support to override PPTable defined by module parameter.Add FW reported version to kernel log. Signed-off-by: Lijo Lazar <Lijo.Lazar@amd.com> Reviewed-by: Kenneth Feng <Kenneth.Feng@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amd/pm: Add atom_smc_dpm_info_v4_10 for aldebaranLijo Lazar1-0/+22
Add atom_smc_dpm_info_v4_10 that defines board parameters for aldebaran Signed-off-by: Lijo Lazar <Lijo.Lazar@amd.com> Reviewed-by: Kenneth Feng <Kenneth.Feng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: update atom_firmware_info_v3_4 (v2)Feifei Xu1-0/+2
v1: Added some pspbl parameters v2: fix fallthrough issue Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Lazar Lijo <Lijo.Lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amd/pm:add aldebaran support for getting bootup valuesFeifei Xu1-1/+15
for SMU config. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu:return true for mode1_reset_support on aldebaranFeifei Xu1-0/+3
Will remove once validation finished. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu:add smu mode1/2 support for aldebaranFeifei Xu7-6/+104
Use MSG_GfxDriverReset for mode reset and retire MSG_Mode1Reset. Centralize soc15_asic_mode1_reset() and nv_asic_mode1_reset()functions. Add mode2_reset_is_support() for smu->ppt_funcs. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amd/swsmu: add aldebaran smu13 ip support (v3)Kevin Wang12-5/+3797
Add initial swSMU support. v1: add smu13 ip support for aldebaran asic (Kevin/Kenneth) v2: switch to thm/mp v13_0 ip headers (Hawking) v3: squash in updates (Alex) Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amd/swsmu: add aldebaran smu driver if header (v2)Kevin Wang1-0/+512
add aldebaran smu13 driver if header v2: squash in updates Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Kenneth Feng <Kenneth.feng@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-05drm/amd/pm/swsmu: clean up user profile functionArunpravin1-22/+12
Remove unnecessary comments, enable restore mode using '|=' operator, fixes the alignment to improve the code readability. v2: Move all restoration flag check to bitwise '&' operator Signed-off-by: Arunpravin <Arunpravin.PaneerSelvam@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-05drm/amdgpu: enable one vf mode on sienna cichlid vfHorace Chen4-16/+18
sienna cichlid needs one vf mode which allows vf to set and get clock status from guest vm. So now expose the required interface and allow some smu request on VF mode. Also since this asic blocked direct MMIO access, use KIQ to send SMU request under sriov vf. OD use same command as getting pp table which is not allowed for sienna cichlid, so remove OD feature under sriov vf. Signed-off-by: Horace Chen <horace.chen@amd.com> Reviewed-by: Monk Liu<monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-05drm/amd/pm: update existing gpu_metrics interfaces V2Evan Quan8-45/+51
Update the gpu_metrics interface implementations to use the latest upgraded data structures. V2: fit the data type change of energy_accumulator Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-03drm/amd/pm: correct the name of one function for vangoghXiaojian Du1-2/+2
This patch is to correct the name of one function for vangogh. This function is used to print the clock levels of all kinds of IP components. Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-02drm/amd/pm: optimize the link width/speed retrieving V2Evan Quan4-22/+30
By using the information provided by PMFW when available. V2: put those structures shared around SMU V11 ASICs in smu_v11_0.h Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-02drm/amd/pm: bump Navi1x driver if version and related data structures V2Evan Quan3-40/+673
New changes were involved for the SmuMetrics structure. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-26drm/amd/pm/swsmu: Remove unnecessary conversion to boolJiapeng Chong1-1/+1
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c:924:47-52: WARNING: conversion to bool not needed here. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-26amdgpu/pm: read_sensor() report failure apporpriatelyShirish S8-8/+8
report -ENOTSUPP instead of -EINVAL, so that if userspace fails to read sensor data can figure it out the failure correctly. Signed-off-by: Shirish S <shirish.s@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-26drm/amd/pm: correct Arcturus mmTHM_BACO_CNTL register addressEvan Quan1-3/+12
Arcturus has a different register address from other SMU V11 ASICs. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-26drm/amdgpu/swsmu/vangogh: Only use RLCPowerNotify msg for disableAlex Deucher1-2/+2
Per discussions with PMFW team, the driver only needs to notify the PMFW when the RLC is disabled. The RLC FW will notify the PMFW directly when it's enabled. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-26drm/amdgpu/pm: make unsupported power profile messages debugAlex Deucher3-3/+3
Making them an error confuses users and the errors are harmless as not all asics support all profiles. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1488 Acked-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-26amdgpu/pm: Powerplay API for smu , updates to some pm functionsDarren Powell3-73/+48
v3: updated to include new clocks od_vddgfx_offset, od_cclk Context mismatch with revision v3 to patch 0003 Modified Functions smu_sys_set_pp_table() - modifed signature to match Powerplay API set_pp_table smu_force_performance_level() - modifed arg0 to match Powerplay API force_performance_level smu_od_edit_dpm_table() - modifed arg0 to match Powerplay API odn_edit_dpm_table Other Changes smu_od_edit_dpm_table() - removed call to task(READJUST_POWER_STATE) after COMMIT_TABLE, now handled in calling function amdgpu_set_power_dpm_force_performance_level() - now checks thermal for swsmu systems before trying to change level amdgpu_set_pp_od_clk_voltage() - now attempts to set fine_grain_clock_vol before swsmu edit dpm table Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-26amdgpu/pm: Powerplay API for smu , changed 4 dpm functions to use APIDarren Powell3-66/+86
v2: fix errors and warnings flagged by checkpatch v3: Context mismatch with revision v3 to patch 0003 New Functions smu_get_mclk - implementation of the Powerplay API function get_mclk smu_get_sclk - implementation of the Powerplay API function get_sclk smu_handle_dpm_task - implementation of the Powerplay API function dispatch_tasks Modified Functions smu_dpm_set_power_gate - - modifed arg0 to match Powerplay API set_powergating_by_smu Other Changes removed special smu handling in dpm functions and called through Powerplay API call to smu_dpm_set_power_gate via Powerplay API now locks mutex for UVD and VCE Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-26amdgpu/pm: Powerplay API for smu , changes to clock and profile mode functionsDarren Powell3-444/+164
v3: updated to include new clocks vclk, dclk, od_vddgfx_offset, od_cclk Added forward declaration for function smu_force_smuclk_levels to resolve clash with other commits Resolved context clashes with other commits and v3 updates to patches 0003, 0004 v2: fix errors flagged by checkpatch New Functions smu_bump_power_profile_mode() - changes profile mode assuming calling function already has mutex smu_force_ppclk_levels() - accepts Powerplay enum pp_clock_type to specify clock to change smu_print_ppclk_levels() - accepts Powerplay enum pp_clock_type to request clock levels amdgpu_get_pp_dpm_clock() - accepts Powerplay enum pp_clock_type to request clock levels and allows all the amdgpu_get_pp_dpm_$CLK functions to have a single codepath amdgpu_set_pp_dpm_clock() - accepts Powerplay enum pp_clock_type to set clock levels and allows all the amdgpu_set_pp_dpm_$CLK functions to have a single codepath Modified Functions smu_force_smuclk_levels - changed function name to make clear difference to smu_force_ppclk_levels smu_force_ppclk_levels() - modifed signature to implement Powerplay API force_clock_level - calls smu_force_smuclk_levels smu_print_smuclk_levels - changed function name to make clear difference to smu_print_ppclk_levels smu_print_ppclk_levels() - modifed signature to implement Powerplay API force_clock_level - calls smu_print_smuclk_levels smu_sys_get_gpu_metrics - modifed arg0 to match Powerplay API get_gpu_metrics smu_get_power_profile_mode - modifed arg0 to match Powerplay API get_power_profile_mode smu_set_power_profile_mode - modifed arg0 to match Powerplay API set_power_profile_mode - removed arg lock_needed, mutex always locked, internal functions can call smu_bump if they already hold lock smu_switch_power_profile - now calls smu_bump as already holds mutex lock smu_adjust_power_state_dynamic - now calls smu_bump as already holds mutex lock amdgpu_get_pp_od_clk_voltage - uses smu_print_ppclk_levels amdgpu_{set,get}_pp_dpm_$CLK - replace logic with call helper function amdgpu_{set,get}_pp_dpm_clock() CLK ={sclk, mclk, socclk, fclk, dcefclk, pci, vclkd, dclk} Other Changes added 5 smu Powerplay functions to swsmu_dpm_funcs removed special smu handling in pm functions and called through Powerplay API Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-26amdgpu/pm: Powerplay API for smu , changed 5 dpm powergating & sensor functions to use APIDarren Powell3-65/+100
v2: add comment to highlight assignment that changes uint32_t value to int fix errors flagged by checkpatch.pl New Functions smu_get_baco_capability() - Implement Powerplay API get_asic_baco_capability smu_baco_set_state() - Implement Powerplay API set_asic_baco_state Modified Functions smu_read_sensor() - modifed signature to match Powerplay API read_sensor Other Changes added 3 above smu Powerplay functions to swsmu_dpm_funcs removed special smu handling in 5 dpm functions and called through Powerplay API Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-26amdgpu/pm: Powerplay API for smu , changed 9 pm power functions to use APIDarren Powell3-67/+58
v2: remove check for error during swsmu amdgpu_dpm_get_pp_num_states() call to match previous powerplay behaviour v3: removed smu implementation of powerplay get_power_limit Resolved context clashes with other commits Modified Files smu_set_power_limit() - modifed arg0 to match Powerplay API set_power_limit smu_sys_get_pp_table() - modifed signature to match Powerplay API get_pp_table smu_get_power_num_states() - modifed arg0 to match Powerplay API get_pp_num_states smu_get_current_power_state() - modifed arg0 to match Powerplay API get_current_power_state smu_sys_get_pp_feature_mask() - modifed signature to match Powerplay API get_ppfeature_status smu_sys_set_pp_feature_mask() - modifed arg0 to match Powerplay API set_ppfeature_status Other Changes added 6 above smu Powerplay functions to swsmu_dpm_funcs removed special smu handling of above functions and called through Powerplay API Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-26amdgpu/pm: Powerplay API for smu , changed 6 pm hwmon fan functions to use APIDarren Powell3-77/+63
v2: changed error return value of smu_get_fan_control_mode to AMD_FAN_CTRL_NONE fixed type in amdgpu_hwmon_get_pwm1_enable() print statement fixed indent flagged by checkpatch.pl Modified Functions smu_set_fan_speed_rpm() - modifed arg0 to match Powerplay API set_fan_speed_rpm smu_get_fan_control_mode() - modifed signature to match Powerplay API get_fan_control_mode smu_set_fan_control_mode() - modifed signature to match Powerplay API set_fan_control_mode smu_get_fan_speed_percent() - modifed signature to match Powerplay API get_fan_speed_percent smu_set_fan_speed_percent() - modifed signature to match Powerplay API set_fan_speed_percent smu_get_fan_speed_rpm() - modifed arg0 to match Powerplay API get_fan_speed_rpm Other Changes added 6 above smu fan Powerplay functions to swsmu_dpm_funcs removed special smu handling of above functions and called through Powerplay API Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-26amdgpu/pm: Powerplay API for smu , changed 6 dpm reset functions to use APIDarren Powell3-44/+41
Modified Functions smu_set_xgmi_pstate() - modifed arg0 to match Powerplay API set_xgmi_pstate smu_mode2_reset() - modifed arg0 to match Powerplay API asic_reset_mode_2 smu_switch_power_profile() - modifed arg0 to match Powerplay API switch_power_profile smu_set_mp1_state() - modifed arg0 to match Powerplay API set_mp1_state smu_set_df_cstate() - modifed arg0 to match Powerplay API set_df_cstate smu_enable_mgpu_fan_boost() - modifed arg0 to match Powerplay API enable_mgpu_fan_boost Other Changes added above smu reset Powerplay functions to swsmu_dpm_funcs removed special smu handling of above functions and called through Powerplay API Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-26amdgpu/pm: Powerplay API for smu , added get_performance_levelDarren Powell3-5/+13
v2: updated the structure name to swsmu_pm_funcs Modified Functions smu_get_performance_level() - modifed arg0 to match Powerplay API get_performance_level Other Changes added a new structure swsmu_dpm_funcs to hold smu functions for Powerplay API removed special smu handling from amdgpu_get_power_dpm_force_performance_level Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-24drm/amdgpu/swsmu/navi1x: Remove unnecessary conversion to boolJiapeng Chong1-1/+1
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c:900:47-52: WARNING: conversion to bool not needed here. Reviewed-by: Evan Quan <evan.quan@amd.com> Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-24drm/amd/pm/swsmu: Avoid using structure_size uninitialized in smu_cmn_init_soft_gpu_metricsNathan Chancellor1-1/+1
Clang warns: drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu_cmn.c:764:2: warning: variable 'structure_size' is used uninitialized whenever switch default is taken [-Wsometimes-uninitialized] default: ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu_cmn.c:770:23: note: uninitialized use occurs here memset(header, 0xFF, structure_size); ^~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu_cmn.c:753:25: note: initialize the variable 'structure_size' to silence this warning uint16_t structure_size; ^ = 0 1 warning generated. Return in the default case, as the size of the header will not be known. Fixes: de4b7cd8cb87 ("drm/amd/pm/swsmu: unify the init soft gpu metrics function") Link: https://github.com/ClangBuiltLinux/linux/issues/1304 Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18drm/amd/pm: do not issue message while write "r" into pp_od_clk_voltageHuang Rui3-70/+0
We should commit the value after restore them back to default as well. $ echo "r" > pp_od_clk_voltage $ echo "c" > pp_od_clk_voltage Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18drm/amd/pm: Replace one-element array with flexible-array in struct _ATOM_Vega10_GFXCLK_Dependency_TableGustavo A. R. Silva1-3/+3
There is a regular need in the kernel to provide a way to declare having a dynamically sized set of trailing elements in a structure. Kernel code should always use “flexible array members”[1] for these cases. The older style of one-element or zero-length arrays should no longer be used[2]. Use flexible-array member in struct _ATOM_Vega10_GFXCLK_Dependency_Table, instead of one-element array. Also, this helps with the ongoing efforts to enable -Warray-bounds and fix the following warning: drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c: In function ‘vega10_get_pp_table_entry_callback_func’: drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:3113:30: warning: array subscript 4 is above array bounds of ‘ATOM_Vega10_GFXCLK_Dependency_Record[1]’ {aka ‘struct _ATOM_Vega10_GFXCLK_Dependency_Record[1]’} [-Warray-bounds] 3113 | gfxclk_dep_table->entries[4].ulClk; | ~~~~~~~~~~~~~~~~~~~~~~~~~^~~ [1] https://en.wikipedia.org/wiki/Flexible_array_member [2] https://www.kernel.org/doc/html/v5.9/process/deprecated.html#zero-length-and-one-element-arrays Link: https://github.com/KSPP/linux/issues/79 Link: https://github.com/KSPP/linux/issues/109 Build-tested-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/lkml/6023ff3d.WY3sSCkGRQPdPlVo%25lkp@intel.com/ Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18drm/amd/pm: Replace one-element array with flexible-array in struct SISLANDS_SMC_SWSTATEGustavo A. R. Silva2-9/+7
There is a regular need in the kernel to provide a way to declare having a dynamically sized set of trailing elements in a structure. Kernel code should always use “flexible array members”[1] for these cases. The older style of one-element or zero-length arrays should no longer be used[2]. Refactor the code according to the use of a flexible-array member in struct SISLANDS_SMC_SWSTATE, instead of a one-element array, and use the struct_size() helper to calculate the size for the allocation. Also, this helps with the ongoing efforts to enable -Warray-bounds and fix the following warnings: drivers/gpu/drm/amd/amdgpu/../pm/powerplay/si_dpm.c:2448:20: warning: array subscript 1 is above array bounds of ‘SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’ {aka ‘struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’} [-Warray-bounds] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/si_dpm.c:2449:20: warning: array subscript 1 is above array bounds of ‘SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’ {aka ‘struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’} [-Warray-bounds] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/si_dpm.c:2450:20: warning: array subscript 1 is above array bounds of ‘SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’ {aka ‘struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’} [-Warray-bounds] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/si_dpm.c:2451:20: warning: array subscript 1 is above array bounds of ‘SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’ {aka ‘struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’} [-Warray-bounds] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/si_dpm.c:2452:20: warning: array subscript 1 is above array bounds of ‘SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’ {aka ‘struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’} [-Warray-bounds] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/si_dpm.c:5570:20: warning: array subscript 1 is above array bounds of ‘SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’ {aka ‘struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’} [-Warray-bounds] [1] https://en.wikipedia.org/wiki/Flexible_array_member [2] https://www.kernel.org/doc/html/v5.9/process/deprecated.html#zero-length-and-one-element-arrays Link: https://github.com/KSPP/linux/issues/79 Link: https://github.com/KSPP/linux/issues/109 Build-tested-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/lkml/6023be58.sk66L%2FV4vuSJI5mI%25lkp@intel.com/ Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18drm/amd/pm: fix spelling mistake in various messages "power_dpm_force_perfomance_level"Colin Ian King3-3/+3
There are spelling mistakes in error and warning messages, the text power_dpm_force_perfomance_level is missing a letter r and should be power_dpm_force_performance_level. Fix them. Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18drm/amd/pm: do not use drm middle layer for debugfsNirmoy Das2-14/+13
Use debugfs API directly instead of drm middle layer. v2: * checkpatch.pl: use '0444' instead of S_IRUGO. * remove S_IFREG from mode. * remove mode variable. Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18drm/amdgpu: do not keep debugfs dentryNirmoy Das1-3/+0
Cleanup unnecessary debugfs dentries and surrounding functions. v3: remove return value check for debugfs_create_file() v2: remove ttm_debugfs_entries array. do not init variables. Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-09drm/amd/pm: make the error log more clear for fine grain tuning functionXiaojian Du3-3/+5
This patch is to make the error log more clear for fine grain tuning function, it covers Raven/Raven2/Picasso/Renoir/Vangogh. The fine grain tuning function uses the sysfs file -- pp_od_clk_voltage, but only when another sysfs file -- power_dpm_force_performance_level is switched to "manual" mode, it is allowed to access "pp_od_clk_voltage". Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Acked-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-09drm/amd/pm: enable LCLK DSKenneth Feng1-0/+3
Enable LCLK deep sleep and it works if we enable ASPM: modprobe amdgpu aspm=1 Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-09drm/amd/pm: add support for hwmon control of slow and fast PPT limit on vangoghXiaomeng Hou6-18/+204
Implement hwmon API for reading/setting slow and fast PPT limit. APU power is managed to system-level requirements through the PPT (package power tracking) feature. PPT is intended to limit power to the requirements of the power source and could be dynamically updated to maximize APU performance within the system power budget. Here FAST_PPT_LIMIT manages the ~10 ms moving average of APU power, while SLOW_PPT_LIMIT manages the configurable, thermally significant moving average of APU power (default ~5000 ms). User could read slow/fast ppt limit using command "cat power*_cap" or "sensors" in the hwmon device directory. User could adjust values of slow/fast ppt limit as needed depending on workloads through command "echo ## > power*_cap". Example: $ echo 15000000 > power1_cap $ echo 18000000 > power2_cap $ sensors amdgpu-pci-0300 Adapter: PCI adapter slowPPT: 9.04W (cap = 15.00 W) fastPPT: 9.04W (cap = 18.00 W) v2: align with existing interfaces for the getting/setting of PPT limits. Encode the upper 8 bits of limit value to distinguish slow and fast power limit type. Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-09drm/amd/pm: modify the power limit level parameter from bool to enum typeXiaomeng Hou3-5/+21
The original smu_get_power_limit callback accepts the power limit level parameter as bool which limits to max and current. For possible needs to retrieve other level like min, extend the parameter type using enum. Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-09drm/amd/pm: update the smu v11.5 smc header for vangoghXiaomeng Hou2-1/+9
Add PP messages for reading/setting Fast PPT and Slow PPT limit. Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-09drm/amd/pm/swsmu: unify the init soft gpu metrics functionKevin Wang11-47/+45
the soft gpu metrics is not asic related data structure. unify them to reduce duplicate code. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-09drm/amd/pm: enable DCSKenneth Feng1-0/+5
Enable DCS V1: Enable Async DCS. V2: Add the ppfeaturemask bit to enable from the modprobe parameter. V3: 1. add the flag to skip APU support. 2. remove the hunk for workload selection since it doesn't impact the function. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-09drm/amdgpu/smu12: fix power reporting on renoirAlex Deucher1-1/+1
Align with Vangogh. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1467 Acked-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-09drm/amd/pm: enable ACDC featureKenneth Feng1-0/+3
The power limit and clock ragne are different in AC mode and DC mode. Firmware does the setting after this feature is enabled. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amdgpu: Prevent shift wrapping in amdgpu_read_mask()Dan Carpenter1-3/+3
If the user passes a "level" value which is higher than 31 then that leads to shift wrapping. The undefined behavior will lead to a syzkaller stack dump. Fixes: 5632708f4452 ("drm/amd/powerplay: add dpm force multiple levels on cz/tonga/fiji/polaris (v2)") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/pm: Disable GFXOFF when GFX DPM or PG disabledJinzhou Su1-4/+10
Check GFX DPM and PG bit before enable GFXOFF on Vangogh smu post init. Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/pm: remove some useless code for vangoghXiaojian Du1-3/+0
This patch is to remove some useless code for vangogh. In the earlier code, vangogh can't finish all the sequence of smu late init. But now vangogh has one stable work state,so remove the useless code. Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Copyright © 1996 – 2026 Jason A. Donenfeld. All Rights Reverse Engineered.