aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd (follow)
AgeCommit message (Collapse)AuthorFilesLines
2018-05-31drm/amd/display: Update color props when modeset is requiredLeo (Sunpeng) Li1-2/+6
This fixes issues where color management properties don't persist over DPMS on/off, or when the CRTC is moved across connectors. Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-31drm/amd/display: Make atomic-check validate underscan changesDavid Francis1-7/+16
When the underscan state was changed, atomic-check was triggering a validation but passing the old underscan values. This change adds a somewhat hacky check in dm_update_crtcs_state that will update the stream if old and newunderscan values are different. This was causing 4k on Fiji to allow underscan when it wasn't permitted. Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-30drm/amdgpu/display: check if ppfuncs exists before using itAlex Deucher1-1/+1
Fixes a crash on asics without powerplay yet (e.g., vega20). Reviewed-by: Rex Zhu<rezhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-30drm/amd/pp: Connect display_clock_voltage_request to a function pointerMikita Lipski1-33/+31
Get rid of an empty dublicate of smu10_display_clock_voltage_request Add display_clock_voltage_request to smu10 functions struct so it can be called from outside the class and connect the pointer to the function. That way Display driver can finally apply clock voltage requests when needed. Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-30drm/amdgpu: typo fix for vega20 cg flagsEvan Quan1-0/+1
The AMD_CG_SUPPORT_HDP_LS was wrongly written as AMD_CG_SUPPORT_BIF_LS. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-30drm/amd/powerplay: bug fixs for getsmuclockinfoEvan Quan1-1/+3
The .syspll_id and .dfsdid are not initialzed correctly. And le32_to_cpu transfer is needed on the output. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-30drm/amdgpu: correct SMU11 SYSPLL0 clock id valuesEvan Quan1-7/+5
The SMU11 SYSPLL0 clock ids were assigned wrong values. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-30drm/amdgpu: gds bo must not be per-vm-boChunming Zhou1-0/+7
In per-vm-bo case, there could be no bo list. But gds bo created from user space must be passed to bo list. So adding a check to prevent to creat gds bo as per-vm-bo. Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-30drm/amdgpu: To get gds, gws and oa from adev->gds (v2)Emily Deng1-15/+23
As now enabled per vm bo feature, the user mode driver won't supply the bo_list generally, for this case, the gdb_base, gds_size, gws_base, gws_size and oa_base, oa_size won't be set. v2: fix warning (Chunming) Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-30PM / Domains: Drop genpd as in-param for pm_genpd_remove_device()Ulf Hansson1-1/+1
There is no need to pass a genpd struct to pm_genpd_remove_device(), as we already have the information about the PM domain (genpd) through the device structure. Additionally, we don't allow to remove a PM domain from a device, other than the one it may have assigned to it, so really it does not make sense to have a separate in-param for it. For these reason, drop it and update the current only call to pm_genpd_remove_device() from amdgpu_acp. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2018-05-29drm/amd/display: Fix BUG_ON during CRTC atomic check updateLeo (Sunpeng) Li1-6/+7
For cases where the CRTC is inactive (DPMS off), where a modeset is not required, yet the CRTC is still in the atomic state, we should not attempt to update anything on it. Previously, we were relying on the modereset_required() helper to check the above condition. However, the function returns false immediately if a modeset is not required, ignoring the CRTC's enable/active state flags. The correct way to filter is by looking at these flags instead. Fixes: e277adc5a06c "drm/amd/display: Hookup color management functions" Bugzilla: https://bugs.freedesktop.org/106194 Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-29drm/amd/display: Fix BUG_ON during CRTC atomic check updateLeo (Sunpeng) Li1-6/+7
For cases where the CRTC is inactive (DPMS off), where a modeset is not required, yet the CRTC is still in the atomic state, we should not attempt to update anything on it. Previously, we were relying on the modereset_required() helper to check the above condition. However, the function returns false immediately if a modeset is not required, ignoring the CRTC's enable/active state flags. The correct way to filter is by looking at these flags instead. Fixes: e277adc5a06c "drm/amd/display: Hookup color management functions" Bugzilla: https://bugs.freedesktop.org/106194 Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-29drm/amd/display: Read DP_SINK_COUNT_ESI range on HPD for DP 1.4Nikola Cornij1-5/+30
DP 1.4 compliance now requires that registers at DP_SINK_COUNT_ESI range (0x2002-0x2003, 0x200c-0x200f) are read instead of DP_SINK_COUNT range (0x200-0x2005. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-29drm/amd/display: Read DPCD link caps up to and including DP_ADAPTER_CAPNikola Cornij1-1/+1
DP 1.4 compliance requires 16 bytes to be read when reading link caps, i.e. it requires DP_ADAPTER_CAP to be included. Included it for all DP versions because reading more than required won't fail. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-29drm/amd/display: Do not program interrupt status on disabled crtcMikita Lipski1-0/+3
Prevent interrupt programming of a crtc on which the stream is disabled and it doesn't have an OTG to reference. Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-29drm/amd/display: fix dscl_manual_ratio_initDmytro Laktyushkin5-11/+13
This change will fix wb and display scaling when ratios of 4 or more are involved Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-29drm/amd/display: Destroy connector state on resetLeo (Sunpeng) Li1-2/+4
When a DRM mode reset is called on resume, the connector state's destructor is not called. This leaves a dangling reference on the CRTC commit object, which was obtained by the connector state during commit setup. Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-29drm/amd/display: Set TMZ and DCC for secondary surfaceEric Bernstein2-4/+18
Add register programming to support TMZ and DCC on secondary surfaces. Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-29drm/amd/display: DP component depth 16 bpcEric Bernstein1-0/+4
Add register programming to support 16bpc component depth for DP. Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-29drm/amd/display: check if audio clk enable is applicableRoman Li1-1/+2
Fixing warning on dce10 with HDMI display. Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-29drm/amd/display: add register offset != 0 check.Charlene Liu2-2/+3
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-29drm/amd/display: Release fake sinkMikita Lipski1-15/+16
If connector doesn't have a sink, fake sink is created, but never released as it assumed that its destroyed with the stream it is used for. But now sink is released before the stream maintaing refcount consistency. This way we also avoid assigning anything to connector keeping all the operation local. Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-29drm/amd/display: replace msleep with udelay in fbc pathRoman Li1-4/+4
FBC enabling and disabling path has msleep which leads to BUG hit when called in atomic context, hence this patch replaces msleeps with udelays appropriately. Signed-off-by: Shirish S <shirish.s@amd.com> Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-29drm/amd/display: Do not limit color depth to 8bpcMikita Lipski1-6/+0
Delete if statement that would force any display's color depth higher than 8 bpc to 8 Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-29drm/amdgpu: remove unnecessary scheduler entity for VCNLeo Liu2-43/+10
It should be stateless, and no need for scheduler to take care specially. Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-29drm/amdgpu: Add helper function to get buffer domainDeepak Sharma3-13/+17
Move logic of getting supported domain to a helper function Signed-off-by: Deepak Sharma <Deepak.Sharma@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-29drm/amdgpu: Use GTT for dumb buffer if sg display enabled (v2)Deepak Sharma1-2/+8
When vram size <= THRESHOLD(256M) lets use GTT for dumb buffer allocation. As SG will be enabled with vram size <= 256M scan out will not be an issue. v2: Use amdgpu_display_supported_domains to get supported domain. Signed-off-by: Deepak Sharma <Deepak.Sharma@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-29drm/amd/pp: Add cases for getting phys and disp clks for SMU10Mikita Lipski1-0/+6
Add case options to retrieve either physical or display clocks with voltage from SMU controller that are needed by display driver. Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-29drm/amd/display: Fix wrong latency assignment for VEGA clock levelsHarry Wentland1-2/+1
Also drop wrong 10kHz comment Fixes: drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latency Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-25drm/amdgpu: vcn_v1_0_is_idle() can be statickbuild test robot1-2/+2
Fixes: 9b4c412a654c ("drm/amdgpu: Add static CG control for VCN on RV") Signed-off-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-25drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latencyHarry Wentland1-2/+44
This is required so we use the correct minimum clocks for Vega. Without this pplib will never be able to enter the lowest clock states. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-25drm/amdgpu: fix 32-bit build warningArnd Bergmann1-2/+2
Casting a pointer to a 64-bit type causes a warning on 32-bit targets: drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:473:24: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast] lower_32_bits((uint64_t)wptr)); ^ drivers/gpu/drm/amd/amdgpu/amdgpu.h:1701:53: note: in definition of macro 'WREG32' #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) ^ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:473:10: note: in expansion of macro 'lower_32_bits' lower_32_bits((uint64_t)wptr)); ^~~~~~~~~~~~~ The correct method is to cast to 'uintptr_t'. Fixes: d5a114a6c5f7 ("drm/amdgpu: Add GFXv9 kfd2kgd interface functions") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
2018-05-25Merge branch 'drm-next-4.18' of git://people.freedesktop.org/~agd5f/linux into drm-nextDave Airlie135-2819/+6950
Last feature request for 4.18. Mostly vega20 support. - Vega20 support - clock and powergating for VCN - misc bug fixes Signed-off-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180524152427.32713-1-alexander.deucher@amd.com
2018-05-24drm/amdgpu: Use dev_info() to report amdkfd is not supported for this ASICTom Stellard1-1/+1
This is an important message, so it should be visible to users without having to enable extra debugging. Signed-off-by: Tom Stellard <tstellar@redhat.com> Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
2018-05-24drm/amd/display: Remove use of division operator for long longsDavid Francis1-1/+1
In fixed31_32.h, in dc_fixpt_shl,'/' was used for division of one long long int by another long long int. As there is no inbuilt long long int division function in c, gcc inserted its own. However, gcc does not link the library that contains this function. To avoid this, use bitwise operators instead of / Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-24drm/amdgpu: Update GFX info structure to match what vega20 usedShaoyun Liu2-6/+5
Update to the latest version from the vbios team. Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-24drm/amdgpu/pp: remove duplicate assignmentAlex Deucher1-1/+0
is_dpm_running callback was assigned to the same value twice. Drop the duplicate. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-24drm/amdgpu: move VM BOs on LRU againChristian König2-5/+26
Move all BOs belonging to a VM on the LRU with every submission. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-24drm/amdgpu: consistenly use VM moved flagChristian König1-13/+15
Instead of sometimes checking if the vm_status is empty use the moved flag and also reset it when the BO leaves the state machine. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-24drm/amdgpu: kmap PDs/PTs in amdgpu_vm_update_directoriesChristian König1-7/+8
In theory it is possible that PDs/PTs can move without eviction. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-24drm/amdgpu: further optimize amdgpu_vm_handle_movedChristian König1-13/+14
Splice the moved list to a local one to avoid taking the lock over and over again. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-24drm/amdgpu: cleanup amdgpu_vm_validate_pt_bos v2Christian König1-12/+7
Use list_for_each_entry_safe here. v2: Drop the optimization, it doesn't work as expected. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-24drm/amdgpu: rework VM state machine lock handling v2Christian König2-49/+21
Only the moved state needs a separate spin lock protection. All other states are protected by reserving the VM anyway. v2: fix some more incorrect cases Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-24drm/amdgpu: Add runtime VCN PG supportRex Zhu2-18/+30
Enable support for dynamically powering up/down VCN on demand. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-24drm/amdgpu: Enable VCN static PG by default on RVRex Zhu1-1/+2
Enable static VCN powergating by default on Raven. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-24drm/amdgpu: Add VCN static PG support on RVRex Zhu2-1/+102
Implement static powergating suport on VCN. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-24drm/amdgpu: Enable VCN CG by default on RVRex Zhu1-1/+2
Enable VCN clockgating by default on Raven. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-24drm/amdgpu: Add static CG control for VCN on RVRex Zhu1-11/+39
Implement proper static clockgating support for VCN. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-24drm/amdgpu: Add SOC15_WAIT_ON_RREG macro defineRex Zhu1-0/+15
Add new macro to wait on a register field to be a specific value. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-24drm/amdgpu: Add CG/PG flags for VCNRex Zhu1-1/+2
Define new clock and powergating flags for VCN block. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.