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2021-11-22drm/amd/display: 3.2.162Aric Cyr1-1/+1
This version brings along following fixes: - Fix issue that secondary display goes blank on Non DCN31. - Adjust flushing data in DMCUB - Revert patches which cause regression in hadnling MPO/Link encoder assignment - Correct the setting within MSA of DP2.0 - Adjustment for DML isolation - Fix FIFO erro in fast boot sequence - Enable DSC over eDP - Adjust the DSC power off sequence Reviewed-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-22drm/amd/display: fixed the DSC power off sequence during Driver PnPYi-Ling Chen9-5/+62
[WHY] After unloading driver, driver would not disable DSC function. At next loading driver, driver would power all DSC engines off. When driver powered the active DSC off, the screen would be gray until reprograming DSC relatived register correcntly. [HOW] 1. Remove DSC Power down code into init_pipes() 2. Depend on the OTG mapping information and DSC status to skip power off for the working DSC. Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Yi-Ling Chen <Yi-Ling.Chen2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-22drm/amd/display: [FW Promotion] Release 0.0.93Anthony Koo1-5/+5
- Fix ARR39-C issue with scaled integer addition in rb func Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-22drm/amd/display: [FW Promotion] Release 0.0.92Anthony Koo1-2/+2
Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-22drm/amd/display: Visual Confirm Bar Height Adjusthvanzyll2-1/+15
[What] This change allows adjustment to the Visual Confirm height border. [Why] Aids debugging and testing [How] Use the existing infrastructure to implement logic to draw borders Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Harry VanZyllDeJong <hvanzyll@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-22drm/amd/display: Fix eDP will flash when boot to OSBrandon Syu2-2/+5
[WHY] With eDP DSC enabled and set 4K 60Hz, there would be screen corruption when booting to OS or enabling the driver. [HOW] Avoid powering down VDD when we cannot apply eDP fast boot. Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Brandon Syu <Brandon.Syu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-22drm/amd/display: Enable DSC over eDPMikita Lipski11-7/+255
[why] - Adding a DM interface to enable DSC over eDP on Linux - DSC over eDP will allow to power savings by reducing the bandwidth required to support panel's modes - Apply link optimization algorithm to reduce link bandwidth when DSC is enabled [how] - Read eDP panel's DSC capabilities - Apply DSC policy on eDP panel based on its DSC capabilities - Enable DSC encoder's on the pipe - Enable DSC on panel's side by setting DSC_ENABLE DPCD register - Adding link optimization algorithm to reduce link rate or lane count based Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-22drm/amd/display: Fix LTTPR not EnabledAngus Wang3-0/+52
[WHY] Previous LTTPR change has caused a regression that led to an issue where LTTPR is disabled [HOW] Extended changes from previous fix to DCN30X Reviewed-by: Wesley Chalmers <wesley.chalmers@amd.com> Reviewed-by: Martin Leung <Martin.Leung@amd.com> Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Angus Wang <angus.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-22drm/amd/display: Reset fifo after enable otgXu, Jinze6-0/+31
[Why] In fast boot sequence, when change dispclk, otg is disabled but digfe is enabled. This may cause dig fifo error. [How] Reset dig fifo after enable otg. Reviewed-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: JinZe.Xu <JinZe.Xu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-22drm/amd/display: Code change for DML isolationJun Lei4-0/+2208
[why] DML itself is SW only, putting the logic as part of resource makes it hw dependent and thus impossible to compile separately from dc. Separate compilation is critical for unit testing as well as bbox tool development [how] create new dml wrapper. Copy logic from the validation functions into dml wrapper as base implementation. Dml wrapper has internal/static implementations for all helpers, and does not reference other functions. It may reference dc structures/types for convenience. This change now has all the changes for DML isolation squashed into one. Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Jun Lei <jun.lei@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-22drm/amd/display: set MSA vsp/hsp to 0 for positive polarity for DP 128b/132bWenjing Liu1-2/+2
[why] There is a bug in MSA programming sequence that mistakenly set MSA vsp/hsp to 1 for positive polarity. This is incorrect. Reviewed-by: Ariel Bernstein <Eric.Bernstein@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-22drm/amd/display: Revert changes for MPO underflowAngus Wang4-4/+4
[WHY] The previous changes for fixing MPO underflow with multiple display connected caused a regression where the machine runs into a hang when doing multiple driver pnp with multiple displays connected [HOW] Reverted offending change Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Angus Wang <angus.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-22drm/amd/display: Only flush delta from last command executionNicholas Kazlauskas2-1/+9
[Why] We're currently flushing commands that had been previously been flushed or are currently being processed by the DMCUB when we don't immediately wait for idle after command execution. [How] Avoiding reflushing the data by keeping track of the last wptr. We'll treat this as the actual rptr by creating a copy of the inbox and modifying the copy's rptr. Reviewed-by: Eric Yang <Eric.Yang2@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-22drm/amd/display: Secondary display goes blank on Non DCN31Ahmad Othman1-1/+2
[Why] Due to integration issues with branch merging, a regression happened that prevented secondary displays from lighting up or enabling certain features [How] Separated the new logic to be for DCN31 only and retained pre DCN31 logic for all other ASICs Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Ahmad Othman <Ahmad.Othman@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-22drm/amdgpu: Pin MMIO/DOORBELL BO's in GTT domainRamesh Errabolu1-0/+69
MMIO/DOORBELL BOs encode control data and should be pinned in GTT domain before enabling PCIe connected peer devices in accessing it Signed-off-by: Ramesh Errabolu <Ramesh.Errabolu@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-22drm/amdgpu: Update BO memory accounting to rely on allocation flagRamesh Errabolu2-36/+65
Accounting system to track amount of available memory (system, TTM and VRAM of a device) relies on BO's domain. The change is to rely instead on allocation flag indicating BO type - VRAM, GTT, USERPTR, MMIO or DOORBELL Signed-off-by: Ramesh Errabolu <Ramesh.Errabolu@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-22drm/amd/display: Reduce dmesg error to a debug printLeo (Hanghong) Ma1-1/+1
[Why & How] Dmesg errors are found on dcn3.1 during reset test, but it's not a really failure. So reduce it to a debug print. Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-22drm/amd/display: Drop config guard for DC_LOG_DP2Leo (Hanghong) Ma1-4/+0
[Why & How] It doesn't make sense to guard DC_LOG_DP2 by CONFIG_DRM_AMD_DCN, and this also caused build failure for allmodconfig; So drop the guard to fix the compile failure; Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-18Merge drm/drm-next into drm-misc-nextThomas Zimmermann178-3169/+4353
Backmerging from drm/drm-next for v5.16-rc1. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
2021-11-17drm/amd/amdgpu: fix potential memleakBernard Zhao1-0/+1
In function amdgpu_get_xgmi_hive, when kobject_init_and_add failed There is a potential memleak if not call kobject_put. Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Bernard Zhao <bernard@vivo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-17drm/amd/amdkfd: Fix kernel panic when reset failed and been triggered againshaoyunl1-0/+5
In SRIOV configuration, the reset may failed to bring asic back to normal but stop cpsch already been called, the start_cpsch will not be called since there is no resume in this case. When reset been triggered again, driver should avoid to do uninitialization again. Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-17drm/amd/pm: add GFXCLK/SCLK clocks level print support for APUsPerry Yuan4-2/+74
add support that allow the userspace tool like RGP to get the GFX clock value at runtime, the fix follow the old way to show the min/current/max clocks level for compatible consideration. === Test === $ cat /sys/class/drm/card0/device/pp_dpm_sclk 0: 200Mhz * 1: 1100Mhz 2: 1600Mhz then run stress test on one APU system. $ cat /sys/class/drm/card0/device/pp_dpm_sclk 0: 200Mhz 1: 1040Mhz * 2: 1600Mhz The current GFXCLK value is updated at runtime. BugLink: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5260 Reviewed-by: Huang Ray <Ray.Huang@amd.com> Signed-off-by: Perry Yuan <Perry.Yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2021-11-17drm/amdgpu: fix set scaling mode Full/Full aspect/Center not works on vga and dvi connectorshongao1-0/+1
amdgpu_connector_vga_get_modes missed function amdgpu_get_native_mode which assign amdgpu_encoder->native_mode with *preferred_mode result in amdgpu_encoder->native_mode.clock always be 0. That will cause amdgpu_connector_set_property returned early on: if ((rmx_type != DRM_MODE_SCALE_NONE) && (amdgpu_encoder->native_mode.clock == 0)) when we try to set scaling mode Full/Full aspect/Center. Add the missing function to amdgpu_connector_vga_get_mode can fix this. It also works on dvi connectors because amdgpu_connector_dvi_helper_funcs.get_mode use the same method. Signed-off-by: hongao <hongao@uniontech.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2021-11-17drm/amd/display: Fix OLED brightness control on eDPRoman Li1-1/+2
[Why] After commit ("drm/amdgpu/display: add support for multiple backlights") number of eDPs is defined while registering backlight device. However the panel's extended caps get updated once before register call. That leads to regression with extended caps like oled brightness control. [How] Update connector ext caps after register_backlight_device Fixes: 7fd13baeb7a3a4 ("drm/amdgpu/display: add support for multiple backlights") Link: https://www.reddit.com/r/AMDLaptops/comments/qst0fm/after_updating_to_linux_515_my_brightness/ Signed-off-by: Roman Li <Roman.Li@amd.com> Tested-by: Samuel Čavoj <samuel@cavoj.net> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jasdeep Dhillon <Jasdeep.Dhillon@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2021-11-17drm/amd/pm: Remove artificial freq level on Navi1xLijo Lazar1-5/+8
Print Navi1x fine grained clocks in a consistent manner with other SOCs. Don't show aritificial DPM level when the current clock equals min or max. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-17drm/amd/pm: avoid duplicate powergate/ungate settingEvan Quan4-1/+23
Just bail out if the target IP block is already in the desired powergate/ungate state. This can avoid some duplicate settings which sometimes may cause unexpected issues. Link: https://lore.kernel.org/all/YV81vidWQLWvATMM@zn.tnic/ Bug: https://bugzilla.kernel.org/show_bug.cgi?id=214921 Bug: https://bugzilla.kernel.org/show_bug.cgi?id=215025 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1789 Fixes: bf756fb833cb ("drm/amdgpu: add missing cleanups for Polaris12 UVD/VCE on suspend") Signed-off-by: Evan Quan <evan.quan@amd.com> Tested-by: Borislav Petkov <bp@suse.de> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2021-11-17drm/amdgpu: add error print when failing to add IP block(v2)Guchun Chen1-0/+36
Driver initialization is driven by IP version from IP discovery table. So add error print when failing to add ip block during driver initialization, this will be more friendly to user to know which IP version is not correct. [ 40.467361] [drm] host supports REQ_INIT_DATA handshake [ 40.474076] [drm] add ip block number 0 <nv_common> [ 40.474090] [drm] add ip block number 1 <gmc_v10_0> [ 40.474101] [drm] add ip block number 2 <psp> [ 40.474103] [drm] add ip block number 3 <navi10_ih> [ 40.474114] [drm] add ip block number 4 <smu> [ 40.474119] [drm] add ip block number 5 <amdgpu_vkms> [ 40.474134] [drm] add ip block number 6 <gfx_v10_0> [ 40.474143] [drm] add ip block number 7 <sdma_v5_2> [ 40.474147] amdgpu 0000:00:08.0: amdgpu: Fatal error during GPU init [ 40.474545] amdgpu 0000:00:08.0: amdgpu: amdgpu: finishing device. v2: use dev_err to multi-GPU system Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-17drm/amd/pm: Enhanced reporting also for a stuck commandLuben Tuikov1-2/+6
Also print the message index and parameter of the stuck command. Cc: Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Acked-by: Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-17drm/amd/pm: add GFXCLK/SCLK clocks level print support for APUsPerry Yuan4-2/+74
add support that allow the userspace tool like RGP to get the GFX clock value at runtime, the fix follow the old way to show the min/current/max clocks level for compatible consideration. === Test === $ cat /sys/class/drm/card0/device/pp_dpm_sclk 0: 200Mhz * 1: 1100Mhz 2: 1600Mhz then run stress test on one APU system. $ cat /sys/class/drm/card0/device/pp_dpm_sclk 0: 200Mhz 1: 1040Mhz * 2: 1600Mhz The current GFXCLK value is updated at runtime. BugLink: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5260 Reviewed-by: Huang Ray <Ray.Huang@amd.com> Signed-off-by: Perry Yuan <Perry.Yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-17drm/amdkfd: replace asic_family with asic_typeGraham Sider10-53/+22
asic_family was a duplicate of asic_type, both of type amd_asic_type. Replace all instances of device_info->asic_family with adev->asic_type and remove asic_family from device_info. Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-17drm/amdkfd: convert misc checks to IP version checkingGraham Sider10-35/+33
Switch to IP version checking instead of asic_type on various KFD version checks. Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-17drm/amdkfd: convert switches to IP version checkingGraham Sider6-155/+102
Converts KFD switch statements to use IP version checking instead of asic_type. Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-17drm/amdkfd: convert KFD_IS_SOC to IP version checkingGraham Sider4-5/+6
Defined as GC HWIP >= IP_VERSION(9, 0, 1). Also defines KFD_GC_VERSION to return GC HWIP version. Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-17drm/amdgpu: add error print when failing to add IP block(v2)Guchun Chen1-0/+36
Driver initialization is driven by IP version from IP discovery table. So add error print when failing to add ip block during driver initialization, this will be more friendly to user to know which IP version is not correct. [ 40.467361] [drm] host supports REQ_INIT_DATA handshake [ 40.474076] [drm] add ip block number 0 <nv_common> [ 40.474090] [drm] add ip block number 1 <gmc_v10_0> [ 40.474101] [drm] add ip block number 2 <psp> [ 40.474103] [drm] add ip block number 3 <navi10_ih> [ 40.474114] [drm] add ip block number 4 <smu> [ 40.474119] [drm] add ip block number 5 <amdgpu_vkms> [ 40.474134] [drm] add ip block number 6 <gfx_v10_0> [ 40.474143] [drm] add ip block number 7 <sdma_v5_2> [ 40.474147] amdgpu 0000:00:08.0: amdgpu: Fatal error during GPU init [ 40.474545] amdgpu 0000:00:08.0: amdgpu: amdgpu: finishing device. v2: use dev_err to multi-GPU system Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-17drm/amd/pm: Enhanced reporting also for a stuck commandLuben Tuikov1-2/+6
Also print the message index and parameter of the stuck command. Cc: Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Acked-by: Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-17drm/amdgpu: remove unneeded variableran jianping1-2/+2
Fix the following coccicheck review: ./drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c:1174:14-18 :Unneeded variable Remove unneeded variable used to store return value. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: ran jianping <ran.jianping@zte.com.cn> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-17drm/amdkfd: replace trivial funcs with direct accessGraham Sider6-47/+10
These get funcs simply return an adev field. Replace funcs/calls with direct field accesses instead. Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-17drm/amd/display: log amdgpu_dm_atomic_check() failure causeShirish S1-18/+51
update developers with next level of info about unsupported display configuration query that led to atomic check failure. Signed-off-by: Shirish S <shirish.s@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-17drm/amd/display: Wait for ACK for INBOX0 HW LockAlvin Lee5-3/+115
[Why] In DC we want to wait for the INBOX0 HW Lock command to ACK before continuing. This is to ensure that the lock has been successfully acquired before programming HW in DC. [How] Add interfaces to send messages on INBOX0, poll for their completation and clear the ack. Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-17drm/amd/display: Initialise encoder assignment when initialising dc_stateJimmy Kizito4-7/+7
[Why] Link encoder assignment tracking variables need to be (re)initialised whenever dc_state is (re)initialised. Otherwise variables used for dynamic encoder assignment (especially the link encoder availability pool) are out of sync with dc_state and future encoder assignments are invalid. [How] Initialise encoder assignment variables when creating new dc_state resource. Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-17drm/amd/display: Query all entries in assignment table during updates.Jimmy Kizito1-1/+12
[Why] Stream ordering and count can vary from one state to the next. Only checking a subset of entries in the encoder assignment table can lead to invalid encoder assignments. [How] Check all entries in encoder assignment table when querying it. Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-17drm/amd/display: To support sending TPS3 pattern when restoring linkRobin Chen3-3/+14
[Why] Some panels require to use TPS3 pattern to wake up link in PSR mode. [How] To add TPS3 selection information in PSR settings command and pass to DMUB FW. Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Robin Chen <po-tchen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-17drm/amd/display: 3.2.161Aric Cyr1-1/+1
This version brings along following fixes: - Improvements to INBOX0 HW Lock - Add support for sending TPS3 pattern - Fix Coverity Issues - Fixes for DMUB - Fix RGB MPO underflow with multiple displays - WS fixes and code restructure Acked-by: Anson Jacob <Anson.Jacob@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-17drm/amd/display: Adjust code indentationCharlene Liu1-3/+3
Reviewed-by: Sung joon Kim <Sungjoon.Kim@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-17drm/amd/display: Add hpd pending flag to indicate detection of new hpdMeenakshikumar Somasundaram3-13/+14
[Why] For dpia link, link->hpd_status indicates current state, but driver fails to capture hpd transitions in certain scenarios such as during link training. [How] Added link->hpd_pending flag that captures arrival of new hpd. Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-17drm/amd/display: Fix Coverity IssuesChris Park1-1/+5
[Why] Coverity discovers holes in logic that needs to be addressed for improved code integrity. [How] Address issues found by coverity without changing the actual logic. Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Chris Park <Chris.Park@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-17drm/amd/display: retain/release stream pointer in link enc tableSung Joon Kim1-0/+2
[why] At every reference to stream pointer, we need to increment/decrement the kref_count. Not doing so will result in invalid stream pointer still alive after hibernate cycle. [how] Call stream retain/release whenever the link encoder assignment is set to true/false since it indicates if we want to reference the stream pointer or not. Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Sung Joon Kim <sungkim@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-17drm/amd/display: fix stale info in link encoder assignmentRoy Chan1-22/+14
[Why] The link encoder assignment leaves the old stream data when it was unassigned. When the clear encoder assignment is called, it based on the old stale data to access the de-allocated stream. [How] There should be no need to explicitly clean up the link encoder assignment if the unassign loop does the work properly, the loop should base on the current state to clean up the assignment. Also, the unassignment should better clean up the values in the assignement slots as well. Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Roy Chan <roy.chan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-17drm/amd/display: use link_rate_set above DPCD 1.3 (#1527)Huang, ChiaWen1-1/+1
[Why & How] According to eDP spec, DPCD 1.3 is only for eDP DPCD v1.4 In dpcd_set_link_settings function, the driver is just above v1.3 Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: ChiawenHuang <chiawen.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-17drm/amd/display: clean up some formats and logCharlene Liu3-7/+3
[why] reduce az indirect register dump. need add az clock_gating control field used in some project. [how] conditional output indrect register in the log. add clock_gating feild Reviewed-by: Sung joon Kim <Sungjoon.Kim@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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