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path: root/drivers/gpu/drm/amd
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2020-07-01drm/amdgpu: support memory training for sienna_cichlidLikun Gao1-1/+3
Add memory training support for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: reserve fb according to return value from vbiosLikun Gao1-56/+71
Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc), otherwise, fallback to legacy approach to check and reserve tmr block for ip discovery data and G6 memory training data respectively Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: let PMFW to handle the features disablement on BACO in V2Evan Quan1-6/+18
For Sienna_Cichlid, PMFW will handle the features disablement on BACO in. No need to have driver stepped in. V2: limit this for baco really Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: drop sienna_cichlid hardcode of using pptableLikun Gao1-2/+1
Drop the hardcode of sienna_cichlid which will force to use softpptable, so that it can use pptable on vbios once the value of pp_table_id get from vbios is 0. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: update smu function for sienna_cichlidLikun Gao1-56/+45
Add function to check whether baco is support for sienna cichlid. Remove fucntion of get clock by type with latency as it will not be called. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: update golden setting for sienna_cichlidLikun Gao1-0/+2
Update golden setting for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu/psp: support for loading PSP SPL fwLikun Gao3-0/+46
Add support for loading SPL firmware. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu/psp: initialization PSP SPL fwLikun Gao2-0/+37
Support for psp firmware header version v1_3 initialization and information print. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu/psp: add structure to support PSP SPLLikun Gao2-0/+11
Add support for PSP SPL (Security patch level) table to support anti-rollback of FW loaded by Trusted OS. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: show gfxclk=0 in gfxoff stateKenneth Feng1-3/+4
The instant retrieved gfxclk value should be 0 in gfxoff state. This can be fetched with gfxoff enabled. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: enable gfxoff for sienna_cichlidLikun Gao3-3/+5
Enable GFXOFF for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/amdgpu: disable gfxoff to retrieve gfxclkLikun Gao1-11/+60
For Sienna_Cichlid, GFXOFF state puts gfx dpm into standby mode, then the gfxclk can't be retireved. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: support mclk socclk limit value set for sienna_cichlid.Likun Gao1-0/+4
Add support to force and unforce MCLK or SOCCLK to dpm limit value. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu/sriov : Add sriov detection for sienna_cichlidshaoyunl1-0/+1
This is a regression due to the rebase , add sienna_cichlid sriov detection back Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: only use one gfx pipe for Sienna_CichlidLikun Gao1-2/+2
Only enable one gfx pipe for sienna_cichlid currently. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: drop jpeg instance1 dpm setupLikun Gao1-6/+0
VCN removed JPEG for instance 1, so drop jpeg instance1 dpm setup. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: disable runtime pm for sienna_cichlid temporarilyLikun Gao1-0/+1
Disable runtime pm for sienna_cichlid temporarily as BACO regression issue. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: enable fw ctfKenneth Feng1-0/+1
fw ctf can be triggered if the temperature can't be throttled below the limit. then the gpu will be powered off and the whole system will hang. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: skip GPU scheduler setup for KIQ and MES ringLikun Gao1-1/+1
Fix the coding error to skip GPU scheduler setup for KIQ and MES ring. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: enable VDDCI and MVDD for sienna_cichlidLikun Gao1-1/+3
Enable VDDCI and MVDD if PP_MCLK_DPM_MASK was enable for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: append pptable for sienna_cichlid (v2)Likun Gao1-0/+101
Add function to append powerplay table from vbios for sienna_cichlid. v2: squash in warning fix Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: and smc dpm info struct for sienna_cichlidLikun Gao1-0/+123
And atom_smc_dpm_info_v4_9 struct for sienna_cichlid use. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu/sriov : Use kiq to do tlb invalidation for gfx10 on sriovshaoyunl2-0/+21
On SRIOV run time, driver shouldn't directly access invalidation registers through MMIO. Use kiq to submit wait_reg_mem package for the invalidation Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: enable ULCK DS for sienna_cichlidLikun Gao1-0/+1
Enable uclk deep sleep for sienna_cichlid. Df cstate kicks in first, then df triggers uclk ds with the sideband. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu/vcn3.0: schedule instance 0 for decode and 1 for encodeAlex Deucher1-0/+4
VCN3 has 2 unsymmetrical instances, i.e there're less codecs on instance 1, we use 0 for decode and 1 for encode for now Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu/mes10.1: add no scheduler flag for mesAlex Deucher1-0/+1
We don't want a gpu scheduler for mes. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: enable DPG mode for VCN3.0Boyuan Zhang2-2/+6
Enable DPG mode for VCN3.0 by updating related flag. V2: update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: add workaround for issue in DPG for VCN3.0Boyuan Zhang1-0/+4
To workaround an issue in DPG V2: update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: rename macro for VCN2.0 2.5 and 3.0Boyuan Zhang4-137/+137
Rename SOC15_DPG_MODE_OFFSET_2_0, RREG32_SOC15_DPG_MODE_2_0 and WREG32_SOC15_DPG_MODE_2_0 for VCN2.0, VCN2.5 and VCN3.0. These three macros are used VCN2.0, VCN2.5 and VCN3.0, therefore rename it to be a general name. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: rename macro for VCN1.0Boyuan Zhang2-50/+50
Rename RREG32_SOC15_DPG_MODE and WREG32_SOC15_DPG_MODE for VCN1.0 These two macros are used specifically for VCN1.0, therefore rename it from general name to VCN1.0 specific name. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: add internal reg offset translation for VCN inst 1Boyuan Zhang1-1/+13
Add range for vcn instance 1 for translation for internal register offset, which is needed for VCN3.0 V2: update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: set indirect sram mode for VCN3.0Boyuan Zhang1-0/+3
Use indirect sram for secure DPG mode V2: update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: add pause DPG mode for VCN3.0Boyuan Zhang1-0/+66
Add vcn_v3_0_pause_dpg_mode to pause/unpause DPG mode for VCN3.0 V2: update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: add stop DPG mode for VCN3.0Boyuan Zhang1-0/+34
Add vcn_v3_0_stop_dpg_mode to power off in DPG mode for VCN3.0 V2: update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: add start DPG mode for VCN3.0Boyuan Zhang1-0/+141
Add vcn_v3_0_start_dpg_mode to setup and start VCN block in DPG mode for VCN3.0 V2: Separate from previous patch-0002, and update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: add mc resume DPG mode for VCN3.0Boyuan Zhang1-0/+89
Add vcn_v3_0_mc_resume_dpg_mode to resume memory controller in DPG mode for VCN3.0 V2: Separate from previous patch-0002, and update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: add clock gating DPG mode for VCN3.0Boyuan Zhang1-0/+48
Add vcn_v3_0_clock_gating_dpg_mode to enabling clock gating in DPG mode for VCN3.0 V2: Separate from previous patch-0002, and update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/am/powerplay: enable OUT OF BAND MONITER for sienna_cichlidLikun Gao1-1/+2
Enable OUT OF BAND MONITER for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: enable RSMU SMN PG for sienna_cichlidLikun Gao1-0/+1
Enable RSMU SMN PG for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: update golden setting for sienna_cichlidLikun Gao1-1/+1
Update golden setting for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: bundle GPO with gfx DPMKenneth Feng1-1/+3
Bundle GPO with gfx DPM and enable it since gfxclk dpm should work first then GPO works. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: enable GPOKenneth Feng2-0/+2
GPO is graphics power optimizer. SMU calculates the 16 gfxclk V/F points according to the CU numbers and memory activity.RLC picks one of them according to the memory speed requirements for the data transmission. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: enable mmhub pgKenneth Feng2-1/+5
mmhub pg can be obvserved from PCTL_CTRL Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: enable athub pgKenneth Feng2-1/+5
enable athub pg and the status can be checked in ATHUB_MISC_CNTL. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: skip VM inv eng assignment for mes ringLe Ma1-0/+3
Statically allocated VM inv eng of gfxhub on sienna_cichlid is used up. Also VM inv eng is no need for mes ring. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu/mes: allocate memory slots for hw resource settingLe Ma1-0/+36
Pass a piece of memory to MES ucode to fill contents. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu/mes: add status fence memory definitionsLe Ma2-0/+5
Update for new member query_status_fence_gpu_mc_ptr in MESAPI_SET_HW_RESOURCES. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu/mes: update mes fw apiLe Ma1-288/+326
Update mes_api_def.h to match the latest mes fw. v2: clean up coding style based on kernel standards: - fix indentation and alignment - break long lines - put the opening brace last on the line - remove unnecessary blank line and space - replace uint(32|64) with standard uint(32|64)_t Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: add function to get power limit for sienna_cichlidLikun Gao1-0/+7
Add function to get pptable power limit for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: enable APCC DFLL for sienna_cichlidLikun Gao1-0/+2
Enable APCC DFLL for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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